From 52133392b277bf0afdd27c41501c155910b402c9 Mon Sep 17 00:00:00 2001 From: zhaohe Date: Sat, 14 Oct 2023 21:15:47 +0800 Subject: [PATCH] update --- .settings/stm32cubeide.project.prefs | 2 +- Core/Inc/stm32f4xx_it.h | 2 ++ Core/Src/dma.c | 6 +++++ Core/Src/stm32f4xx_it.c | 30 +++++++++++++++++++++++ Core/Src/usart.c | 42 ++++++++++++++++++++++++++++++++ Intelligent_winding_robot_main_board.ioc | 26 +++++++++++++++++++- 6 files changed, 106 insertions(+), 2 deletions(-) diff --git a/.settings/stm32cubeide.project.prefs b/.settings/stm32cubeide.project.prefs index 0435235..834c4e0 100644 --- a/.settings/stm32cubeide.project.prefs +++ b/.settings/stm32cubeide.project.prefs @@ -1,5 +1,5 @@ 635E684B79701B039C64EA45C3F84D30=6180EFBD1DA04EB1319C95830D4DB159 66BE74F758C12D739921AEA421D593D3=5 8DF89ED150041C4CBC7CB9A9CAA90856=C40676F5C274295C653AEC2EC599A69D -DC22A860405A8BF2F2C095E5B6529F12=6A0355D3636C06BA51C454D12FB4F7BB +DC22A860405A8BF2F2C095E5B6529F12=C40676F5C274295C653AEC2EC599A69D eclipse.preferences.version=1 diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h index 183dd56..ceb48fd 100644 --- a/Core/Inc/stm32f4xx_it.h +++ b/Core/Inc/stm32f4xx_it.h @@ -54,6 +54,8 @@ void UsageFault_Handler(void); void DebugMon_Handler(void); void DMA1_Stream1_IRQHandler(void); void DMA1_Stream3_IRQHandler(void); +void DMA1_Stream5_IRQHandler(void); +void DMA1_Stream6_IRQHandler(void); void CAN1_TX_IRQHandler(void); void CAN1_RX0_IRQHandler(void); void CAN1_RX1_IRQHandler(void); diff --git a/Core/Src/dma.c b/Core/Src/dma.c index 3d42cc3..ee8905e 100644 --- a/Core/Src/dma.c +++ b/Core/Src/dma.c @@ -49,6 +49,12 @@ void MX_DMA_Init(void) /* DMA1_Stream3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn); + /* DMA1_Stream5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); + /* DMA1_Stream6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); } diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c index 551bc63..4fe4406 100644 --- a/Core/Src/stm32f4xx_it.c +++ b/Core/Src/stm32f4xx_it.c @@ -59,6 +59,8 @@ extern CAN_HandleTypeDef hcan1; extern TIM_HandleTypeDef htim6; extern TIM_HandleTypeDef htim7; extern TIM_HandleTypeDef htim10; +extern DMA_HandleTypeDef hdma_usart2_rx; +extern DMA_HandleTypeDef hdma_usart2_tx; extern DMA_HandleTypeDef hdma_usart3_rx; extern DMA_HandleTypeDef hdma_usart3_tx; extern UART_HandleTypeDef huart1; @@ -195,6 +197,34 @@ void DMA1_Stream3_IRQHandler(void) } /** + * @brief This function handles DMA1 stream5 global interrupt. + */ +void DMA1_Stream5_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */ + + /* USER CODE END DMA1_Stream5_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_rx); + /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */ + + /* USER CODE END DMA1_Stream5_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream6 global interrupt. + */ +void DMA1_Stream6_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */ + + /* USER CODE END DMA1_Stream6_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart2_tx); + /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */ + + /* USER CODE END DMA1_Stream6_IRQn 1 */ +} + +/** * @brief This function handles CAN1 TX interrupts. */ void CAN1_TX_IRQHandler(void) diff --git a/Core/Src/usart.c b/Core/Src/usart.c index 89bb8bb..d3c3b7a 100644 --- a/Core/Src/usart.c +++ b/Core/Src/usart.c @@ -27,6 +27,8 @@ UART_HandleTypeDef huart1; UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; +DMA_HandleTypeDef hdma_usart2_rx; +DMA_HandleTypeDef hdma_usart2_tx; DMA_HandleTypeDef hdma_usart3_rx; DMA_HandleTypeDef hdma_usart3_tx; @@ -169,6 +171,43 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /* USART2 DMA Init */ + /* USART2_RX Init */ + hdma_usart2_rx.Instance = DMA1_Stream5; + hdma_usart2_rx.Init.Channel = DMA_CHANNEL_4; + hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_rx.Init.Mode = DMA_NORMAL; + hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx); + + /* USART2_TX Init */ + hdma_usart2_tx.Instance = DMA1_Stream6; + hdma_usart2_tx.Init.Channel = DMA_CHANNEL_4; + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_tx.Init.Mode = DMA_NORMAL; + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); + /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ @@ -273,6 +312,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + /* USART2 DMA DeInit */ + HAL_DMA_DeInit(uartHandle->hdmarx); + HAL_DMA_DeInit(uartHandle->hdmatx); /* USER CODE BEGIN USART2_MspDeInit 1 */ /* USER CODE END USART2_MspDeInit 1 */ diff --git a/Intelligent_winding_robot_main_board.ioc b/Intelligent_winding_robot_main_board.ioc index dbf12a7..9e81ea8 100644 --- a/Intelligent_winding_robot_main_board.ioc +++ b/Intelligent_winding_robot_main_board.ioc @@ -16,7 +16,29 @@ CAN1.SJW=CAN_SJW_3TQ CAN1.TTCM=ENABLE Dma.Request0=USART3_RX Dma.Request1=USART3_TX -Dma.RequestsNb=2 +Dma.Request2=USART2_RX +Dma.Request3=USART2_TX +Dma.RequestsNb=4 +Dma.USART2_RX.2.Direction=DMA_PERIPH_TO_MEMORY +Dma.USART2_RX.2.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART2_RX.2.Instance=DMA1_Stream5 +Dma.USART2_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_RX.2.MemInc=DMA_MINC_ENABLE +Dma.USART2_RX.2.Mode=DMA_NORMAL +Dma.USART2_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_RX.2.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_RX.2.Priority=DMA_PRIORITY_LOW +Dma.USART2_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.USART2_TX.3.Direction=DMA_MEMORY_TO_PERIPH +Dma.USART2_TX.3.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART2_TX.3.Instance=DMA1_Stream6 +Dma.USART2_TX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_TX.3.MemInc=DMA_MINC_ENABLE +Dma.USART2_TX.3.Mode=DMA_NORMAL +Dma.USART2_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_TX.3.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_TX.3.Priority=DMA_PRIORITY_LOW +Dma.USART2_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode Dma.USART3_RX.0.Direction=DMA_PERIPH_TO_MEMORY Dma.USART3_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE Dma.USART3_RX.0.Instance=DMA1_Stream1 @@ -90,6 +112,8 @@ NVIC.CAN1_SCE_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true NVIC.CAN1_TX_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DMA1_Stream5_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DMA1_Stream6_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false