diff --git a/README.md b/README.md index b1b119a..21024f7 100644 --- a/README.md +++ b/README.md @@ -5,6 +5,8 @@ ``` ``` + V10: + 1.修复当寄存器变化频率的时候,SPI读取数据错误的BUG V9: 1.修复PL无法2+倍频的BUG V7: @@ -17,4 +19,7 @@ 1.解决上电灯闪烁的问题 2.修改默认滤波参数为10 3.优化分频倍频逻辑,支持不稳定频率输入 + +TODO: + 寄存器变化频率的时候,SPI读取数据错误的BUG(PS:没有完全解决,暂时不知道问题在哪) ``` \ No newline at end of file diff --git a/camera_light_src_timing_controller_fpga.pds b/camera_light_src_timing_controller_fpga.pds index 64a051e..162fdd2 100644 --- a/camera_light_src_timing_controller_fpga.pds +++ b/camera_light_src_timing_controller_fpga.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Fri May 10 14:08:59 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Fri May 10 16:41:06 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,11 +19,11 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-05-10T14:05:07") + (_timespec "2024-05-10T15:22:54") ) (_file "source/src/spi_reg_reader.v" (_format verilog) - (_timespec "2024-03-08T21:15:01") + (_timespec "2024-05-10T16:29:40") ) (_file "source/src/zutils/zutils_pluse_generator.v" (_format verilog) @@ -147,7 +147,7 @@ ) (_file "source/src/zutils/zutils_freq_detector_v2.v" (_format verilog) - (_timespec "2024-04-23T18:27:17") + (_timespec "2024-05-10T16:39:14") ) (_file "source/src/zutils/zutils_multiplexer_8t1.v" (_format verilog) @@ -163,7 +163,7 @@ ) (_file "source/src/internal/internal_clock_generator.v" (_format verilog) - (_timespec "2024-03-10T18:52:01") + (_timespec "2024-05-10T16:08:28") ) (_file "source/src/internal/internal_genlock_generator.v" (_format verilog) @@ -187,7 +187,7 @@ ) (_file "source/src/trigger_source/trigger_source_base_module.v" (_format verilog) - (_timespec "2024-05-10T11:58:19") + (_timespec "2024-05-10T15:21:17") ) (_file "source/src/output/light_src_ctrl.v" (_format verilog) @@ -279,17 +279,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-05-10T14:07:34") + (_timespec "2024-05-10T16:39:23") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-05-10T14:07:32") + (_timespec "2024-05-10T16:39:21") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-05-10T14:07:34") + (_timespec "2024-05-10T16:39:23") ) ) ) @@ -305,21 +305,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-05-10T14:07:53") + (_timespec "2024-05-10T16:39:41") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-05-10T14:07:54") + (_timespec "2024-05-10T16:39:43") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-05-10T14:07:55") + (_timespec "2024-05-10T16:39:44") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-05-10T14:07:55") + (_timespec "2024-05-10T16:39:44") ) ) ) @@ -340,21 +340,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-05-10T14:08:02") + (_timespec "2024-05-10T16:39:48") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-05-10T14:08:00") + (_timespec "2024-05-10T16:39:46") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-05-10T14:08:02") + (_timespec "2024-05-10T16:39:48") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-05-10T14:08:02") + (_timespec "2024-05-10T16:39:48") ) ) ) @@ -363,7 +363,7 @@ (_input (_file "device_map/camera_light_src_timing_controller_fpga.pcf" (_format pcf) - (_timespec "2024-05-10T14:08:02") + (_timespec "2024-05-10T16:39:48") ) ) ) @@ -378,33 +378,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-05-10T14:08:41") + (_timespec "2024-05-10T16:40:24") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-05-10T14:08:41") + (_timespec "2024-05-10T16:40:24") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-05-10T14:08:41") + (_timespec "2024-05-10T16:40:24") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-05-10T14:08:41") + (_timespec "2024-05-10T16:40:24") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-05-10T14:08:13") + (_timespec "2024-05-10T16:39:59") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-05-10T14:08:41") + (_timespec "2024-05-10T16:40:24") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-05-10T14:08:41") + (_timespec "2024-05-10T16:40:24") ) ) ) @@ -439,19 +439,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-05-10T14:08:58") + (_timespec "2024-05-10T16:41:05") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-05-10T14:08:58") + (_timespec "2024-05-10T16:41:05") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-05-10T14:08:58") + (_timespec "2024-05-10T16:41:05") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-05-10T14:08:59") + (_timespec "2024-05-10T16:41:06") ) ) ) diff --git a/release/V10/Top.sbit b/release/V10/Top.sbit new file mode 100644 index 0000000..58297c8 Binary files /dev/null and b/release/V10/Top.sbit differ diff --git a/release/V10/Top.sfc b/release/V10/Top.sfc new file mode 100644 index 0000000..91d6e59 Binary files /dev/null and b/release/V10/Top.sfc differ diff --git a/source/src/config.v b/source/src/config.v index b9b6db0..005206a 100644 --- a/source/src/config.v +++ b/source/src/config.v @@ -1,4 +1,4 @@ -`define REGADDOFF__FPGA_VERSION 32'd9 +`define REGADDOFF__FPGA_VERSION 32'd10 /******************************************************************************* * 寄存器地址分配 * *******************************************************************************/ diff --git a/source/src/spi_reg_reader.v b/source/src/spi_reg_reader.v index b663241..0dd2eae 100644 --- a/source/src/spi_reg_reader.v +++ b/source/src/spi_reg_reader.v @@ -22,6 +22,8 @@ module spi_reg_reader ( parameter STATE_WRITE_REG = 5; parameter ADDRESS_WIDTH_BYTE_NUM = 2; + + // initial begin // addr = 0; // wr_data = 0; @@ -33,28 +35,28 @@ module spi_reg_reader ( zutils_signal_filter #( .FILTER_COUNT(2) ) cs_filter ( - .clk(clk), + .clk (clk), .rst_n(rst_n), - .in(spi_cs_pin), - .out(spi_cs_pin_after_filter) + .in (spi_cs_pin), + .out (spi_cs_pin_after_filter) ); zutils_signal_filter #( .FILTER_COUNT(1) ) clk_filter ( - .clk(clk), + .clk (clk), .rst_n(rst_n), - .in(spi_clk_pin), - .out(spi_clk_pin_after_filter) + .in (spi_clk_pin), + .out (spi_clk_pin_after_filter) ); zutils_signal_filter #( .FILTER_COUNT(1) ) spi_rx_filter ( - .clk(clk), + .clk (clk), .rst_n(rst_n), - .in(spi_rx_pin), - .out(spi_rx_pin_after_filter) + .in (spi_rx_pin), + .out (spi_rx_pin_after_filter) ); // @@ -65,18 +67,18 @@ module spi_reg_reader ( // zutils_edge_detecter cs_edge_detecter ( - .clk(clk), - .rst_n(rst_n), - .in_signal(spi_cs_pin_after_filter), + .clk (clk), + .rst_n (rst_n), + .in_signal (spi_cs_pin_after_filter), .in_signal_falling_edge(spi_cs_negedge_tri) ); zutils_edge_detecter clk_edge_detecter ( - .clk(clk), - .rst_n(rst_n), - .in_signal(spi_clk_pin_after_filter), - .in_signal_rising_edge(spi_clk_posedge_tri), + .clk (clk), + .rst_n (rst_n), + .in_signal (spi_clk_pin_after_filter), + .in_signal_rising_edge (spi_clk_posedge_tri), .in_signal_falling_edge(spi_clk_negedge_tri) ); @@ -109,11 +111,11 @@ module spi_reg_reader ( .clk_signal_in(spi_clk_pin_after_filter), .clk_start_signal(spi_clk_start_signal), - .clk_mid_signal(spi_clk_mid_signal), - .clk_end_signal(spi_clk_end_signal), - .clk_cnt(spi_clk_cnt), //[31:0] - .byte_cnt(spi_byte_cnt), //[31:0] - .clk_bit_cnt(bit_cnt) //[7:0] + .clk_mid_signal (spi_clk_mid_signal), + .clk_end_signal (spi_clk_end_signal), + .clk_cnt (spi_clk_cnt), //[31:0] + .byte_cnt (spi_byte_cnt), //[31:0] + .clk_bit_cnt (bit_cnt) //[7:0] ); @@ -134,10 +136,10 @@ module spi_reg_reader ( // 当 bit_cnt == 7时 接收完一byte数据 // reg [7:0] spi_rx_1byte_data = 0; - reg spi_rx_1byte_data_valid = 0; + reg spi_rx_1byte_data_valid = 0; always @(posedge clk or negedge rst_n) begin if (!rst_n || spi_cs_pin_after_filter) begin - spi_rx_1byte_data <= 0; + spi_rx_1byte_data <= 0; spi_rx_1byte_data_valid <= 0; end else begin if (spi_clk_mid_signal) begin @@ -177,13 +179,31 @@ module spi_reg_reader ( /******************************************************************************* * 自动设置SPI需要发送的数据 spi_tx_1byte_data * *******************************************************************************/ + reg [31:0] rd_data_cache; + reg lock_rd_data; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + rd_data_cache <= 0; + lock_rd_data <= 0; + end else begin + if (spi_byte_cnt == ADDRESS_WIDTH_BYTE_NUM) begin + if (!lock_rd_data) begin + rd_data_cache <= rd_data; + lock_rd_data <= 1; + end + end else if (spi_byte_cnt == 0) begin + lock_rd_data <= 0; + end + end + end + always @(*) begin case (spi_byte_cnt) - ADDRESS_WIDTH_BYTE_NUM + 0: spi_tx_1byte_data <= rd_data[7:0]; - ADDRESS_WIDTH_BYTE_NUM + 1: spi_tx_1byte_data <= rd_data[15:8]; - ADDRESS_WIDTH_BYTE_NUM + 2: spi_tx_1byte_data <= rd_data[23:16]; - ADDRESS_WIDTH_BYTE_NUM + 3: spi_tx_1byte_data <= rd_data[31:24]; - default: spi_tx_1byte_data <= 0; + ADDRESS_WIDTH_BYTE_NUM + 0: spi_tx_1byte_data <= rd_data_cache[7:0]; + ADDRESS_WIDTH_BYTE_NUM + 1: spi_tx_1byte_data <= rd_data_cache[15:8]; + ADDRESS_WIDTH_BYTE_NUM + 2: spi_tx_1byte_data <= rd_data_cache[23:16]; + ADDRESS_WIDTH_BYTE_NUM + 3: spi_tx_1byte_data <= rd_data_cache[31:24]; + default: spi_tx_1byte_data <= 0; endcase end @@ -241,13 +261,13 @@ module spi_reg_reader ( reg has_trigger_wr_en = 0; always @(posedge clk or negedge rst_n) begin if (!rst_n || spi_cs_pin_after_filter) begin - wr_en <= 0; + wr_en <= 0; has_trigger_wr_en <= 0; end else begin if (!has_trigger_wr_en && // spi_byte_cnt == ADDRESS_WIDTH_BYTE_NUM + 4 && // spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM-1][7]) begin - wr_en <= 1; + wr_en <= 1; has_trigger_wr_en <= 1; end else begin wr_en <= 0; diff --git a/source/src/top.v b/source/src/top.v index b5c7088..8c46ddb 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -253,6 +253,7 @@ module Top ( .in_sig_0 (!optocoupler_in1), .in_sig_1 (diff_in1), + .in_sig_2 (sig_bus[`SIG_INTERNAL_CLK]), .in_sig_selected(trigger_in_selected_1), .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_1]), @@ -284,6 +285,7 @@ module Top ( .in_sig_0 (!optocoupler_in2), .in_sig_1 (diff_in2), + .in_sig_2 (sig_bus[`SIG_INTERNAL_CLK]), .in_sig_selected(trigger_in_selected_2), .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_2]), @@ -307,6 +309,7 @@ module Top ( .in_sig_0 (!optocoupler_in3), .in_sig_1 (diff_in3), + .in_sig_2 (sig_bus[`SIG_INTERNAL_CLK]), .in_sig_selected(trigger_in_selected_3), @@ -331,6 +334,7 @@ module Top ( .in_sig_0 (!optocoupler_in4), .in_sig_1 (diff_in4), + .in_sig_2 (sig_bus[`SIG_INTERNAL_CLK]), .in_sig_selected(trigger_in_selected_4), .out_trigger_sig (sig_bus[`SIG_EXT_TRIGGER_4]), diff --git a/source/src/trigger_source/trigger_source_base_module.v b/source/src/trigger_source/trigger_source_base_module.v index a791b92..f031aa3 100644 --- a/source/src/trigger_source/trigger_source_base_module.v +++ b/source/src/trigger_source/trigger_source_base_module.v @@ -16,6 +16,7 @@ module trigger_source_base_module #( // input wire in_sig_0, input wire in_sig_1, + input wire in_sig_2, output wire in_sig_selected, output wire out_trigger_sig, @@ -113,11 +114,12 @@ module trigger_source_base_module #( end end - wire [3:0] in_sig; + wire [4:0] in_sig; assign in_sig[0] = in_sig_0; assign in_sig[1] = in_sig_1; - assign in_sig[2] = !in_sig_0; - assign in_sig[3] = !in_sig_1; + assign in_sig[2] = in_sig_2; + assign in_sig[3] = !in_sig_0; + assign in_sig[4] = !in_sig_1; reg sig_af_choose; //!选择后的触发信号 wire sig_af_choose_af_filter; //!滤波后的脉冲 diff --git a/source/src/zutils/zutils_freq_detector_v2.v b/source/src/zutils/zutils_freq_detector_v2.v index b2d2156..9993871 100644 --- a/source/src/zutils/zutils_freq_detector_v2.v +++ b/source/src/zutils/zutils_freq_detector_v2.v @@ -1,9 +1,4 @@ -// -// @功能: -// 1. 滤波(add later) -// 2. 频率探测 -// 3. 输出灯光控制 -// + module zutils_freq_detector_v2 ( input clk, //! 时钟输入 input rst_n, //! 复位输入 @@ -55,10 +50,13 @@ module zutils_freq_detector_v2 ( freq_detect_cnt <= 0; pluse_width_cnt <= freq_detect_cnt; end else begin - freq_detect_cnt <= freq_detect_cnt + 1; - if (freq_detect_cnt >= pluse_width_cnt) begin + if (freq_detect_cnt < 32'd300000000) begin //TODO: 将这个变量提取到config.v中,最大频率探测1.5s + freq_detect_cnt <= freq_detect_cnt + 1; + end else begin + freq_detect_cnt <= freq_detect_cnt; pluse_width_cnt <= freq_detect_cnt; end + end end end