11 changed files with 629 additions and 389 deletions
-
114camera_light_src_timing_controller_fpga.pds
-
68source/src/config.v
-
77source/src/spi_reg_bus.v
-
116source/src/sys/sys_clock.v
-
81source/src/sys/sys_genlock.v
-
93source/src/sys/sys_timecode.v
-
160source/src/top.v
-
0source/src/trigger_source/handler_trigger_source.v
-
130source/src/trigger_source/trigger_source_base_module.v
-
0source/src/trigger_source/ttl_trigger_source.v
-
179source/src/zutils/zutils_debug_pwm_generator.v
@ -1,38 +1,38 @@ |
|||
`define REGADDOFF__FPGA_INFO 16'h0020 |
|||
`define REGADDOFF__TTLIN 16'h0100 |
|||
`define REGADDOFF__TIMECODE_IN 16'h0120 |
|||
`define REGADDOFF__GENLOCK_IN 16'h0130 |
|||
`define REGADDOFF__INTERNAL_TIMECODE 16'h0300 |
|||
`define REGADDOFF__INTERNAL_GENLOCK 16'h0310 |
|||
`define REGADDOFF__INTERNAL_CLOCK 16'h0320 |
|||
`define REGADDOFF__TTLOUT1 16'h0200 |
|||
`define REGADDOFF__TTLOUT2 16'h0210 |
|||
`define REGADDOFF__TTLOUT3 16'h0220 |
|||
`define REGADDOFF__TTLOUT4 16'h0230 |
|||
`define REGADDOFF__TIMECODE_OUT 16'h0240 |
|||
`define REGADDOFF__GENLOCK_OUT 16'h0250 |
|||
`define REGADDOFF__CAMERA_SYNC_OUT 16'h0260 |
|||
`define REGADDOFF__SYS_TIMECODE 16'h0400 |
|||
`define REGADDOFF__SYS_GENLOCK 16'h0410 |
|||
`define REGADDOFF__SYS_CLOCK 16'h0420 |
|||
`define REGADDOFF__RECORD_SIG_GENERATOR 16'h0500 |
|||
`define REGADDOFF__FPGA_VERSION 32'd1 |
|||
/******************************************************************************* |
|||
* 寄存器地址分配 * |
|||
*******************************************************************************/ |
|||
`define REGADDOFF__FPGA_INFO 16'h1000 |
|||
`define REGADDOFF__INTERNAL_TRIGGER 16'h1020 |
|||
|
|||
`define REGADDOFF__TRIGGER_IN0 16'h2000 |
|||
`define REGADDOFF__TRIGGER_IN1 16'h2020 |
|||
`define REGADDOFF__TRIGGER_IN2 16'h2040 |
|||
`define REGADDOFF__TRIGGER_IN3 16'h2060 |
|||
|
|||
`define REGADDOFF__LIGHT_CTROL_MODULE0 16'h3000 |
|||
`define REGADDOFF__LIGHT_CTROL_MODULE1 16'h3020 |
|||
`define REGADDOFF__LIGHT_CTROL_MODULE2 16'h3040 |
|||
`define REGADDOFF__LIGHT_CTROL_MODULE3 16'h3060 |
|||
|
|||
`define REGADDOFF__TTL_OUTPUT_MODULE0 16'h4000 |
|||
`define REGADDOFF__TTL_OUTPUT_MODULE1 16'h4020 |
|||
`define REGADDOFF__TTL_OUTPUT_MODULE2 16'h4040 |
|||
`define REGADDOFF__TTL_OUTPUT_MODULE3 16'h4060 |
|||
|
|||
/******************************************************************************* |
|||
* 部分寄存器初始化数值 * |
|||
*******************************************************************************/ |
|||
`define FREQ_DETECT_BIAS_DEFAULT 32'd10 |
|||
`define FREQ_TTL_INPUT_FILTER 32'd10 |
|||
|
|||
`define SIGNAL_LOGIC0 32'd0 |
|||
`define SIGNAL_LOGIC1 32'd1 |
|||
`define SIGNAL_TTLIN1 32'd2 |
|||
`define SIGNAL_TTLIN2 32'd3 |
|||
`define SIGNAL_TTLIN3 32'd4 |
|||
`define SIGNAL_TTLIN4 32'd5 |
|||
`define SIGNAL_EXT_GENLOCK_FREQ 32'd6 |
|||
`define SIGNAL_EXT_TIMECODE_FREQ 32'd7 |
|||
`define SIGNAL_INTERNAL_TIMECODE_FREQ 32'd8 |
|||
`define SIGNAL_INTERNAL_GENLOCK_FREQ 32'd9 |
|||
`define SIGNAL_INTERNAL_CLOCK_SIG 32'd10 |
|||
`define SIGNAL_SYS_CLK_OUTPUT 32'd11 |
|||
`define SIGNAL_SYS_GENLOCK_OUTPUT 32'd12 |
|||
`define SIGNAL_SYS_TIMECODE_FREQ_OUTPUT 32'd13 |
|||
`define SIGNAL_BUSINESS_RECORD_SIG 32'd14 |
|||
`define SIGNAL_BUSINESS_RECORD_EXPOSURE_SIG 32'd15 |
|||
/******************************************************************************* |
|||
* 公共信号ID * |
|||
*******************************************************************************/ |
|||
`define SIG_LOGIC0 32'd0 |
|||
`define SIG_LOGIC1 32'd1 |
|||
`define SIG_EXT_TRIGGER_SIG_1 32'd2 |
|||
`define SIG_EXT_TRIGGER_SIG_2 32'd3 |
|||
`define SIG_EXT_TRIGGER_SIG_3 32'd4 |
|||
`define SIG_EXT_TRIGGER_SIG_4 32'd5 |
|||
`define SIG_INTERNAL_TRIGGER_SIG_0 32'd2 |
|||
@ -1,116 +0,0 @@ |
|||
`include "../config.v" |
|||
module sys_clock #( |
|||
parameter REG_START_ADD = 0, |
|||
parameter SYS_CLOCK_FREQ = 10000000 |
|||
) ( |
|||
input clk, //clock input |
|||
input rst_n, //asynchronous reset input, low active |
|||
|
|||
//寄存器读写接口 |
|||
input [31:0] addr, |
|||
input [31:0] wr_data, |
|||
input wr_en, |
|||
output wire [31:0] rd_data, |
|||
|
|||
input [31:0] signal_in, |
|||
output sys_clock |
|||
); |
|||
|
|||
/******************************************************************************* |
|||
* 寄存器列表 * |
|||
*******************************************************************************/ |
|||
reg [31:0] reg1_sig_src; //!信号源选择 |
|||
reg [31:0] reg2_freq_division_ctrl; //!分频控制 |
|||
reg [31:0] reg3_freq_multiplication_ctrl; //!倍频控制 |
|||
reg [31:0] reg4_freq_detect_bias; //!频率探测滤波系数 |
|||
reg [31:0] reg5_trigger_edge_select; //!触发电平 |
|||
wire [31:0] regE_infreq_detect; //!输入频率探测 |
|||
wire [31:0] regF_outfreq_detect; //!输出频率探测 |
|||
|
|||
wire [31:0] reg_wr_index; //!寄存器写入时相对地址 |
|||
wire signal_in_choose; //!选择的信号源 |
|||
wire signal_in_af_pll; |
|||
|
|||
|
|||
//!TTLOUT_寄存器自动赋值选择器 |
|||
zutils_register_advanced #( |
|||
.REG_START_ADD(REG_START_ADD) |
|||
) _register ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.addr (addr), |
|||
.wr_data(wr_data), |
|||
.wr_en (wr_en), |
|||
.rd_data(rd_data), |
|||
.reg1 (reg1_sig_src), |
|||
.reg2 (reg2_freq_division_ctrl), |
|||
.reg3 (reg3_freq_multiplication_ctrl), |
|||
.reg4 (reg4_freq_detect_bias), |
|||
|
|||
.regE (regE_infreq_detect), |
|||
.regF (regF_outfreq_detect), |
|||
.reg_wr_sig(reg_wr_sig), |
|||
.reg_index (reg_wr_index) |
|||
); |
|||
|
|||
//!寄存器写入逻辑 |
|||
always @(posedge clk or negedge rst_n) begin |
|||
if (!rst_n) begin |
|||
|
|||
reg1_sig_src <= `SIGNAL_INTERNAL_CLOCK_SIG; //!默认为内部时钟 |
|||
reg2_freq_division_ctrl <= 0; |
|||
reg3_freq_multiplication_ctrl <= 0; |
|||
reg4_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; |
|||
end else begin |
|||
if (reg_wr_sig) begin |
|||
case (reg_wr_index) |
|||
1: reg1_sig_src <= wr_data; |
|||
2: reg2_freq_division_ctrl <= wr_data; |
|||
3: reg3_freq_multiplication_ctrl <= wr_data; |
|||
4: reg4_freq_detect_bias <= wr_data; |
|||
default: begin |
|||
end |
|||
endcase |
|||
end |
|||
end |
|||
end |
|||
|
|||
//!信号选择器 |
|||
zutils_multiplexer_32t1 signal_in_multiplexer ( |
|||
.chooseindex(reg1_sig_src), |
|||
.signal (signal_in), |
|||
.signalout (signal_in_choose) |
|||
); |
|||
|
|||
//!pll信号处理 |
|||
zsimple_pll _simple_pll ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.insignal (signal_in_choose), |
|||
.trigger_eage_type (reg5_trigger_edge_select[0]), |
|||
.freq_detect_bias (reg4_freq_detect_bias), |
|||
.freq_division (reg2_freq_division_ctrl), |
|||
.freq_multiplication(reg3_freq_multiplication_ctrl), |
|||
.polarity_ctrl (1'd0), |
|||
.cfg_change (reg_wr_sig), |
|||
.outsignal (signal_in_af_pll) |
|||
); |
|||
|
|||
zutils_freq_detector_v2 in_freq_detector ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.freq_detect_bias(reg4_freq_detect_bias), |
|||
.pluse_input (signal_in_choose), |
|||
.pluse_width_cnt (regE_infreq_detect) |
|||
); |
|||
|
|||
zutils_freq_detector_v2 output_freq_detector ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.freq_detect_bias(reg4_freq_detect_bias), |
|||
.pluse_input (sys_clock), |
|||
.pluse_width_cnt (regF_outfreq_detect) |
|||
); |
|||
assign sys_clock = signal_in_af_pll; |
|||
|
|||
endmodule |
|||
@ -1,81 +0,0 @@ |
|||
`include "../config.v" |
|||
module sys_genlock #( |
|||
parameter REG_START_ADD = 0, |
|||
parameter SYS_CLOCK_FREQ = 10000000 |
|||
) ( |
|||
input clk, //clock input |
|||
input rst_n, //asynchronous reset input, low active |
|||
|
|||
//寄存器读写接口 |
|||
input [31:0] addr, |
|||
input [31:0] wr_data, |
|||
input wr_en, |
|||
output wire [31:0] rd_data, |
|||
|
|||
input internal_genlock_sig, |
|||
input external_genlock_sig, |
|||
|
|||
output reg sys_genlock_tigger_sig |
|||
); |
|||
|
|||
/******************************************************************************* |
|||
* 寄存器列表 * |
|||
*******************************************************************************/ |
|||
reg [31:0] reg1_sig_src; //!信号源选择 |
|||
reg [31:0] reg2_genlock_freq_detect_bias; //!频率探测滤波参数 |
|||
wire [31:0] reg3_sig_freq; //!信号源频率 |
|||
|
|||
wire [31:0] reg_wr_index; //!寄存器写入时相对地址 |
|||
|
|||
//!TTLOUT_寄存器自动赋值选择器 |
|||
zutils_register_advanced #( |
|||
.REG_START_ADD(REG_START_ADD) |
|||
) _register ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.addr (addr), |
|||
.wr_data (wr_data), |
|||
.wr_en (wr_en), |
|||
.rd_data (rd_data), |
|||
.reg1 (reg1_sig_src), |
|||
.reg2 (reg2_genlock_freq_detect_bias), |
|||
.reg3 (reg3_sig_freq), |
|||
.reg_wr_sig(reg_wr_sig), |
|||
.reg_index (reg_wr_index) |
|||
); |
|||
|
|||
//!寄存器写入逻辑 |
|||
always @(posedge clk or negedge rst_n) begin |
|||
if (!rst_n) begin |
|||
reg1_sig_src <= 0; |
|||
reg2_genlock_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; |
|||
end else begin |
|||
if (reg_wr_sig) begin |
|||
case (reg_wr_index) |
|||
1: reg1_sig_src <= wr_data; |
|||
2: reg2_genlock_freq_detect_bias <= wr_data; |
|||
default: begin |
|||
end |
|||
endcase |
|||
end |
|||
end |
|||
end |
|||
|
|||
always @(*) begin |
|||
if (!reg1_sig_src[0]) begin |
|||
sys_genlock_tigger_sig <= internal_genlock_sig; |
|||
end else begin |
|||
sys_genlock_tigger_sig <= external_genlock_sig; |
|||
end |
|||
end |
|||
|
|||
zutils_freq_detector_v2 freq_detector1 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.freq_detect_bias(reg2_genlock_freq_detect_bias), |
|||
.pluse_input (sys_genlock_tigger_sig), |
|||
.pluse_width_cnt (reg3_sig_freq) |
|||
); |
|||
|
|||
|
|||
endmodule |
|||
@ -1,93 +0,0 @@ |
|||
module sys_timecode #( |
|||
parameter REG_START_ADD = 0, |
|||
parameter SYS_CLOCK_FREQ = 10000000 |
|||
) ( |
|||
input clk, //clock input |
|||
input rst_n, //asynchronous reset input, low active |
|||
|
|||
//寄存器读写接口 |
|||
input [31:0] addr, |
|||
input [31:0] wr_data, |
|||
input wr_en, |
|||
output wire [31:0] rd_data, |
|||
|
|||
input internal_timecode_tigger_sig, |
|||
input [31:0] internal_timecode_format, |
|||
input [63:0] internal_timecode_data, |
|||
input internal_timecode_serial_data, |
|||
|
|||
input external_timecode_tigger_sig, |
|||
input [31:0] external_timecode_format, |
|||
input [63:0] external_timecode_data, |
|||
input external_timecode_serial_data, |
|||
|
|||
output reg sys_timecode_tigger_sig, |
|||
output reg [31:0] sys_timecode_format, |
|||
output reg [63:0] sys_timecode_data, |
|||
output reg sys_timecode_serial_data |
|||
|
|||
); |
|||
|
|||
/******************************************************************************* |
|||
* 寄存器列表 * |
|||
*******************************************************************************/ |
|||
reg [31:0] reg1_sys_timecode_selecter; //!内部时码使能控制 |
|||
wire [31:0] reg2_sys_timecode_format; //!内部时码格式 |
|||
wire [31:0] reg3_sys_timecode_data0; //!时码数值0 |
|||
wire [31:0] reg4_sys_timecode_data1; //!时码数值1 |
|||
wire [31:0] reg_wr_index; //!寄存器写入时相对地址 |
|||
|
|||
//!TTLOUT_寄存器自动赋值选择器 |
|||
zutils_register_advanced #( |
|||
.REG_START_ADD(REG_START_ADD) |
|||
) _register ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.addr (addr), |
|||
.wr_data (wr_data), |
|||
.wr_en (wr_en), |
|||
.rd_data (rd_data), |
|||
.reg1 (reg1_sys_timecode_selecter), |
|||
.reg2 (reg2_sys_timecode_format), |
|||
.reg3 (reg3_sys_timecode_data0), |
|||
.reg4 (reg4_sys_timecode_data1), |
|||
.reg_wr_sig(reg_wr_sig), |
|||
.reg_index (reg_wr_index) |
|||
); |
|||
|
|||
//!寄存器写入逻辑 |
|||
always @(posedge clk or negedge rst_n) begin |
|||
if (!rst_n) begin |
|||
reg1_sys_timecode_selecter <= 0; |
|||
end else begin |
|||
if (reg_wr_sig) begin |
|||
case (reg_wr_index) |
|||
1: reg1_sys_timecode_selecter <= wr_data; |
|||
default: begin |
|||
end |
|||
endcase |
|||
end |
|||
end |
|||
end |
|||
|
|||
always @(*) begin |
|||
if (!reg1_sys_timecode_selecter[0]) begin |
|||
sys_timecode_tigger_sig <= internal_timecode_tigger_sig; |
|||
sys_timecode_format <= internal_timecode_format; |
|||
sys_timecode_data <= internal_timecode_data; |
|||
sys_timecode_serial_data <= internal_timecode_serial_data; |
|||
end else begin |
|||
sys_timecode_tigger_sig <= external_timecode_tigger_sig; |
|||
sys_timecode_format <= external_timecode_format; |
|||
sys_timecode_data <= external_timecode_data; |
|||
sys_timecode_serial_data <= external_timecode_serial_data; |
|||
end |
|||
end |
|||
|
|||
assign reg2_sys_timecode_format = sys_timecode_format; |
|||
assign reg3_sys_timecode_data0 = sys_timecode_data[31:0]; |
|||
assign reg4_sys_timecode_data1 = sys_timecode_data[63:32]; |
|||
|
|||
|
|||
|
|||
endmodule |
|||
@ -0,0 +1,130 @@ |
|||
`include "../config.v" |
|||
module trigger_source_base_module #( |
|||
parameter REG_START_ADD = 0, |
|||
parameter SYS_CLOCK_FREQ = 10000000 |
|||
) ( |
|||
|
|||
input clk, //! 时钟输入 |
|||
input rst_n, //! 复位输入 |
|||
|
|||
input [31:0] addr, //! 寄存器地址 |
|||
input [31:0] wr_data, //! 写入数据 |
|||
input wr_en, //! 写使能 |
|||
output wire [31:0] rd_data, //! 读出数据 |
|||
|
|||
// |
|||
input wire [1:0] in_sig, |
|||
|
|||
output wire [16:0] out_trigger_index_sig, |
|||
output wire out_trigger_sig |
|||
); |
|||
|
|||
reg [31:0] reg1_src_slect; //!信号源选择 |
|||
reg [31:0] reg2_fileter_coefficient; //!滤波系数 |
|||
reg [31:0] reg3_flag; //! 0:PLL使能标志位 |
|||
reg [31:0] reg4_trigger_edge; //!触发边沿 |
|||
reg [31:0] reg5_freq_detect_bias; //!脉冲频率探测误差 |
|||
reg [31:0] reg6_pll_freq_division; //!频率分频 |
|||
reg [31:0] reg7_pll_freq_multiplication; //!频率倍频 |
|||
reg [31:0] reg9_sequential_control_pluse_cnt_max; //!顺序控制脉冲最大计数 |
|||
reg [31:0] regE_in_signal_freq; //!输入脉冲频率 |
|||
reg [31:0] regF_out_signal_freq; //!输出脉冲频率 |
|||
|
|||
wire [31:0] reg_wr_index; |
|||
zutils_register_advanced #( |
|||
.REG_START_ADD(REG_START_ADD) |
|||
) _register ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.addr (addr), |
|||
.wr_data(wr_data), |
|||
.wr_en (wr_en), |
|||
.rd_data(rd_data), |
|||
|
|||
.reg1(reg1_src_slect), |
|||
.reg2(reg2_fileter_coefficient), |
|||
.reg3(reg3_flag), |
|||
.reg4(reg4_trigger_edge), |
|||
.reg5(reg5_freq_detect_bias), |
|||
.reg6(reg6_pll_freq_division), |
|||
.reg7(reg7_pll_freq_multiplication), |
|||
.reg9(reg9_sequential_control_pluse_cnt_max), |
|||
|
|||
.regE(regE_in_signal_freq), |
|||
.regF(regF_out_signal_freq), |
|||
|
|||
.reg_wr_sig(reg_wr_sig), |
|||
.reg_index (reg_wr_index) |
|||
); |
|||
|
|||
always @(posedge clk or negedge rst_n) begin |
|||
if (!rst_n) begin |
|||
reg1_src_slect <= 0; |
|||
reg2_fileter_coefficient <= `FREQ_TTL_INPUT_FILTER; |
|||
reg3_flag <= 0; |
|||
reg4_trigger_edge <= 0; |
|||
reg5_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; |
|||
reg6_pll_freq_division <= 0; |
|||
reg7_pll_freq_multiplication <= 0; |
|||
reg9_sequential_control_pluse_cnt_max <= 0; |
|||
end else begin |
|||
if (reg_wr_sig) begin |
|||
case (reg_wr_index) |
|||
1: reg1_src_slect <= wr_data; |
|||
2: reg2_fileter_coefficient <= wr_data; |
|||
3: reg3_flag <= wr_data; |
|||
4: reg4_trigger_edge <= wr_data; |
|||
5: reg5_freq_detect_bias <= wr_data; |
|||
6: reg6_pll_freq_division <= wr_data; |
|||
7: reg7_pll_freq_multiplication <= wr_data; |
|||
9: reg9_sequential_control_pluse_cnt_max <= wr_data; |
|||
default: begin |
|||
end |
|||
endcase |
|||
end |
|||
end |
|||
end |
|||
|
|||
|
|||
reg signal_in_choose; //!选择后的触发信号 |
|||
reg insig_after_pll; //!pll处理过后的信号 |
|||
reg signal_out_final; //!最终输出的信号 |
|||
|
|||
always @(*) begin |
|||
if (reg1_src_slect <= 1) begin |
|||
signal_in_choose = in_sig[reg1_src_slect]; |
|||
end else begin |
|||
signal_in_choose = 0; |
|||
end |
|||
end |
|||
|
|||
zsimple_pll _simple_pll ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.insignal (signal_in_choose), |
|||
.trigger_eage_type (reg4_trigger_edge[0]), |
|||
.freq_detect_bias (reg5_freq_detect_bias), |
|||
.freq_division (reg6_pll_freq_division), |
|||
.freq_multiplication(reg7_pll_freq_multiplication), |
|||
.polarity_ctrl (32'd1), |
|||
.cfg_change (reg_wr_sig), |
|||
.outsignal (signal_in_af_pll) |
|||
); |
|||
|
|||
zutils_freq_detector_v2 freq_detector1 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.freq_detect_bias(reg5_freq_detect_bias), |
|||
.pluse_input (ttlin1_sig_af_filter), |
|||
.pluse_width_cnt (r2_ttlin1_freq_detector) |
|||
); |
|||
|
|||
zutils_freq_detector_v2 freq_detector2 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.freq_detect_bias(reg5_freq_detect_bias), |
|||
.pluse_input (ttlin2_sig_af_filter), |
|||
.pluse_width_cnt (r3_ttlin2_freq_detector) |
|||
); |
|||
|
|||
endmodule |
|||
@ -0,0 +1,179 @@ |
|||
module zutils_debug_pwm_generator #( |
|||
parameter SYS_CLOCK_FREQ = 10000000 |
|||
) ( |
|||
input clk, |
|||
input rst_n, |
|||
output wire pwm100hz, |
|||
output wire pwm101hz, |
|||
output wire pwm102hz, |
|||
output wire pwm103hz, |
|||
output wire pwm104hz, |
|||
output wire pwm105hz, |
|||
output wire pwm106hz, |
|||
output wire pwm107hz, |
|||
output wire pwm108hz, |
|||
output wire pwm109hz, |
|||
output wire pwm110hz, |
|||
output wire pwm111hz, |
|||
output wire pwm112hz, |
|||
output wire pwm113hz, |
|||
output wire pwm114hz, |
|||
output wire pwm115hz |
|||
); |
|||
|
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(100 * 100) //10.00HZ |
|||
) pwm0 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm100hz) |
|||
); |
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(101 * 100) //10.10HZ |
|||
) pwm1 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm101hz) |
|||
); |
|||
|
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(102 * 100) //10.20HZ |
|||
) pwm2 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm102hz) |
|||
); |
|||
|
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(103 * 100) //10.30HZ |
|||
) pwm3 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm103hz) |
|||
); |
|||
|
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(104 * 100) //10.40HZ |
|||
) pwm4 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm104hz) |
|||
); |
|||
|
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(105 * 100) //10.50HZ |
|||
) pwm5 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm105hz) |
|||
); |
|||
|
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(106 * 100) //10.60HZ |
|||
) pwm6 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm106hz) |
|||
); |
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(107 * 100) //10.70HZ |
|||
) pwm7 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm107hz) |
|||
); |
|||
|
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(108 * 100) //10.80HZ |
|||
) pwm8 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm108hz) |
|||
); |
|||
|
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(109 * 100) //10.90HZ |
|||
) pwm9 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm109hz) |
|||
); |
|||
|
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(110 * 100) //11.00HZ |
|||
) pwm10 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm110hz) |
|||
); |
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(111 * 100) //11.10HZ |
|||
) pwm11 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm111hz) |
|||
); |
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(112 * 100) //11.20HZ |
|||
) pwm12 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm112hz) |
|||
); |
|||
|
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(113 * 100) //11.30HZ |
|||
) pwm13 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm113hz) |
|||
); |
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(114 * 100) //11.40HZ |
|||
) pwm14 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm114hz) |
|||
); |
|||
zutils_pwm_generator_advanced #( |
|||
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), |
|||
.OUTPUT_FREQ_P00(115 * 100) //11.50HZ |
|||
) pwm15 ( |
|||
.clk (clk), |
|||
.rst_n (rst_n), |
|||
.ctrl_sig (1'd1), |
|||
.output_signal(pwm115hz) |
|||
); |
|||
|
|||
|
|||
endmodule |
|||
Write
Preview
Loading…
Cancel
Save
Reference in new issue