diff --git a/camera_light_src_timing_controller_fpga.pds b/camera_light_src_timing_controller_fpga.pds index 95611ca..c87c9a9 100644 --- a/camera_light_src_timing_controller_fpga.pds +++ b/camera_light_src_timing_controller_fpga.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Mar 10 11:26:03 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Mar 10 11:54:51 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-03-10T11:25:28") + (_timespec "2024-03-10T11:54:50") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -125,10 +125,6 @@ (_format verilog) (_timespec "2024-03-08T21:15:01") ) - (_file "source/src/output/timecode_output.v" - (_format verilog) - (_timespec "2024-03-08T21:15:01") - ) (_file "source/src/input/timecode_input.v" (_format verilog) (_timespec "2024-03-08T21:15:01") @@ -193,10 +189,6 @@ (_format verilog) (_timespec "2024-03-08T21:15:01") ) - (_file "source/src/output/camera_sync_signal_output.v" - (_format verilog) - (_timespec "2024-03-08T21:15:01") - ) (_file "source/src/business/record_sig_generator.v" (_format verilog) (_timespec "2024-03-08T21:15:01") @@ -271,21 +263,21 @@ ) (_task tsk_compile (_command cmd_compile - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-10T11:25:37") + (_timespec "2024-03-10T11:41:33") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-10T11:25:36") + (_timespec "2024-03-10T11:41:33") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-10T11:25:37") + (_timespec "2024-03-10T11:41:33") ) ) ) @@ -295,27 +287,27 @@ ) (_task tsk_synthesis (_command cmd_synthesize - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_option ads (_switch ON)) (_option selected_syn_tool_opt (_integer 2)) (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-03-10T11:25:43") + (_timespec "2024-03-10T11:41:40") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-03-10T11:25:43") + (_timespec "2024-03-10T11:41:40") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-03-10T11:25:44") + (_timespec "2024-03-10T11:41:40") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-03-10T11:25:44") + (_timespec "2024-03-10T11:41:40") ) ) ) @@ -332,25 +324,25 @@ ) (_task tsk_devmap (_command cmd_devmap - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-03-10T11:25:46") + (_timespec "2024-03-10T11:41:43") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-03-10T11:25:46") + (_timespec "2024-03-10T11:41:42") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-03-10T11:25:46") + (_timespec "2024-03-10T11:41:43") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-03-10T11:25:46") + (_timespec "2024-03-10T11:41:43") ) ) ) @@ -359,7 +351,7 @@ (_input (_file "device_map/camera_light_src_timing_controller_fpga.pcf" (_format pcf) - (_timespec "2024-03-10T11:25:46") + (_timespec "2024-03-10T11:41:43") ) ) ) @@ -369,38 +361,38 @@ ) (_task tsk_pnr (_command cmd_pnr - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_option mode (_string "fast")) (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-03-10T11:25:54") + (_timespec "2024-03-10T11:41:51") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-03-10T11:25:54") + (_timespec "2024-03-10T11:41:51") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-03-10T11:25:54") + (_timespec "2024-03-10T11:41:50") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-03-10T11:25:54") + (_timespec "2024-03-10T11:41:50") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-03-10T11:25:51") + (_timespec "2024-03-10T11:41:47") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-03-10T11:25:54") + (_timespec "2024-03-10T11:41:51") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-03-10T11:25:55") + (_timespec "2024-03-10T11:41:51") ) ) ) @@ -431,23 +423,23 @@ ) (_task tsk_gen_bitstream (_command cmd_gen_bitstream - (_gci_state (_integer 2)) + (_gci_state (_integer 3)) (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-03-10T11:26:03") + (_timespec "2024-03-10T11:41:58") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-03-10T11:26:03") + (_timespec "2024-03-10T11:41:58") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-03-10T11:26:03") + (_timespec "2024-03-10T11:41:58") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-03-10T11:26:03") + (_timespec "2024-03-10T11:41:59") ) ) ) diff --git a/release/test01/README.md b/release/test01/README.md new file mode 100644 index 0000000..6069701 --- /dev/null +++ b/release/test01/README.md @@ -0,0 +1,55 @@ + +``` +assign diff_out1 = diff_in1; + assign diff_out2 = diff_in2; + assign diff_out3 = diff_in3; + assign diff_out4 = diff_in4; + + + assign optocoupler_out1 = optocoupler_in1; + assign optocoupler_out2 = optocoupler_in2; + assign optocoupler_out3 = optocoupler_in3; + assign optocoupler_out4 = optocoupler_in4; + + + assign uart_tx = uart_rx; + assign stm32_output_bus[0] = stm32_input_bus[0]; + assign stm32_output_bus[1] = stm32_input_bus[1]; + assign stm32_output_bus[2] = stm32_input_bus[2]; + assign stm32_output_bus[3] = stm32_input_bus[3]; + assign stm32_output_bus[4] = stm32_input_bus[4]; + assign stm32_output_bus[5] = stm32_input_bus[5]; + assign stm32_output_bus[6] = stm32_input_bus[6]; + assign stm32_output_bus[7] = stm32_input_bus[7]; + + FPGA引出的测试引脚分别输出 + pwm100hz + pwm101hz + pwm102hz + pwm103hz + pwm104hz + pwm105hz + pwm106hz + pwm107hz + pwm108hz + pwm109hz + pwm110hz + pwm111hz + pwm112hz + pwm113hz + pwm114hz + pwm115hz + + 亮度控制: + .pwm100hz(lt1_en), + .pwm101hz(lt2_en), + .pwm102hz(lt3_en), + .pwm103hz(lt4_en), + .pwm104hz(lt1_intensity_ctrl), + .pwm105hz(lt2_intensity_ctrl), + .pwm106hz(lt3_intensity_ctrl), + .pwm107hz(lt4_intensity_ctrl) + + + +``` \ No newline at end of file diff --git a/release/test01/Top.sbit b/release/test01/Top.sbit new file mode 100644 index 0000000..57463ca Binary files /dev/null and b/release/test01/Top.sbit differ diff --git a/release/v2.0/xsync_fpage_v2.sbit b/release/v2.0/xsync_fpage_v2.sbit deleted file mode 100644 index fb324c5..0000000 Binary files a/release/v2.0/xsync_fpage_v2.sbit and /dev/null differ diff --git a/release/v2.0/xsync_fpage_v2.sfc b/release/v2.0/xsync_fpage_v2.sfc deleted file mode 100644 index da45617..0000000 Binary files a/release/v2.0/xsync_fpage_v2.sfc and /dev/null differ diff --git a/source/src/output/camera_sync_signal_output.v b/source/src/output/camera_sync_signal_output.v deleted file mode 100644 index 8d41a82..0000000 --- a/source/src/output/camera_sync_signal_output.v +++ /dev/null @@ -1,83 +0,0 @@ -module camera_sync_signal_output #( - parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - //寄存器读写接口 - input [31:0] addr, - input [31:0] wr_data, - input wr_en, - output wire [31:0] rd_data, - - input frame_sig, - input record_en_sig, - - output stm32if_camera_sync_out, //ttl输出信号 - output stm32if_record_sync_out // -); - - /******************************************************************************* - * 寄存器列表 * - *******************************************************************************/ - reg [31:0] reg1_pulse_mode_valid_len; - wire [31:0] reg_wr_index; - - zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk (clk), - .rst_n (rst_n), - .addr (addr), - .wr_data (wr_data), - .wr_en (wr_en), - .rd_data (rd_data), - .reg1 (reg1_pulse_mode_valid_len), - .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) - ); - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - reg1_pulse_mode_valid_len <= SYS_CLOCK_FREQ / 1000; - end else begin - if (reg_wr_sig) begin - case (reg_wr_index) - 1: reg1_pulse_mode_valid_len <= wr_data; - default: begin - end - endcase - end - end - end - - /******************************************************************************* - * 内部信号 * - *******************************************************************************/ - - wire frame_sig_rising_edge; - wire frame_sig_fa_process; - - // 边沿检测 - zutils_edge_detecter _signal_in ( - .clk (clk), - .rst_n (rst_n), - .in_signal (frame_sig), - .in_signal_rising_edge(frame_sig_rising_edge) - ); - - // 短脉冲，触发生成，长脉冲 - zutils_pluse_generator _pluse_generator ( - .clk (clk), - .rst_n (rst_n), - .pluse_width (reg1_pulse_mode_valid_len), //100us - .pluse_delay (0), - .trigger (frame_sig_rising_edge), - .output_signal(frame_sig_fa_process) - ); - - assign stm32if_camera_sync_out = frame_sig_fa_process; - assign stm32if_record_sync_out = record_en_sig; - -endmodule diff --git a/source/src/output/timecode_output.v b/source/src/output/timecode_output.v deleted file mode 100644 index 5028be3..0000000 --- a/source/src/output/timecode_output.v +++ /dev/null @@ -1,114 +0,0 @@ -module timecode_output #( - parameter REG_START_ADD = 0, - parameter SYS_CLOCK_FREQ = 10000000 -) ( - input clk, //clock input - input rst_n, //asynchronous reset input, low active - - input [31:0] addr, - input [31:0] wr_data, - input wr_en, - output wire [31:0] rd_data, - - /******************************************************************************* - * TIMECODE输出 * - *******************************************************************************/ - - input in_timecode_tigger_sig, - input [31:0] in_timecode_format, - input [63:0] in_timecode_data, - input in_timecode_serial_data, - - /******************************************************************************* - * 输出接口 * - *******************************************************************************/ - output stm32if_timecode_tigger_sig, - - output reg timecode_out_bnc, - output reg timecode_out_bnc_select, // 电平选择 0line,1:mic - output reg timecode_out_bnc_state_led, - - output reg timecode_out_headphone, - output reg timecode_out_headphone_select, // 电平选择 0line,1:mic - output reg timecode_out_headphone_state_led - -); - // 1ms - wire [31:0] r1_timecode0; //时码原始码0 //注意这个数据要比ext_timecode_serial_data晚一帧 - wire [31:0] r2_timecode1; //时码原始码1 //注意这个数据要比ext_timecode_serial_data晚一帧 - wire [31:0] r3_timecode_format; // - reg [31:0] r4_bnc_outut_level_select; // 0:line, 1:mic - reg [31:0] r5_headphone_outut_level_select; // 0:line, 1:mic - - wire [31:0] reg_wr_index; - - zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk (clk), - .rst_n (rst_n), - .addr (addr), - .wr_data(wr_data), - .wr_en (wr_en), - .rd_data(rd_data), - - .reg1(r1_timecode0), - .reg2(r2_timecode1), - .reg3(r3_timecode_format), - .reg4(r4_bnc_outut_level_select), - .reg5(r5_headphone_outut_level_select), - - - .reg_wr_sig(reg_wr_sig), - .reg_index (reg_wr_index) - ); - - always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - r4_bnc_outut_level_select <= 0; - r5_headphone_outut_level_select <= 0; - end else begin - if (reg_wr_sig) begin - case (reg_wr_index) - 31'h4: r4_bnc_outut_level_select <= wr_data; - 31'h5: r5_headphone_outut_level_select <= wr_data; - default: begin - end - endcase - end - end - end - - - assign r1_timecode0 = in_timecode_data[31:0]; - assign r2_timecode1 = in_timecode_data[63:32]; - assign r3_timecode_format = in_timecode_format; - assign out_timecode_serial_data = in_timecode_serial_data; - assign timecode_tigger_sig = in_timecode_tigger_sig; - - - zutils_pluse_generator _pluse_generator ( - .clk (clk), - .rst_n (rst_n), - .pluse_width (1000), //1ms - .pluse_delay (32'd0), - .trigger (timecode_tigger_sig), - .output_signal(stm32if_timecode_tigger_sig) - ); - - - always @(*) begin - timecode_out_bnc <= out_timecode_serial_data; - timecode_out_bnc_select <= r4_bnc_outut_level_select[0]; - timecode_out_bnc_state_led <= 1; - - timecode_out_headphone <= out_timecode_serial_data; - timecode_out_headphone_select <= r5_headphone_outut_level_select[0]; - timecode_out_headphone_state_led <= 1; - end - - - - - -endmodule diff --git a/source/src/top.v b/source/src/top.v index 4e4ec3f..ddb8560 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -152,8 +152,8 @@ module Top ( *******************************************************************************/ zutils_register16 #( .REG_START_ADD(`REGADDOFF__FPGA_INFO), - .REG0_INIT(`REGADDOFF__FPGA_VERSION), - .REG1_INIT(2), + .REG0_INIT(`REGADDOFF__FPGA_INFO), + .REG1_INIT(`REGADDOFF__FPGA_VERSION), .REG2_INIT(3), .REG3_INIT(4), .REG4_INIT(5), @@ -211,6 +211,28 @@ module Top ( ); + + + zutils_debug_pwm_generator #( + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) zutils_debug_pwm_generator0 ( + .clk (sys_clk), + .rst_n (sys_rst_n), + .pwm100hz(lt1_en), + .pwm101hz(lt2_en), + .pwm102hz(lt3_en), + .pwm103hz(lt4_en), + .pwm104hz(lt1_intensity_ctrl), + .pwm105hz(lt2_intensity_ctrl), + .pwm106hz(lt3_intensity_ctrl), + .pwm107hz(lt4_intensity_ctrl) + ); + + + + + + assign diff_out1 = diff_in1; assign diff_out2 = diff_in2; assign diff_out3 = diff_in3;