10 changed files with 627 additions and 430 deletions
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66led_test.pds
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14source/src/config.v
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245source/src/output/ttl_output.v
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86source/src/spi_reg_bus.v
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460source/src/top.v
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3source/src/zutils/zsimple_pll.v
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47source/src/zutils/zutils_bus32_multi_to_one.v
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2source/src/zutils/zutils_clk_parser.v
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87source/src/zutils/zutils_freq_detector_v2.v
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47source/src/zutils/zutils_multiplexer_8t1.v
@ -0,0 +1,14 @@ |
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`define REGADDOFF__FPGA_INFO 16'h0020 |
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`define REGADDOFF__TTLIN 16'h0100 |
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`define REGADDOFF__TIMECODE_IN 16'h0120 |
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`define REGADDOFF__GENLOCK_IN 16'h0130 |
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`define REGADDOFF__INTERNAL_TIMECODE 16'h0300 |
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`define REGADDOFF__INTERNAL_GENLOCK 16'h0310 |
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`define REGADDOFF__INTERNAL_CLOCK 16'h0320 |
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`define REGADDOFF__TTLOUT1 16'h0200 |
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`define REGADDOFF__TTLOUT2 16'h0210 |
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`define REGADDOFF__TTLOUT3 16'h0220 |
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`define REGADDOFF__TTLOUT4 16'h0230 |
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`define REGADDOFF__TIMECODE_OUT 16'h0240 |
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`define REGADDOFF__GENLOCK_OUT 16'h0250 |
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`define REGADDOFF__CAMERA_SYNC_OUT 16'h0260 |
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@ -0,0 +1,86 @@ |
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`include "config.v" |
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module spi_reg_bus ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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|
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//regbus interface |
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output [31:0] addr, |
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output [31:0] wr_data, |
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output wr_en, |
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// |
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input wire spi_cs_pin, // |
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input wire spi_clk_pin, // |
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input wire spi_rx_pin, // |
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output wire spi_tx_pin, |
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|
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input [31:0] rd_data_module_fpga_info, |
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input [31:0] rd_data_module_ttlin, |
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input [31:0] rd_data_module_timecode_in, |
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input [31:0] rd_data_module_genlock_in, |
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input [31:0] rd_data_module_internal_timecode, |
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input [31:0] rd_data_module_internal_genlock, |
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input [31:0] rd_data_module_internal_clock, |
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input [31:0] rd_data_module_ttlout1, |
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input [31:0] rd_data_module_ttlout2, |
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input [31:0] rd_data_module_ttlout3, |
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input [31:0] rd_data_module_ttlout4, |
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input [31:0] rd_data_module_timecode_out, |
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input [31:0] rd_data_module_genlock_out, |
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input [31:0] rd_data_module_camera_sync_out |
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); |
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|
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reg [31:0] rd_data; |
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|
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spi_reg_reader spi_reg_reader_inst ( |
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.clk (clk), |
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.rst_n (rst_n), |
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.addr (addr), |
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.wr_data (wr_data), |
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.wr_en (wr_en), |
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.rd_data (rd_data), |
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.spi_cs_pin (spi_cs_pin), |
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.spi_clk_pin(spi_clk_pin), |
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.spi_rx_pin (spi_rx_pin), |
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.spi_tx_pin (spi_tx_pin) |
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); |
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|
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// 数据路由 |
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wire [31:0] addr_group; |
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assign addr_group = addr & 31'hFFFF_FFF0; |
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always @(*) begin |
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case (addr_group) |
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`REGADDOFF__FPGA_INFO: |
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rd_data <= rd_data_module_fpga_info; |
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`REGADDOFF__TTLIN: |
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rd_data <= rd_data_module_ttlin; |
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`REGADDOFF__TIMECODE_IN: |
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rd_data <= rd_data_module_timecode_in; |
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`REGADDOFF__GENLOCK_IN: |
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rd_data <= rd_data_module_genlock_in; |
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`REGADDOFF__INTERNAL_TIMECODE: |
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rd_data <= rd_data_module_internal_timecode; |
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`REGADDOFF__INTERNAL_GENLOCK: |
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rd_data <= rd_data_module_internal_genlock; |
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`REGADDOFF__INTERNAL_CLOCK: |
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rd_data <= rd_data_module_internal_clock; |
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`REGADDOFF__TTLOUT1: |
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rd_data <= rd_data_module_ttlout1; |
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`REGADDOFF__TTLOUT2: |
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rd_data <= rd_data_module_ttlout2; |
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`REGADDOFF__TTLOUT3: |
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rd_data <= rd_data_module_ttlout3; |
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`REGADDOFF__TTLOUT4: |
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rd_data <= rd_data_module_ttlout4; |
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`REGADDOFF__TIMECODE_OUT: |
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rd_data <= rd_data_module_timecode_out; |
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`REGADDOFF__GENLOCK_OUT: |
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rd_data <= rd_data_module_genlock_out; |
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`REGADDOFF__CAMERA_SYNC_OUT: |
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rd_data <= rd_data_module_camera_sync_out; |
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default: |
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rd_data <= 0; |
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endcase |
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end |
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|
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|
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endmodule |
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@ -0,0 +1,47 @@ |
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module zutils_multiplexer_8t1 ( |
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input [31:0] chooseindex, |
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input wire signal0, |
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input wire signal1, |
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input wire signal2, |
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input wire signal3, |
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input wire signal4, |
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input wire signal5, |
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input wire signal6, |
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input wire signal7, |
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input wire signal8, |
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output reg signalout |
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); |
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|
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|
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always @(*) begin |
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case (chooseindex) |
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0: begin |
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signalout = signal0; |
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end |
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1: begin |
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signalout = signal1; |
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end |
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2: begin |
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signalout = signal2; |
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end |
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3: begin |
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signalout = signal3; |
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end |
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4: begin |
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signalout = signal4; |
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end |
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5: begin |
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signalout = signal5; |
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end |
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6: begin |
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signalout = signal6; |
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end |
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7: begin |
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signalout = signal7; |
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end |
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default: begin |
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signalout = 0; |
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end |
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endcase |
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end |
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endmodule |
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@ -0,0 +1,47 @@ |
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module zutils_multiplexer_8t1 ( |
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input [31:0] chooseindex, |
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input wire signal0, |
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input wire signal1, |
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input wire signal2, |
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input wire signal3, |
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input wire signal4, |
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input wire signal5, |
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input wire signal6, |
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input wire signal7, |
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input wire signal8, |
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output reg signalout |
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); |
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|
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|
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always @(*) begin |
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case (chooseindex) |
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0: begin |
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signalout = signal0; |
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end |
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1: begin |
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signalout = signal1; |
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end |
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2: begin |
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signalout = signal2; |
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end |
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3: begin |
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signalout = signal3; |
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end |
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4: begin |
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signalout = signal4; |
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end |
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5: begin |
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signalout = signal5; |
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end |
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6: begin |
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signalout = signal6; |
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end |
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7: begin |
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signalout = signal7; |
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end |
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default: begin |
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signalout = 0; |
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end |
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endcase |
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end |
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endmodule |
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