diff --git a/led_test.pds b/led_test.pds index 772ddf4..b63e76d 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Mar 2 22:45:22 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Mar 4 15:16:02 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-03-02T17:50:26") + (_timespec "2024-03-04T10:57:17") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -51,7 +51,7 @@ ) (_file "source/src/zutils/zutils_clk_parser.v" (_format verilog) - (_timespec "2024-02-27T20:28:55") + (_timespec "2024-03-04T10:38:07") ) (_file "source/src/zutils/zutils_multiplexer_16t1.v" (_format verilog) @@ -59,7 +59,7 @@ ) (_file "source/src/output/ttl_output.v" (_format verilog) - (_timespec "2024-03-02T22:23:06") + (_timespec "2024-03-04T14:18:34") ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) @@ -167,11 +167,19 @@ ) (_file "source/src/zutils/zsimple_pll.v" (_format verilog) - (_timespec "2024-03-02T22:44:30") + (_timespec "2024-03-04T09:54:54") ) (_file "source/src/zutils/zutils_freq_detector_v2.v" (_format verilog) - (_timespec "2024-03-02T22:20:27") + (_timespec "2024-03-04T15:12:52") + ) + (_file "source/src/zutils/zutils_multiplexer_8t1.v" + (_format verilog) + (_timespec "2024-03-04T10:57:15") + ) + (_file "source/src/spi_reg_bus.v" + (_format verilog) + (_timespec "2024-03-04T11:36:33") ) ) ) @@ -243,17 +251,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-02T22:44:36") + (_timespec "2024-03-04T15:12:56") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-02T22:44:35") + (_timespec "2024-03-04T15:12:56") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-02T22:44:36") + (_timespec "2024-03-04T15:12:57") ) ) ) @@ -269,21 +277,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-03-02T22:44:44") + (_timespec "2024-03-04T15:13:29") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-03-02T22:44:45") + (_timespec "2024-03-04T15:13:34") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-03-02T22:44:46") + (_timespec "2024-03-04T15:13:38") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-03-02T22:44:46") + (_timespec "2024-03-04T15:13:39") ) ) ) @@ -304,21 +312,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-03-02T22:44:49") + (_timespec "2024-03-04T15:13:43") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-03-02T22:44:48") + (_timespec "2024-03-04T15:13:41") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-03-02T22:44:49") + (_timespec "2024-03-04T15:13:43") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-03-02T22:44:49") + (_timespec "2024-03-04T15:13:43") ) ) ) @@ -327,7 +335,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-03-02T22:44:49") + (_timespec "2024-03-04T15:13:43") ) ) ) @@ -342,33 +350,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-03-02T22:45:03") + (_timespec "2024-03-04T15:15:24") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-03-02T22:45:03") + (_timespec "2024-03-04T15:15:24") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-03-02T22:45:03") + (_timespec "2024-03-04T15:15:23") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-03-02T22:45:03") + (_timespec "2024-03-04T15:15:23") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-03-02T22:44:55") + (_timespec "2024-03-04T15:13:56") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-03-02T22:45:03") + (_timespec "2024-03-04T15:15:24") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-03-02T22:45:04") + (_timespec "2024-03-04T15:15:25") ) ) ) @@ -403,19 +411,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-03-02T22:45:21") + (_timespec "2024-03-04T15:16:00") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-03-02T22:45:21") + (_timespec "2024-03-04T15:16:00") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-03-02T22:45:21") + (_timespec "2024-03-04T15:16:00") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-03-02T22:45:22") + (_timespec "2024-03-04T15:16:02") ) ) ) diff --git a/source/src/config.v b/source/src/config.v new file mode 100644 index 0000000..76cf0f0 --- /dev/null +++ b/source/src/config.v @@ -0,0 +1,14 @@ +`define REGADDOFF__FPGA_INFO 16'h0020 +`define REGADDOFF__TTLIN 16'h0100 +`define REGADDOFF__TIMECODE_IN 16'h0120 +`define REGADDOFF__GENLOCK_IN 16'h0130 +`define REGADDOFF__INTERNAL_TIMECODE 16'h0300 +`define REGADDOFF__INTERNAL_GENLOCK 16'h0310 +`define REGADDOFF__INTERNAL_CLOCK 16'h0320 +`define REGADDOFF__TTLOUT1 16'h0200 +`define REGADDOFF__TTLOUT2 16'h0210 +`define REGADDOFF__TTLOUT3 16'h0220 +`define REGADDOFF__TTLOUT4 16'h0230 +`define REGADDOFF__TIMECODE_OUT 16'h0240 +`define REGADDOFF__GENLOCK_OUT 16'h0250 +`define REGADDOFF__CAMERA_SYNC_OUT 16'h0260 diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v index af88491..5d881f2 100644 --- a/source/src/output/ttl_output.v +++ b/source/src/output/ttl_output.v @@ -2,7 +2,7 @@ module ttl_output #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 10000000, parameter ID = 1 - ) ( +) ( input clk, //clock input input rst_n, //asynchronous reset input, low active @@ -14,117 +14,112 @@ module ttl_output #( input [31:0] signal_in, - output ttloutput, //ttl输出信号 + output ttloutput, //ttl输出信号 output ttloutput_state_led //ttl输出状态信号 - ); - - // 编写注意事项 - // 1. 修改配置寄存器时候，部分计数需要清空 - - +); /******************************************************************************* * 寄存器列表 * *******************************************************************************/ //!信号处理模式 0:固定输出低电平，1:固定输出高电平，2:分频倍频模式，3:转发模式，4:测试模式 - reg [31:0] reg_signal_process_mode; + reg [31:0] reg_signal_process_mode; //!TTLOUT_信号选择器 - reg [31:0] reg_input_signal_select; + reg [31:0] reg_input_signal_select; //!TTLOUT_分频器 - reg [31:0] reg_input_freq_division; + reg [31:0] reg_pllout_freq_division_ctrl; //!TTLOUT_频率倍增器 - reg [31:0] reg_input_freq_multiplication; + reg [31:0] reg_pllout_freq_multiplication_ctrl; //!TTLOUT_极性控制寄存器 - reg [31:0] reg_input_polarity_ctrl; + reg [31:0] reg_pllout_polarity_ctrl; //!TTLOUT_触发信号边沿类型 - reg [31:0] reg_input_trigger_edge_select; - //!输出脉冲宽度 - reg [31:0] output_pluse_width; - // !频率探测偏差 - reg [31:0] freq_detect_bias; - //!输出脉冲延迟 - reg [31:0] output_pluse_delay; + reg [31:0] reg_pllout_trigger_edge_select; + //!转发模式下的极性控制 + reg [31:0] reg_forward_mode_polarity_ctrl; + //!占位 + reg [31:0] reg_placeholder0; + // !频率探测偏差 + reg [31:0] reg_freq_detect_bias; + //!输入信号频率探测 read only - reg [31:0] reg_sig_in_freq_detect; + wire [31:0] reg_sig_in_freq_detect; //!输出信号频率探测 read only - reg [31:0] reg_sig_out_freq_detect; - + wire [31:0] reg_sig_out_freq_detect; - - wire [31:0] reg_wr_index;//!寄存器写入时相对地址 - reg signal_in_choose; //!原始信号 - wire signal_in_pll;//!倍频后的信号 - wire signal_in_polarity_ctrl;//!极性翻转后的信号 + wire [31:0] reg_wr_index; //!寄存器写入时相对地址 + wire signal_in_choose; //!原始信号 + wire signal_in_af_pll; //!倍频后的信号 + wire signal_af_pll_af_polarity_ctrl; //!极性翻转后的信号 + wire signal_in_af_forward_mode_polarity_ctrl; //!转发模式下的输入信号 + wire signal_test; //!测试信号 //信号流转图 // - // signal_in[] - // ---> signal_in_choose - // ---> + // signal_in[](原始信号) + // ---> reg_input_signal_select -->signal_in_choose(信号选择器) + // --> + // reg_pllout_trigger_edge_select + // reg_pllout_freq_division_ctrl ---> signal_in_af_pll(经分频倍频后的信号) + // reg_pllout_freq_multiplication_ctrl + // ---> signal_af_pll_af_polarity_ctrl // // - + // 0:0 ---| + // 1:1 ---| + // 2:signal_af_pll_af_polarity_ctrl ---|--> + // 3:signal_in_af_forward_mode_polarity_ctrl ---| + // 4:test_sig ---| + // //!TTLOUT_寄存器自动赋值选择器 zutils_register_advanced #( - .REG_START_ADD(REG_START_ADD) - ) _register ( - .clk(clk), - .rst_n(rst_n), - .addr(addr), - .wr_data(wr_data), - .wr_en(wr_en), - .rd_data(rd_data), - .reg0(reg_signal_process_mode), - .reg1(reg_input_signal_select), - .reg2(reg_input_freq_division), - .reg3(reg_input_freq_multiplication), - .reg4(reg_input_polarity_ctrl), - .reg5(reg_input_trigger_edge_select), - .reg6(output_pluse_width), - .reg7(output_pluse_delay), - .reg8(freq_detect_bias), - .regE(reg_sig_in_freq_detect), - .regF(reg_sig_out_freq_detect), - .reg_wr_sig(reg_wr_sig), - .reg_index(reg_wr_index) - ); + .REG_START_ADD(REG_START_ADD) + ) _register ( + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data (wr_data), + .wr_en (wr_en), + .rd_data (rd_data), + .reg0 (reg_signal_process_mode), + .reg1 (reg_input_signal_select), + .reg2 (reg_pllout_freq_division_ctrl), + .reg3 (reg_pllout_freq_multiplication_ctrl), + .reg4 (reg_pllout_polarity_ctrl), + .reg5 (reg_pllout_trigger_edge_select), + .reg6 (reg_forward_mode_polarity_ctrl), + .reg7 (reg_placeholder0), + .reg8 (reg_freq_detect_bias), + .regE (reg_sig_in_freq_detect), + .regF (reg_sig_out_freq_detect), + .reg_wr_sig(reg_wr_sig), + .reg_index (reg_wr_index) + ); //!寄存器写入逻辑 always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - reg_signal_process_mode<=0; - reg_input_signal_select<=0; - reg_input_freq_division<=0; - reg_input_freq_multiplication<=0; - reg_input_polarity_ctrl<=0; - reg_input_trigger_edge_select<=1; //上升沿触发 - output_pluse_width<= 1000; // 100us - output_pluse_delay<=0; - freq_detect_bias<= 32'd10; - end - else begin + reg_signal_process_mode <= 0; + reg_input_signal_select <= 0; + reg_pllout_freq_division_ctrl <= 0; + reg_pllout_freq_multiplication_ctrl <= 0; + reg_pllout_polarity_ctrl <= 0; + reg_pllout_trigger_edge_select <= 1; + reg_forward_mode_polarity_ctrl <= 0; + reg_placeholder0 <= 0; + reg_freq_detect_bias <= 32'd10; + end else begin if (reg_wr_sig) begin case (reg_wr_index) - 0: - reg_signal_process_mode <= wr_data; - 1: - reg_input_signal_select <= wr_data; - 2: - reg_input_freq_division <= wr_data; - 3: - reg_input_freq_multiplication <= wr_data; - 4: - reg_input_polarity_ctrl <= wr_data; - 5: - reg_input_trigger_edge_select <= wr_data; - 6: - output_pluse_width <= wr_data; - 7: - output_pluse_delay <= wr_data; - 8: - freq_detect_bias <= wr_data; + 0: reg_signal_process_mode <= wr_data; + 1: reg_input_signal_select <= wr_data; + 2: reg_pllout_freq_division_ctrl <= wr_data; + 3: reg_pllout_freq_multiplication_ctrl <= wr_data; + 4: reg_pllout_polarity_ctrl <= wr_data; + 5: reg_pllout_trigger_edge_select <= wr_data; + 6: reg_forward_mode_polarity_ctrl <= wr_data; + 7: reg_placeholder0 <= wr_data; + 8: reg_freq_detect_bias <= wr_data; default: begin end endcase @@ -133,31 +128,73 @@ module ttl_output #( end //!信号选择器 - always @(*) begin - if(reg_input_signal_select <= 31) begin - signal_in_choose <= signal_in[reg_input_signal_select]; - end - else begin - signal_in_choose <= 0; - end - end - + zutils_multiplexer_32t1 signal_in_multiplexer ( + .chooseindex(reg_input_signal_select), + .signal (signal_in), + .signalout (signal_in_choose) + ); + //!pll信号处理 zsimple_pll _simple_pll ( - .clk(clk), - .rst_n(rst_n), - .insignal(signal_in[2]), - .trigger_eage_type(reg_input_trigger_edge_select[0]), - .freq_detect_bias(freq_detect_bias), - .freq_division(reg_input_freq_division), - .freq_multiplication(3), - .cfg_change(reg_wr_sig), - .outsignal(signal_in_pll) - ); + .clk (clk), + .rst_n (rst_n), + .insignal (signal_in_choose), + .trigger_eage_type (reg_pllout_trigger_edge_select[0]), + .freq_detect_bias (reg_freq_detect_bias), + .freq_division (reg_pllout_freq_division_ctrl), + .freq_multiplication(reg_pllout_freq_multiplication_ctrl), + .polarity_ctrl (reg_pllout_polarity_ctrl[0]), + .cfg_change (reg_wr_sig), + .outsignal (signal_in_af_pll) + ); - assign ttloutput_state_led = 1; - assign ttloutput = signal_in_pll; + //!100HZ测试信号发生器 + zutils_pwm_generator #( + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .OUTPUT_FREQ(100) + ) pwm100hz_gen ( + .clk (clk), + .rst_n (rst_n), + .output_signal(signal_test) + ); + + + + assign signal_in_af_forward_mode_polarity_ctrl = signal_in_choose ^ reg_forward_mode_polarity_ctrl[0]; + + //!信号输出选择器 + zutils_multiplexer_8t1 signal_output_multiplexer ( + .chooseindex(reg_signal_process_mode), + .signal0 (1'b0), + .signal1 (1'b1), + .signal2 (signal_in_af_pll), + .signal3 (signal_in_af_forward_mode_polarity_ctrl), + .signal4 (signal_test), + .signal5 (1'b0), + .signal6 (1'b0), + .signal7 (1'b0), + .signalout (ttloutput) + ); + + // + // + zutils_freq_detector_v2 in_freq_detector ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(reg_freq_detect_bias), + .pluse_input (signal_in_choose), + .pluse_width_cnt (reg_sig_in_freq_detect) + ); + + zutils_freq_detector_v2 output_freq_detector ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(reg_freq_detect_bias), + .pluse_input (ttloutput), + .pluse_width_cnt (reg_sig_out_freq_detect) + ); + assign ttloutput_state_led = 1; endmodule diff --git a/source/src/spi_reg_bus.v b/source/src/spi_reg_bus.v new file mode 100644 index 0000000..632d7cd --- /dev/null +++ b/source/src/spi_reg_bus.v @@ -0,0 +1,86 @@ +`include "config.v" +module spi_reg_bus ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + + //regbus interface + output [31:0] addr, + output [31:0] wr_data, + output wr_en, + // + input wire spi_cs_pin, // + input wire spi_clk_pin, // + input wire spi_rx_pin, // + output wire spi_tx_pin, + + input [31:0] rd_data_module_fpga_info, + input [31:0] rd_data_module_ttlin, + input [31:0] rd_data_module_timecode_in, + input [31:0] rd_data_module_genlock_in, + input [31:0] rd_data_module_internal_timecode, + input [31:0] rd_data_module_internal_genlock, + input [31:0] rd_data_module_internal_clock, + input [31:0] rd_data_module_ttlout1, + input [31:0] rd_data_module_ttlout2, + input [31:0] rd_data_module_ttlout3, + input [31:0] rd_data_module_ttlout4, + input [31:0] rd_data_module_timecode_out, + input [31:0] rd_data_module_genlock_out, + input [31:0] rd_data_module_camera_sync_out + ); + + reg [31:0] rd_data; + + spi_reg_reader spi_reg_reader_inst ( + .clk (clk), + .rst_n (rst_n), + .addr (addr), + .wr_data (wr_data), + .wr_en (wr_en), + .rd_data (rd_data), + .spi_cs_pin (spi_cs_pin), + .spi_clk_pin(spi_clk_pin), + .spi_rx_pin (spi_rx_pin), + .spi_tx_pin (spi_tx_pin) + ); + + // 数据路由 + wire [31:0] addr_group; + assign addr_group = addr & 31'hFFFF_FFF0; + always @(*) begin + case (addr_group) + `REGADDOFF__FPGA_INFO: + rd_data <= rd_data_module_fpga_info; + `REGADDOFF__TTLIN: + rd_data <= rd_data_module_ttlin; + `REGADDOFF__TIMECODE_IN: + rd_data <= rd_data_module_timecode_in; + `REGADDOFF__GENLOCK_IN: + rd_data <= rd_data_module_genlock_in; + `REGADDOFF__INTERNAL_TIMECODE: + rd_data <= rd_data_module_internal_timecode; + `REGADDOFF__INTERNAL_GENLOCK: + rd_data <= rd_data_module_internal_genlock; + `REGADDOFF__INTERNAL_CLOCK: + rd_data <= rd_data_module_internal_clock; + `REGADDOFF__TTLOUT1: + rd_data <= rd_data_module_ttlout1; + `REGADDOFF__TTLOUT2: + rd_data <= rd_data_module_ttlout2; + `REGADDOFF__TTLOUT3: + rd_data <= rd_data_module_ttlout3; + `REGADDOFF__TTLOUT4: + rd_data <= rd_data_module_ttlout4; + `REGADDOFF__TIMECODE_OUT: + rd_data <= rd_data_module_timecode_out; + `REGADDOFF__GENLOCK_OUT: + rd_data <= rd_data_module_genlock_out; + `REGADDOFF__CAMERA_SYNC_OUT: + rd_data <= rd_data_module_camera_sync_out; + default: + rd_data <= 0; + endcase + end + + +endmodule diff --git a/source/src/top.v b/source/src/top.v index a03b4fb..8cc4f0c 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -1,4 +1,5 @@ `timescale 1ns / 1ns +`include "config.v" module Top ( input ex_clk, input ex_rst_n, @@ -71,30 +72,16 @@ module Top ( output [15:0] debug_signal_output, output wire core_board_debug_led - ); +); - localparam REGADDOFF__FPGA_INFO = 16'h0020; - localparam REGADDOFF__TTLIN = 16'h0100; - localparam REGADDOFF__TIMECODE_IN = 16'h0120; - localparam REGADDOFF__GENLOCK_IN = 16'h0130; - localparam REGADDOFF__INTERNAL_TIMECODE = 16'h0200; - localparam REGADDOFF__INTERNAL_GENLOCK = 16'h0210; - localparam REGADDOFF__INTERNAL_CLOCK = 16'h0220; - localparam REGADDOFF__TTLOUT1 = 16'h0200; - localparam REGADDOFF__TTLOUT2 = 16'h0210; - localparam REGADDOFF__TTLOUT3 = 16'h0220; - localparam REGADDOFF__TTLOUT4 = 16'h0230; - localparam REGADDOFF__TIMECODE_OUT = 16'h0240; - localparam REGADDOFF__GENLOCK_OUT = 16'h0250; - localparam REGADDOFF__CAMERA_SYNC_OUT = 16'h0260; - localparam SYS_CLOCK_FREQ = 10000000; + localparam SYS_CLOCK_FREQ = 10000000; - wire sys_clk; //! 系统时钟 - wire sys_rst_n; //! 系统复位 + wire sys_clk; //! 系统时钟 + wire sys_rst_n; //! 系统复位 //寄存器读写总线 wire [31:0] RegReaderBus_addr; //!寄存器读写-地址总线 @@ -110,179 +97,156 @@ module Top ( wire [31:0] rd_data_module_internal_timecode; //! 模块寄存器数据总线读数据 wire [31:0] rd_data_module_internal_genlock; //! 模块寄存器数据总线读数据 wire [31:0] rd_data_module_internal_clock; //! 模块寄存器数据总线读数据 - wire [31:0] rd_data_module_ttlout1;//! 模块寄存器数据总线读数据 - wire [31:0] rd_data_module_ttlout2;//! 模块寄存器数据总线读数据 - wire [31:0] rd_data_module_ttlout3;//! 模块寄存器数据总线读数据 - wire [31:0] rd_data_module_ttlout4;//! 模块寄存器数据总线读数据 - wire [31:0] rd_data_module_timecode_out;//! 模块寄存器数据总线读数据 - wire [31:0] rd_data_module_genlock_out;//! 模块寄存器数据总线读数据 - wire [31:0] rd_data_module_camera_sync_out;//! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_ttlout1; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_ttlout2; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_ttlout3; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_ttlout4; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_timecode_out; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_genlock_out; //! 模块寄存器数据总线读数据 + wire [31:0] rd_data_module_camera_sync_out; //! 模块寄存器数据总线读数据 //内部信号 - wire signal_logic0; //! 逻辑0 - wire signal_logic1; //! 逻辑1 - wire signal_ttlin1; //! TTL输入1 - wire signal_ttlin2; //! TTL输入2 - wire signal_ttlin3; //! TTL输入3 - wire signal_ttlin4; //! TTL输入4 - wire signal_ext_genlock_freq; //! 外部GENLOCK频率信号 - wire signal_ext_timecode_freq; //! 外部时间码频率信号 - wire signal_internal_timecode_freq;//! 内部时间码频率信号 - wire signal_internal_genlock_freq;//! 内部GENLOCK频率信号 - wire signal_internal_freq_sig;//! 内部频率信号 - wire signal_sys_clk_output;//! 系统时钟输出 - wire signal_sys_genlock_output;//! 系统GENLOCK输出 - wire signal_sys_timecode_freq_output;//! 系统时间码频率输出 - wire signal_business_record_sig; //! 业务摄影状态信号 - wire signal_business_record_exposure_sig;//! 业务摄影拍照曝光信号 - - wire [31:0] sig_src; // 系统内部信号总线 - - assign sig_src[0] = signal_logic0; - assign sig_src[1] = signal_logic1; - assign sig_src[2] = signal_ttlin1; - assign sig_src[3] = signal_ttlin2; - assign sig_src[4] = signal_ttlin3; - assign sig_src[5] = signal_ttlin4; - assign sig_src[6] = signal_ext_genlock_freq; - assign sig_src[7] = signal_ext_timecode_freq; - assign sig_src[8] = signal_internal_timecode_freq; - assign sig_src[9] = signal_internal_genlock_freq; - assign sig_src[10] = signal_internal_freq_sig; - assign sig_src[11] = signal_sys_clk_output; - assign sig_src[12] = signal_sys_genlock_output; - assign sig_src[13] = signal_sys_timecode_freq_output; - assign sig_src[14] = signal_business_record_sig; - assign sig_src[15] = signal_business_record_exposure_sig; + wire signal_logic0; //! 逻辑0 + wire signal_logic1; //! 逻辑1 + wire signal_ttlin1; //! TTL输入1 + wire signal_ttlin2; //! TTL输入2 + wire signal_ttlin3; //! TTL输入3 + wire signal_ttlin4; //! TTL输入4 + wire signal_ext_genlock_freq; //! 外部GENLOCK频率信号 + wire signal_ext_timecode_freq; //! 外部时间码频率信号 + wire signal_internal_timecode_freq; //! 内部时间码频率信号 + wire signal_internal_genlock_freq; //! 内部GENLOCK频率信号 + wire signal_internal_freq_sig; //! 内部频率信号 + wire signal_sys_clk_output; //! 系统时钟输出 + wire signal_sys_genlock_output; //! 系统GENLOCK输出 + wire signal_sys_timecode_freq_output; //! 系统时间码频率输出 + wire signal_business_record_sig; //! 业务摄影状态信号 + wire signal_business_record_exposure_sig; //! 业务摄影拍照曝光信号 + + wire [31:0] sig_src; // 系统内部信号总线 + + assign sig_src[0] = signal_logic0; + assign sig_src[1] = signal_logic1; + assign sig_src[2] = signal_ttlin1; + assign sig_src[3] = signal_ttlin2; + assign sig_src[4] = signal_ttlin3; + assign sig_src[5] = signal_ttlin4; + assign sig_src[6] = signal_ext_genlock_freq; + assign sig_src[7] = signal_ext_timecode_freq; + assign sig_src[8] = signal_internal_timecode_freq; + assign sig_src[9] = signal_internal_genlock_freq; + assign sig_src[10] = signal_internal_freq_sig; + assign sig_src[11] = signal_sys_clk_output; + assign sig_src[12] = signal_sys_genlock_output; + assign sig_src[13] = signal_sys_timecode_freq_output; + assign sig_src[14] = signal_business_record_sig; + assign sig_src[15] = signal_business_record_exposure_sig; assign signal_logic0 = 1'b0; assign signal_logic1 = 1'b1; //系统时钟源 SPLL spll ( - .clkin1 (ex_clk), - .pll_lock(pll_lock), - .clkout0 (sys_clk_25m), - .clkout1 (sys_clk_10m), - .clkout2 (sys_clk_5m) - ); + .clkin1 (ex_clk), + .pll_lock(pll_lock), + .clkout0 (sys_clk_25m), + .clkout1 (sys_clk_10m), + .clkout2 (sys_clk_5m) + ); assign sys_clk = sys_clk_10m; assign sys_rst_n = ex_rst_n & pll_lock; + spi_reg_bus _spi_reg_bus ( + .clk (sys_clk), + .rst_n (sys_rst_n), + .addr (RegReaderBus_addr), + .wr_data (RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .spi_cs_pin (spi2_cs_pin), + .spi_clk_pin(spi2_clk_pin), + .spi_rx_pin (spi2_rx_pin), + .spi_tx_pin (spi2_tx_pin), + + .rd_data_module_fpga_info (rd_data_module_fpga_info), + .rd_data_module_ttlin (rd_data_module_ttlin), + .rd_data_module_timecode_in (rd_data_module_timecode_in), + .rd_data_module_genlock_in (rd_data_module_genlock_in), + .rd_data_module_internal_timecode(rd_data_module_internal_timecode), + .rd_data_module_internal_genlock (rd_data_module_internal_genlock), + .rd_data_module_internal_clock (rd_data_module_internal_clock), + .rd_data_module_ttlout1 (rd_data_module_ttlout1), + .rd_data_module_ttlout2 (rd_data_module_ttlout2), + .rd_data_module_ttlout3 (rd_data_module_ttlout3), + .rd_data_module_ttlout4 (rd_data_module_ttlout4), + .rd_data_module_timecode_out (rd_data_module_timecode_out), + .rd_data_module_genlock_out (rd_data_module_genlock_out), + .rd_data_module_camera_sync_out (rd_data_module_camera_sync_out) + + ); - spi_reg_reader spi_reg_reader_inst ( - .clk (sys_clk), - .rst_n (sys_rst_n), - .addr (RegReaderBus_addr), - .wr_data (RegReaderBus_wr_data), - .wr_en (RegReaderBus_wr_en), - .rd_data (RegReaderBus_rd_data), - .spi_cs_pin (spi2_cs_pin), - .spi_clk_pin(spi2_clk_pin), - .spi_rx_pin (spi2_rx_pin), - .spi_tx_pin (spi2_tx_pin) - ); - - // 数据路由 - wire [31:0] addr_group; - assign addr_group = RegReaderBus_addr & 31'hFFFF_FFF0; - always @(*) begin - case (addr_group) - REGADDOFF__FPGA_INFO: - RegReaderBus_rd_data <= rd_data_module_fpga_info; - REGADDOFF__TTLIN: - RegReaderBus_rd_data <= rd_data_module_ttlin; - REGADDOFF__TIMECODE_IN: - RegReaderBus_rd_data <= rd_data_module_timecode_in; - REGADDOFF__GENLOCK_IN: - RegReaderBus_rd_data <= rd_data_module_genlock_in; - REGADDOFF__INTERNAL_TIMECODE: - RegReaderBus_rd_data <= rd_data_module_internal_timecode; - REGADDOFF__INTERNAL_GENLOCK: - RegReaderBus_rd_data <= rd_data_module_internal_genlock; - REGADDOFF__INTERNAL_CLOCK: - RegReaderBus_rd_data <= rd_data_module_internal_clock; - REGADDOFF__TTLOUT1: - RegReaderBus_rd_data <= rd_data_module_ttlout1; - REGADDOFF__TTLOUT2: - RegReaderBus_rd_data <= rd_data_module_ttlout2; - REGADDOFF__TTLOUT3: - RegReaderBus_rd_data <= rd_data_module_ttlout3; - REGADDOFF__TTLOUT4: - RegReaderBus_rd_data <= rd_data_module_ttlout4; - REGADDOFF__TIMECODE_OUT: - RegReaderBus_rd_data <= rd_data_module_timecode_out; - REGADDOFF__GENLOCK_OUT: - RegReaderBus_rd_data <= rd_data_module_genlock_out; - REGADDOFF__CAMERA_SYNC_OUT: - RegReaderBus_rd_data <= rd_data_module_camera_sync_out; - default: - RegReaderBus_rd_data <= 0; - endcase - end /******************************************************************************* * FPGA_INFO * *******************************************************************************/ zutils_register16 #( - .REG_START_ADD(REGADDOFF__FPGA_INFO), - .REG0_INIT(1), - .REG1_INIT(2), - .REG2_INIT(3), - .REG3_INIT(4), - .REG4_INIT(5), - .REG5_INIT(6), - .REG6_INIT(7), - .REG7_INIT(8), - .REG8_INIT(9), - .REG9_INIT(10), - .REGA_INIT(11), - .REGB_INIT(12), - .REGC_INIT(13), - .REGD_INIT(14), - .REGE_INIT(15), - .REGF_INIT(16) - ) test_reg ( - .clk(sys_clk), - .rst_n(sys_rst_n), - .addr(RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en(RegReaderBus_wr_en), - .rd_data(rd_data_module_fpga_info) - ); + .REG_START_ADD(`REGADDOFF__FPGA_INFO), + .REG0_INIT(1), + .REG1_INIT(2), + .REG2_INIT(3), + .REG3_INIT(4), + .REG4_INIT(5), + .REG5_INIT(6), + .REG6_INIT(7), + .REG7_INIT(8), + .REG8_INIT(9), + .REG9_INIT(10), + .REGA_INIT(11), + .REGB_INIT(12), + .REGC_INIT(13), + .REGD_INIT(14), + .REGE_INIT(15), + .REGF_INIT(16) + ) test_reg ( + .clk (sys_clk), + .rst_n (sys_rst_n), + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_fpga_info) + ); /******************************************************************************* * TTL输入模块 * *******************************************************************************/ ttl_input #( - .REG_START_ADD (REGADDOFF__TTLIN), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) - ) ttl_inputr_ins ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en(RegReaderBus_wr_en), - .rd_data(rd_data_module_ttlin), - - .ttlin1_raw(sync_ttl_in1), - .ttlin2_raw(sync_ttl_in2), - .ttlin3_raw(sync_ttl_in3), - .ttlin4_raw(!sync_ttl_in4), //in4电路上进行了反向 - - //指示灯 - .ttlin1_state_led(sync_ttl_in1_state_led), - .ttlin2_state_led(sync_ttl_in2_state_led), - .ttlin3_state_led(sync_ttl_in3_state_led), - .ttlin4_state_led(sync_ttl_in4_state_led), - - //原始信号 - .sig_ttlin1(signal_ttlin1), - .sig_ttlin2(signal_ttlin2), - .sig_ttlin3(signal_ttlin3), - .sig_ttlin4(signal_ttlin4) - ); + .REG_START_ADD (`REGADDOFF__TTLIN), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) + ) ttl_inputr_ins ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_ttlin), + + .ttlin1_raw(sync_ttl_in1), + .ttlin2_raw(sync_ttl_in2), + .ttlin3_raw(sync_ttl_in3), + .ttlin4_raw(!sync_ttl_in4), //in4电路上进行了反向 + + //指示灯 + .ttlin1_state_led(sync_ttl_in1_state_led), + .ttlin2_state_led(sync_ttl_in2_state_led), + .ttlin3_state_led(sync_ttl_in3_state_led), + .ttlin4_state_led(sync_ttl_in4_state_led), + + //原始信号 + .sig_ttlin1(signal_ttlin1), + .sig_ttlin2(signal_ttlin2), + .sig_ttlin3(signal_ttlin3), + .sig_ttlin4(signal_ttlin4) + ); /******************************************************************************* * TTL_OUTPUT * @@ -292,91 +256,91 @@ module Top ( ttl_output #( - .REG_START_ADD(REGADDOFF__TTLOUT1), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(1) - ) ttl_output_1 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en(RegReaderBus_wr_en), - .rd_data(rd_data_module_ttlout1), - - .signal_in(sig_src), - - .ttloutput(sync_ttl_out1), - .ttloutput_state_led(sync_ttl_out1_state_led) - ); + .REG_START_ADD(`REGADDOFF__TTLOUT1), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(1) + ) ttl_output_1 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_ttlout1), + + .signal_in(sig_src), + + .ttloutput (sync_ttl_out1), + .ttloutput_state_led(sync_ttl_out1_state_led) + ); ttl_output #( - .REG_START_ADD(REGADDOFF__TTLOUT2), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(2) - ) ttl_output_2 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en(RegReaderBus_wr_en), - .rd_data(rd_data_module_ttlout2), - - .signal_in(sig_src), - - .ttloutput(sync_ttl_out2), - .ttloutput_state_led(sync_ttl_out2_state_led) - ); + .REG_START_ADD(`REGADDOFF__TTLOUT2), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(2) + ) ttl_output_2 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_ttlout2), + + .signal_in(sig_src), + + .ttloutput (sync_ttl_out2), + .ttloutput_state_led(sync_ttl_out2_state_led) + ); ttl_output #( - .REG_START_ADD(REGADDOFF__TTLOUT3), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(3) - ) ttl_output_3 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en(RegReaderBus_wr_en), - .rd_data(rd_data_module_ttlout3), + .REG_START_ADD(`REGADDOFF__TTLOUT3), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(3) + ) ttl_output_3 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_ttlout3), + + .signal_in(sig_src), + + .ttloutput (sync_ttl_out3), + .ttloutput_state_led(sync_ttl_out3_state_led) + ); - .signal_in(sig_src), + ttl_output #( + .REG_START_ADD(`REGADDOFF__TTLOUT4), + .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), + .ID(4) + ) ttl_output_4 ( + .clk (sys_clk), + .rst_n(sys_rst_n), + + .addr (RegReaderBus_addr), + .wr_data(RegReaderBus_wr_data), + .wr_en (RegReaderBus_wr_en), + .rd_data(rd_data_module_ttlout4), + + .signal_in(sig_src), + + .ttloutput (sync_ttl_out4), + .ttloutput_state_led(sync_ttl_out4_state_led) + ); - .ttloutput(sync_ttl_out3), - .ttloutput_state_led(sync_ttl_out3_state_led) - ); - ttl_output #( - .REG_START_ADD(REGADDOFF__TTLOUT4), - .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ), - .ID(4) - ) ttl_output_4 ( - .clk (sys_clk), - .rst_n(sys_rst_n), - - .addr(RegReaderBus_addr), - .wr_data(RegReaderBus_wr_data), - .wr_en(RegReaderBus_wr_en), - .rd_data(rd_data_module_ttlout4), - - .signal_in(sig_src), - - .ttloutput(sync_ttl_out4), - .ttloutput_state_led(sync_ttl_out4_state_led) - ); - - - assign debug_signal_output[0] = sys_clk; - assign debug_signal_output[1] = sync_ttl_in1; - assign debug_signal_output[2] = sync_ttl_in2; - assign debug_signal_output[3] = sync_ttl_in3; - assign debug_signal_output[4] = sync_ttl_in4; - assign debug_signal_output[5] = sync_ttl_out1; - assign debug_signal_output[6] = sync_ttl_out2; - assign debug_signal_output[7] = sync_ttl_out3; - assign debug_signal_output[8] = sync_ttl_out4; - assign debug_signal_output[9] = genlock_in_fsync; + assign debug_signal_output[0] = sys_clk; + assign debug_signal_output[1] = sync_ttl_in1; + assign debug_signal_output[2] = sync_ttl_in2; + assign debug_signal_output[3] = sync_ttl_in3; + assign debug_signal_output[4] = sync_ttl_in4; + assign debug_signal_output[5] = sync_ttl_out1; + assign debug_signal_output[6] = sync_ttl_out2; + assign debug_signal_output[7] = sync_ttl_out3; + assign debug_signal_output[8] = sync_ttl_out4; + assign debug_signal_output[9] = genlock_in_fsync; assign debug_signal_output[10] = timecode_headphone_in; assign debug_signal_output[11] = timecode_bnc_in; assign debug_signal_output[12] = timecode_out_headphone; diff --git a/source/src/zutils/zsimple_pll.v b/source/src/zutils/zsimple_pll.v index 6195e7b..1db0c25 100644 --- a/source/src/zutils/zsimple_pll.v +++ b/source/src/zutils/zsimple_pll.v @@ -7,6 +7,7 @@ module zsimple_pll ( input wire [31:0] freq_detect_bias, //! 频率偏差计数 input wire [31:0] freq_division, input wire [31:0] freq_multiplication, + input wire polarity_ctrl, input wire cfg_change, output wire outsignal ); @@ -144,5 +145,5 @@ module zsimple_pll ( end - assign outsignal = insignal_multiplication; + assign outsignal = insignal_multiplication ^ polarity_ctrl; endmodule diff --git a/source/src/zutils/zutils_bus32_multi_to_one.v b/source/src/zutils/zutils_bus32_multi_to_one.v new file mode 100644 index 0000000..625bbee --- /dev/null +++ b/source/src/zutils/zutils_bus32_multi_to_one.v @@ -0,0 +1,47 @@ +module zutils_multiplexer_8t1 ( + input [31:0] chooseindex, + input wire signal0, + input wire signal1, + input wire signal2, + input wire signal3, + input wire signal4, + input wire signal5, + input wire signal6, + input wire signal7, + input wire signal8, + output reg signalout +); + + + always @(*) begin + case (chooseindex) + 0: begin + signalout = signal0; + end + 1: begin + signalout = signal1; + end + 2: begin + signalout = signal2; + end + 3: begin + signalout = signal3; + end + 4: begin + signalout = signal4; + end + 5: begin + signalout = signal5; + end + 6: begin + signalout = signal6; + end + 7: begin + signalout = signal7; + end + default: begin + signalout = 0; + end + endcase + end +endmodule diff --git a/source/src/zutils/zutils_clk_parser.v b/source/src/zutils/zutils_clk_parser.v index 5ac753f..eed64f6 100644 --- a/source/src/zutils/zutils_clk_parser.v +++ b/source/src/zutils/zutils_clk_parser.v @@ -1,6 +1,4 @@ // -// -// // cs : ----______________________________________________ // clk : ----------____----____----____----____----____---- // bitcnt : 0 1 2 ... 7 0 diff --git a/source/src/zutils/zutils_freq_detector_v2.v b/source/src/zutils/zutils_freq_detector_v2.v index c830ef7..27254ee 100644 --- a/source/src/zutils/zutils_freq_detector_v2.v +++ b/source/src/zutils/zutils_freq_detector_v2.v @@ -4,30 +4,28 @@ // 2. 频率探测 // 3. 输出灯光控制 // -module zutils_freq_detector_v2 - ( - input clk, //! 时钟输入 - input rst_n, //! 复位输入 - input pluse_input, //! 输入信号1 - input wire [31:0] freq_detect_bias, //! 频率偏差计数 - output reg [31:0]pluse_width_cnt, //! 输出捕获到的脉冲宽度 - output wire pluse_width_cnt_lock //! 输出捕获到的脉冲宽度锁定信号 - ); +module zutils_freq_detector_v2 ( + input clk, //! 时钟输入 + input rst_n, //! 复位输入 + input pluse_input, //! 输入信号1 + input wire [31:0] freq_detect_bias, //! 频率偏差计数 + output reg [31:0] pluse_width_cnt, //! 输出捕获到的脉冲宽度 + output wire pluse_width_cnt_lock //! 输出捕获到的脉冲宽度锁定信号 +); - reg in_signal_last; - reg in_signal_rising_edge; //! 上升沿 - reg [31:0] state; //! 频率捕获状态 - reg [31:0] freq_detect; //! 探测到频率cache1 - reg [31:0] freq_detect_cnt;//! 实时频率探测计数 + reg in_signal_last; + reg in_signal_rising_edge; //! 上升沿 + reg [31:0] state; //! 频率捕获状态 + reg [31:0] freq_detect; //! 探测到频率cache1 + reg [31:0] freq_detect_cnt; //! 实时频率探测计数 //!in_signal_last 捕获 always @(posedge clk or negedge rst_n) begin if (!rst_n) begin in_signal_last <= 0; - end - else begin + end else begin in_signal_last <= pluse_input; end end @@ -35,63 +33,60 @@ module zutils_freq_detector_v2 //!边沿捕获 always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - in_signal_rising_edge <= 0; - end - else begin + in_signal_rising_edge <= 0; + end else begin if (in_signal_last == 0 && pluse_input == 1) begin - in_signal_rising_edge <= 1; - end - else if (in_signal_last == 1 && pluse_input == 0) begin - in_signal_rising_edge <= 0; - end - else begin - in_signal_rising_edge <= 0; + in_signal_rising_edge <= 1; + end else if (in_signal_last == 1 && pluse_input == 0) begin + in_signal_rising_edge <= 0; + end else begin + in_signal_rising_edge <= 0; end end end - assign freq_detect_stable = (freq_detect <= freq_detect_cnt + freq_detect_bias + 1 && freq_detect >= freq_detect_cnt - freq_detect_bias - 1); + assign freq_detect_stable = ((freq_detect <= freq_detect_cnt + freq_detect_bias + 1 )&& (freq_detect >= freq_detect_cnt - freq_detect_bias - 1)); always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - state <= 0; - freq_detect <=0; + state <= 0; + freq_detect <= 0; pluse_width_cnt <= 32'hffff_ffff; - end - else begin + end else begin case (state) 0: begin // 频率探测中 - if(in_signal_rising_edge) begin - freq_detect <= freq_detect_cnt; + if (in_signal_rising_edge) begin + freq_detect <= freq_detect_cnt; freq_detect_cnt <= 0; - if(freq_detect_stable) begin - state <= 1; + if (freq_detect_stable) begin + state <= 1; pluse_width_cnt <= freq_detect; end - else begin - pluse_width_cnt <= 32'hffff_ffff; - end - end - else begin + end else begin + pluse_width_cnt <= 32'hffff_ffff; freq_detect_cnt <= freq_detect_cnt + 1; end end 1: begin // 判断频率是否发生变化，如果频率发生变化，则重新探测 - if(in_signal_rising_edge || freq_detect_cnt> freq_detect+ 1) begin + if (in_signal_rising_edge) begin freq_detect_cnt <= 0; - if(!freq_detect_stable) begin - state <= 0; + if (!freq_detect_stable) begin + state <= 0; + freq_detect <= 32'hffff_ffff; pluse_width_cnt <= 32'hffff_ffff; end - end - else begin + end else if(freq_detect_cnt > freq_detect + freq_detect_bias + 1 )begin + freq_detect_cnt <= 0; + state <= 0; + freq_detect <= 32'hffff_ffff; + pluse_width_cnt <= 32'hffff_ffff; + end else begin freq_detect_cnt <= freq_detect_cnt + 1; end - end default: begin state <= 0; diff --git a/source/src/zutils/zutils_multiplexer_8t1.v b/source/src/zutils/zutils_multiplexer_8t1.v new file mode 100644 index 0000000..625bbee --- /dev/null +++ b/source/src/zutils/zutils_multiplexer_8t1.v @@ -0,0 +1,47 @@ +module zutils_multiplexer_8t1 ( + input [31:0] chooseindex, + input wire signal0, + input wire signal1, + input wire signal2, + input wire signal3, + input wire signal4, + input wire signal5, + input wire signal6, + input wire signal7, + input wire signal8, + output reg signalout +); + + + always @(*) begin + case (chooseindex) + 0: begin + signalout = signal0; + end + 1: begin + signalout = signal1; + end + 2: begin + signalout = signal2; + end + 3: begin + signalout = signal3; + end + 4: begin + signalout = signal4; + end + 5: begin + signalout = signal5; + end + 6: begin + signalout = signal6; + end + 7: begin + signalout = signal7; + end + default: begin + signalout = 0; + end + endcase + end +endmodule