15 changed files with 950 additions and 398 deletions
-
108led_test.fdc
-
169led_test.pds
-
202source/async.v
-
44source/led_test.v
-
31source/src/baud_rate_gen.v
-
24source/src/top.v
-
76source/src/transmitter.v
-
129source/src/uart_reg_reader.v
-
172source/src/uart_rx.v
-
161source/src/uart_tx.v
-
35source/test.v
-
30source/test/test_baud_rate_gen.v
-
50source/test/test_top.v
-
51source/test/test_transmitter.v
-
66source/test/test_uart_reg_reader.v
@ -1,202 +0,0 @@ |
|||
//////////////////////////////////////////////////////// |
|||
// RS-232 RX and TX module |
|||
// (c) fpga4fun.com & KNJN LLC - 2003 to 2016 |
|||
|
|||
// The RS-232 settings are fixed |
|||
// TX: 8-bit data, 2 stop, no-parity |
|||
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course) |
|||
|
|||
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle |
|||
// and RX receives one bit per clock cycle (for fast simulations) |
|||
|
|||
//////////////////////////////////////////////////////// |
|||
module async_transmitter( |
|||
input clk, |
|||
input TxD_start, |
|||
input [7:0] TxD_data, |
|||
output TxD, |
|||
output TxD_busy |
|||
); |
|||
|
|||
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data |
|||
// TxD_data is latched so that it doesn't have to stay valid while it is being sent |
|||
|
|||
parameter ClkFrequency = 50000000; // 50MHz |
|||
parameter Baud = 115200; |
|||
|
|||
generate |
|||
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate"); |
|||
endgenerate |
|||
|
|||
//////////////////////////////// |
|||
`ifdef SIMULATION |
|||
wire BitTick = 1'b1; // output one bit per clock cycle |
|||
`else |
|||
wire BitTick; |
|||
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick)); |
|||
`endif |
|||
|
|||
reg [3:0] TxD_state = 0; |
|||
wire TxD_ready = (TxD_state==0); |
|||
assign TxD_busy = ~TxD_ready; |
|||
|
|||
reg [7:0] TxD_shift = 0; |
|||
always @(posedge clk) |
|||
begin |
|||
if(TxD_ready & TxD_start) |
|||
TxD_shift <= TxD_data; |
|||
else |
|||
if(TxD_state[3] & BitTick) |
|||
TxD_shift <= (TxD_shift >> 1); |
|||
|
|||
case(TxD_state) |
|||
4'b0000: if(TxD_start) TxD_state <= 4'b0100; |
|||
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit |
|||
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0 |
|||
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1 |
|||
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2 |
|||
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3 |
|||
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4 |
|||
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5 |
|||
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6 |
|||
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7 |
|||
4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1 |
|||
4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2 |
|||
default: if(BitTick) TxD_state <= 4'b0000; |
|||
endcase |
|||
end |
|||
|
|||
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits |
|||
endmodule |
|||
|
|||
|
|||
//////////////////////////////////////////////////////// |
|||
module async_receiver( |
|||
input clk, |
|||
input RxD, |
|||
output reg RxD_data_ready = 0, |
|||
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted |
|||
|
|||
// We also detect if a gap occurs in the received stream of characters |
|||
// That can be useful if multiple characters are sent in burst |
|||
// so that multiple characters can be treated as a "packet" |
|||
output RxD_idle, // asserted when no data has been received for a while |
|||
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high) |
|||
); |
|||
|
|||
parameter ClkFrequency = 25000000; // 25MHz |
|||
parameter Baud = 115200; |
|||
|
|||
parameter Oversampling = 8; // needs to be a power of 2 |
|||
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time |
|||
// 8 times oversampling by default, use 16 for higher quality reception |
|||
|
|||
generate |
|||
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling"); |
|||
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value"); |
|||
endgenerate |
|||
|
|||
//////////////////////////////// |
|||
reg [3:0] RxD_state = 0; |
|||
|
|||
`ifdef SIMULATION |
|||
wire RxD_bit = RxD; |
|||
wire sampleNow = 1'b1; // receive one bit per clock cycle |
|||
|
|||
`else |
|||
wire OversamplingTick; |
|||
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick)); |
|||
|
|||
// synchronize RxD to our clk domain |
|||
reg [1:0] RxD_sync = 2'b11; |
|||
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD}; |
|||
|
|||
// and filter it |
|||
reg [1:0] Filter_cnt = 2'b11; |
|||
reg RxD_bit = 1'b1; |
|||
|
|||
always @(posedge clk) |
|||
if(OversamplingTick) |
|||
begin |
|||
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1; |
|||
else |
|||
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1; |
|||
|
|||
if(Filter_cnt==2'b11) RxD_bit <= 1'b1; |
|||
else |
|||
if(Filter_cnt==2'b00) RxD_bit <= 1'b0; |
|||
end |
|||
|
|||
// and decide when is the good time to sample the RxD line |
|||
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction |
|||
localparam l2o = log2(Oversampling); |
|||
reg [l2o-2:0] OversamplingCnt = 0; |
|||
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1; |
|||
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1); |
|||
`endif |
|||
|
|||
// now we can accumulate the RxD bits in a shift-register |
|||
always @(posedge clk) |
|||
case(RxD_state) |
|||
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found? |
|||
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow |
|||
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0 |
|||
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1 |
|||
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2 |
|||
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3 |
|||
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4 |
|||
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5 |
|||
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6 |
|||
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7 |
|||
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit |
|||
default: RxD_state <= 4'b0000; |
|||
endcase |
|||
|
|||
always @(posedge clk) |
|||
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]}; |
|||
|
|||
//reg RxD_data_error = 0; |
|||
always @(posedge clk) |
|||
begin |
|||
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received |
|||
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received |
|||
end |
|||
|
|||
`ifdef SIMULATION |
|||
assign RxD_idle = 0; |
|||
`else |
|||
reg [l2o+1:0] GapCnt = 0; |
|||
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1; |
|||
assign RxD_idle = GapCnt[l2o+1]; |
|||
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0]; |
|||
`endif |
|||
|
|||
endmodule |
|||
|
|||
|
|||
//////////////////////////////////////////////////////// |
|||
// dummy module used to be able to raise an assertion in Verilog |
|||
module ASSERTION_ERROR(); |
|||
endmodule |
|||
|
|||
|
|||
//////////////////////////////////////////////////////// |
|||
module BaudTickGen( |
|||
input clk, enable, |
|||
output tick // generate a tick at the specified baud rate * oversampling |
|||
); |
|||
parameter ClkFrequency = 25000000; |
|||
parameter Baud = 115200; |
|||
parameter Oversampling = 1; |
|||
|
|||
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction |
|||
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte |
|||
reg [AccWidth:0] Acc = 0; |
|||
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow |
|||
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter); |
|||
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0]; |
|||
assign tick = Acc[AccWidth]; |
|||
endmodule |
|||
|
|||
|
|||
//////////////////////////////////////////////////////// |
|||
@ -1,44 +0,0 @@ |
|||
`timescale 1ns/1ns |
|||
module led_test |
|||
( |
|||
sys_clk, // system clock 50Mhz on board |
|||
rst_n, // reset ,low active |
|||
led // LED,use for control the LED signal on board |
|||
); |
|||
|
|||
input sys_clk; |
|||
input rst_n; |
|||
output [3:0] led; |
|||
|
|||
//define the time counter |
|||
reg [31:0] timer; |
|||
reg [3:0] led; |
|||
|
|||
|
|||
always @(posedge sys_clk or negedge rst_n) |
|||
begin |
|||
if (~rst_n) |
|||
timer <= 32'd0; // when the reset signal valid,time counter clearing |
|||
else if (timer == 32'd199_9999_9) //4 seconds count(50M*4-1=199999999) |
|||
timer <= 32'd0; //count done,clearing the time counter |
|||
else |
|||
timer <= timer + 1'b1; //timer counter = timer counter + 1 |
|||
end |
|||
|
|||
always @(posedge sys_clk or negedge rst_n) |
|||
begin |
|||
if (~rst_n) |
|||
led <= 4'b0000; //when the reset signal active |
|||
else if (timer == 32'd49_999_9) //time counter count to 1st sec,LED1 Extinguish |
|||
led <= 4'b0001; |
|||
else if (timer == 32'd99_999_9) //time counter count to 2nd sec,LED2 Extinguish |
|||
begin |
|||
led <= 4'b0010; |
|||
end |
|||
else if (timer == 32'd149_999_9) //time counter count to 3nd sec,LED3 Extinguish |
|||
led <= 4'b0100; |
|||
else if (timer == 32'd199_999_9) //time counter count to 4nd sec,LED4 Extinguish |
|||
led <= 4'b1000; |
|||
end |
|||
|
|||
endmodule |
|||
@ -0,0 +1,31 @@ |
|||
/* |
|||
* Hacky baud rate generator to divide a 50MHz clock into a 115200 baud |
|||
* rx/tx pair where the rx clcken oversamples by 16x. |
|||
*/ |
|||
module baud_rate_gen ( |
|||
input wire clk_50m, |
|||
output wire rxclk_en, |
|||
output wire txclk_en |
|||
); |
|||
|
|||
parameter RX_ACC_MAX = 50000000 / (115200 * 16); |
|||
parameter TX_ACC_MAX = 50000000 / 115200; |
|||
parameter RX_ACC_WIDTH = $clog2(RX_ACC_MAX); |
|||
parameter TX_ACC_WIDTH = $clog2(TX_ACC_MAX); |
|||
reg [RX_ACC_WIDTH - 1:0] rx_acc = 0; |
|||
reg [TX_ACC_WIDTH - 1:0] tx_acc = 0; |
|||
|
|||
assign rxclk_en = (rx_acc == 5'd0); |
|||
assign txclk_en = (tx_acc == 9'd0); |
|||
|
|||
always @(posedge clk_50m) begin |
|||
if (rx_acc == RX_ACC_MAX[RX_ACC_WIDTH-1:0]) rx_acc <= 0; |
|||
else rx_acc <= rx_acc + 5'b1; |
|||
end |
|||
|
|||
always @(posedge clk_50m) begin |
|||
if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH-1:0]) tx_acc <= 0; |
|||
else tx_acc <= tx_acc + 9'b1; |
|||
end |
|||
|
|||
endmodule |
|||
@ -0,0 +1,24 @@ |
|||
`timescale 1ns / 1ns |
|||
module Top ( |
|||
input sys_clk, |
|||
input rst_n, |
|||
output reg [3:0] led, |
|||
output wire test_io3, |
|||
output wire test_io4, |
|||
output wire test_io5, |
|||
output wire test_io6, |
|||
output wire test_io7, |
|||
output wire test_io8, |
|||
output wire test_io9, |
|||
output wire test_io10, |
|||
output wire test_io11, |
|||
output wire test_io12, |
|||
output wire test_io13, |
|||
output wire test_io14, |
|||
output wire test_io15, |
|||
output wire test_io16 |
|||
); |
|||
|
|||
|
|||
|
|||
endmodule |
|||
@ -0,0 +1,76 @@ |
|||
module transmitter ( |
|||
input wire [7:0] din, |
|||
input wire wr_en, |
|||
input wire clk_50m, |
|||
input wire clken, |
|||
input wire rest_n, |
|||
output reg tx, |
|||
output wire tx_busy, |
|||
output wire [1:0] t_state, |
|||
output wire [2:0] t_bitpos, |
|||
output wire t_worksignal |
|||
); |
|||
parameter STATE_IDLE = 2'b00; |
|||
parameter STATE_START = 2'b01; |
|||
parameter STATE_DATA = 2'b10; |
|||
parameter STATE_STOP = 2'b11; |
|||
initial begin |
|||
tx = 1'b1; |
|||
end |
|||
|
|||
|
|||
reg [7:0] data = 8'h00; |
|||
reg [2:0] bitpos = 3'h0; |
|||
reg [1:0] state = STATE_IDLE; |
|||
reg worksignal = 0; |
|||
|
|||
assign workflag = (state != STATE_IDLE); |
|||
|
|||
always @(posedge clken, posedge wr_en) begin |
|||
if (wr_en) begin |
|||
worksignal <= 1'b1; |
|||
data <= din; |
|||
end else begin |
|||
if (!workflag) worksignal <= 1'b0; |
|||
end |
|||
end |
|||
|
|||
|
|||
always @(posedge clken or negedge rest_n) begin |
|||
if (!rest_n) begin |
|||
state <= STATE_IDLE; |
|||
end else begin |
|||
case (state) |
|||
STATE_IDLE: begin |
|||
tx <= 1'b1; |
|||
if (worksignal) begin |
|||
state <= STATE_START; |
|||
bitpos <= 0; |
|||
end |
|||
end |
|||
STATE_START: begin |
|||
tx <= 1'b0; |
|||
state <= STATE_DATA; |
|||
end |
|||
STATE_DATA: begin |
|||
if (bitpos == 3'h7) state <= STATE_STOP; |
|||
else bitpos <= bitpos + 3'h1; |
|||
tx <= data[bitpos]; |
|||
end |
|||
STATE_STOP: begin |
|||
tx <= 1'b1; |
|||
state <= STATE_IDLE; |
|||
end |
|||
default begin |
|||
tx <= 1'b1; |
|||
state <= STATE_IDLE; |
|||
end |
|||
endcase |
|||
end |
|||
end |
|||
|
|||
assign tx_busy = (state != STATE_IDLE); |
|||
assign t_state = state; |
|||
assign t_bitpos = bitpos; |
|||
assign t_worksignal = worksignal; |
|||
endmodule |
|||
@ -0,0 +1,129 @@ |
|||
module uart_reg_reader #( |
|||
parameter CLK_FRE = 50, //clock frequency(Mhz) |
|||
parameter BAUD_RATE = 115200 //serial baud rate |
|||
) ( |
|||
input clk, //clock input |
|||
input rst_n, //asynchronous reset input, low active |
|||
input wire [31:0] reg_data, //received serial data |
|||
output reg [ 7:0] reg_add, |
|||
output reg reg_add_valid, |
|||
input wire uart_rx_pin, |
|||
output wire uart_tx_pin |
|||
); |
|||
// |
|||
// overtime |
|||
// |----------------------^ |
|||
// v | |
|||
// IDLE ---------------> READ REG ADD ---------------> READ_REG ---------------> SEND_REG_DATA |
|||
// ^ | |
|||
// |------------------------------------------------------------------------------------v |
|||
// |
|||
// |
|||
// |
|||
// |
|||
|
|||
parameter STATE_IDLE = 0; |
|||
parameter STATE_READ_REG_ADD = 1; |
|||
parameter STATE_READ_REG = 2; |
|||
parameter STATE_SEND_REG_DATA = 3; |
|||
parameter STATE_WAIT_SEND_END = 4; |
|||
|
|||
|
|||
|
|||
wire [7:0] rx_data; |
|||
wire rx_data_valid; |
|||
wire rx_data_ready; |
|||
|
|||
wire tx_data_ready; |
|||
reg [7:0] tx_data; |
|||
reg tx_data_valid; |
|||
|
|||
reg [7:0] state; |
|||
reg [7:0] rxpacket_num; |
|||
reg [7:0] txpacket_num; |
|||
reg [7:0] rxdatacache; //接收数据buffer |
|||
|
|||
uart_rx #( |
|||
.CLK_FRE (CLK_FRE), |
|||
.BAUD_RATE(BAUD_RATE) |
|||
) uart_rx_impl ( |
|||
.clk (clk), // input |
|||
.rst_n (rst_n), // input |
|||
.rx_data (rx_data), // output |
|||
.rx_data_valid(rx_data_valid), // output |
|||
.rx_data_ready(rx_data_ready), // input |
|||
.rx_pin (uart_rx_pin) // input |
|||
); |
|||
|
|||
uart_tx #( |
|||
.CLK_FRE (CLK_FRE), |
|||
.BAUD_RATE(BAUD_RATE) |
|||
) uart_tx_impl ( |
|||
.clk (clk), // input |
|||
.rst_n (rst_n), // input |
|||
.tx_data (tx_data), // input |
|||
.tx_data_valid(tx_data_valid), // input |
|||
.tx_data_ready(tx_data_ready), // output |
|||
.tx_pin (uart_tx_pin) // output |
|||
); |
|||
|
|||
|
|||
assign rx_data_ready = 1'b1; |
|||
|
|||
reg [3:0] txdatastep = 0; |
|||
always @(posedge clk or negedge rst_n) begin |
|||
if (!rst_n) begin |
|||
state <= STATE_IDLE; |
|||
rxpacket_num <= 0; |
|||
txpacket_num <= 0; |
|||
txdatastep <= 0; |
|||
end else begin |
|||
case (state) |
|||
STATE_IDLE: begin |
|||
rxpacket_num <= 0; |
|||
txpacket_num <= 0; |
|||
txdatastep <= 0; |
|||
state <= STATE_READ_REG_ADD; |
|||
end |
|||
STATE_READ_REG_ADD: begin |
|||
if (rxpacket_num == 1) begin |
|||
state <= STATE_READ_REG; |
|||
end else if (rx_data_valid) begin |
|||
rxdatacache <= rx_data; |
|||
rxpacket_num <= rxpacket_num + 1; |
|||
end |
|||
end |
|||
STATE_READ_REG: begin |
|||
state <= STATE_SEND_REG_DATA; |
|||
end |
|||
STATE_SEND_REG_DATA: begin |
|||
case (txdatastep) |
|||
0: begin |
|||
tx_data <= rxdatacache; |
|||
tx_data_valid <= 1; |
|||
txpacket_num <= txpacket_num + 1; |
|||
txdatastep <= 1; |
|||
end |
|||
1: begin |
|||
tx_data_valid <= 0; |
|||
txdatastep <= 2; |
|||
end |
|||
2: begin |
|||
if (tx_data_ready) begin |
|||
if (txpacket_num != 4) begin |
|||
txdatastep <= 0; |
|||
end else begin |
|||
txdatastep <= 0; |
|||
state <= STATE_IDLE; |
|||
end |
|||
end |
|||
end |
|||
endcase |
|||
end |
|||
default begin |
|||
state <= STATE_IDLE; |
|||
end |
|||
endcase |
|||
end |
|||
end |
|||
endmodule |
|||
@ -0,0 +1,172 @@ |
|||
////////////////////////////////////////////////////////////////////////////////// |
|||
// // |
|||
// // |
|||
// Author: meisq // |
|||
// msq@qq.com // |
|||
// ALINX(shanghai) Technology Co.,Ltd // |
|||
// heijin // |
|||
// WEB: http://www.alinx.cn/ // |
|||
// BBS: http://www.heijin.org/ // |
|||
// // |
|||
////////////////////////////////////////////////////////////////////////////////// |
|||
// // |
|||
// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd // |
|||
// All rights reserved // |
|||
// // |
|||
// This source file may be used and distributed without restriction provided // |
|||
// that this copyright statement is not removed from the file and that any // |
|||
// derivative work contains the original copyright notice and the associated // |
|||
// disclaimer. // |
|||
// // |
|||
////////////////////////////////////////////////////////////////////////////////// |
|||
|
|||
//================================================================================ |
|||
// Revision History: |
|||
// Date By Revision Change Description |
|||
//-------------------------------------------------------------------------------- |
|||
//2017/8/1 1.0 Original |
|||
//*******************************************************************************/ |
|||
module uart_rx |
|||
#( |
|||
parameter CLK_FRE = 50, //clock frequency(Mhz) |
|||
parameter BAUD_RATE = 115200 //serial baud rate |
|||
) |
|||
( |
|||
input clk, //clock input |
|||
input rst_n, //asynchronous reset input, low active |
|||
output reg[7:0] rx_data, //received serial data |
|||
output reg rx_data_valid, //received serial data is valid |
|||
input rx_data_ready, //data receiver module ready |
|||
input rx_pin //serial data input |
|||
); |
|||
//calculates the clock cycle for baud rate |
|||
localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE; |
|||
//state machine code |
|||
localparam S_IDLE = 1; |
|||
localparam S_START = 2; //start bit |
|||
localparam S_REC_BYTE = 3; //data bits |
|||
localparam S_STOP = 4; //stop bit |
|||
localparam S_DATA = 5; |
|||
|
|||
reg[2:0] state; |
|||
reg[2:0] next_state; |
|||
reg rx_d0; //delay 1 clock for rx_pin |
|||
reg rx_d1; //delay 1 clock for rx_d0 |
|||
wire rx_negedge; //negedge of rx_pin |
|||
reg[7:0] rx_bits; //temporary storage of received data |
|||
reg[15:0] cycle_cnt; //baud counter |
|||
reg[2:0] bit_cnt; //bit counter |
|||
|
|||
assign |
|||
rx_negedge = rx_d1 && ~rx_d0; |
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
begin |
|||
rx_d0 <= 1'b0; |
|||
rx_d1 <= 1'b0; |
|||
end |
|||
else |
|||
begin |
|||
rx_d0 <= rx_pin; |
|||
rx_d1 <= rx_d0; |
|||
end |
|||
end |
|||
|
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
state <= S_IDLE; |
|||
else |
|||
state <= next_state; |
|||
end |
|||
|
|||
always@(*) |
|||
begin |
|||
case(state) |
|||
S_IDLE: |
|||
if(rx_negedge) |
|||
next_state <= S_START; |
|||
else |
|||
next_state <= S_IDLE; |
|||
S_START: |
|||
if(cycle_cnt == CYCLE - 1)//one data cycle |
|||
next_state <= S_REC_BYTE; |
|||
else |
|||
next_state <= S_START; |
|||
S_REC_BYTE: |
|||
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data |
|||
next_state <= S_STOP; |
|||
else |
|||
next_state <= S_REC_BYTE; |
|||
S_STOP: |
|||
if(cycle_cnt == CYCLE/2 - 1)//half bit cycle,to avoid missing the next byte receiver |
|||
next_state <= S_DATA; |
|||
else |
|||
next_state <= S_STOP; |
|||
S_DATA: |
|||
if(rx_data_ready) //data receive complete |
|||
next_state <= S_IDLE; |
|||
else |
|||
next_state <= S_DATA; |
|||
default: |
|||
next_state <= S_IDLE; |
|||
endcase |
|||
end |
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
rx_data_valid <= 1'b0; |
|||
else if(state == S_STOP && next_state != state) |
|||
rx_data_valid <= 1'b1; |
|||
else if(state == S_DATA && rx_data_ready) |
|||
rx_data_valid <= 1'b0; |
|||
end |
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
rx_data <= 8'd0; |
|||
else if(state == S_STOP && next_state != state) |
|||
rx_data <= rx_bits;//latch received data |
|||
end |
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
begin |
|||
bit_cnt <= 3'd0; |
|||
end |
|||
else if(state == S_REC_BYTE) |
|||
if(cycle_cnt == CYCLE - 1) |
|||
bit_cnt <= bit_cnt + 3'd1; |
|||
else |
|||
bit_cnt <= bit_cnt; |
|||
else |
|||
bit_cnt <= 3'd0; |
|||
end |
|||
|
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
cycle_cnt <= 16'd0; |
|||
else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state) |
|||
cycle_cnt <= 16'd0; |
|||
else |
|||
cycle_cnt <= cycle_cnt + 16'd1; |
|||
end |
|||
//receive serial data bit data |
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
rx_bits <= 8'd0; |
|||
else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1) |
|||
rx_bits[bit_cnt] <= rx_pin; |
|||
else |
|||
rx_bits <= rx_bits; |
|||
end |
|||
endmodule |
|||
@ -0,0 +1,161 @@ |
|||
////////////////////////////////////////////////////////////////////////////////// |
|||
// // |
|||
// // |
|||
// Author: meisq // |
|||
// msq@qq.com // |
|||
// ALINX(shanghai) Technology Co.,Ltd // |
|||
// heijin // |
|||
// WEB: http://www.alinx.cn/ // |
|||
// BBS: http://www.heijin.org/ // |
|||
// // |
|||
////////////////////////////////////////////////////////////////////////////////// |
|||
// // |
|||
// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd // |
|||
// All rights reserved // |
|||
// // |
|||
// This source file may be used and distributed without restriction provided // |
|||
// that this copyright statement is not removed from the file and that any // |
|||
// derivative work contains the original copyright notice and the associated // |
|||
// disclaimer. // |
|||
// // |
|||
////////////////////////////////////////////////////////////////////////////////// |
|||
|
|||
//================================================================================ |
|||
// Revision History: |
|||
// Date By Revision Change Description |
|||
//-------------------------------------------------------------------------------- |
|||
//2017/8/1 1.0 Original |
|||
//*******************************************************************************/ |
|||
module uart_tx |
|||
#( |
|||
parameter CLK_FRE = 50, //clock frequency(Mhz) |
|||
parameter BAUD_RATE = 115200 //serial baud rate |
|||
) |
|||
( |
|||
input clk, //clock input |
|||
input rst_n, //asynchronous reset input, low active |
|||
input[7:0] tx_data, //data to send |
|||
input tx_data_valid, //data to be sent is valid |
|||
output reg tx_data_ready, //send ready |
|||
output tx_pin //serial data output |
|||
); |
|||
//calculates the clock cycle for baud rate |
|||
localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE; |
|||
//state machine code |
|||
localparam S_IDLE = 1; |
|||
localparam S_START = 2;//start bit |
|||
localparam S_SEND_BYTE = 3;//data bits |
|||
localparam S_STOP = 4;//stop bit |
|||
reg[2:0] state; |
|||
reg[2:0] next_state; |
|||
reg[15:0] cycle_cnt; //baud counter |
|||
reg[2:0] bit_cnt;//bit counter |
|||
reg[7:0] tx_data_latch; //latch data to send |
|||
reg tx_reg; //serial data output |
|||
assign tx_pin = tx_reg; |
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
state <= S_IDLE; |
|||
else |
|||
state <= next_state; |
|||
end |
|||
|
|||
always@(*) |
|||
begin |
|||
case(state) |
|||
S_IDLE: |
|||
if(tx_data_valid == 1'b1) |
|||
next_state <= S_START; |
|||
else |
|||
next_state <= S_IDLE; |
|||
S_START: |
|||
if(cycle_cnt == CYCLE - 1) |
|||
next_state <= S_SEND_BYTE; |
|||
else |
|||
next_state <= S_START; |
|||
S_SEND_BYTE: |
|||
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) |
|||
next_state <= S_STOP; |
|||
else |
|||
next_state <= S_SEND_BYTE; |
|||
S_STOP: |
|||
if(cycle_cnt == CYCLE - 1) |
|||
next_state <= S_IDLE; |
|||
else |
|||
next_state <= S_STOP; |
|||
default: |
|||
next_state <= S_IDLE; |
|||
endcase |
|||
end |
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
begin |
|||
tx_data_ready <= 1'b0; |
|||
end |
|||
else if(state == S_IDLE) |
|||
if(tx_data_valid == 1'b1) |
|||
tx_data_ready <= 1'b0; |
|||
else |
|||
tx_data_ready <= 1'b1; |
|||
else if(state == S_STOP && cycle_cnt == CYCLE - 1) |
|||
tx_data_ready <= 1'b1; |
|||
end |
|||
|
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
begin |
|||
tx_data_latch <= 8'd0; |
|||
end |
|||
else if(state == S_IDLE && tx_data_valid == 1'b1) |
|||
tx_data_latch <= tx_data; |
|||
|
|||
end |
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
begin |
|||
bit_cnt <= 3'd0; |
|||
end |
|||
else if(state == S_SEND_BYTE) |
|||
if(cycle_cnt == CYCLE - 1) |
|||
bit_cnt <= bit_cnt + 3'd1; |
|||
else |
|||
bit_cnt <= bit_cnt; |
|||
else |
|||
bit_cnt <= 3'd0; |
|||
end |
|||
|
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
cycle_cnt <= 16'd0; |
|||
else if((state == S_SEND_BYTE && cycle_cnt == CYCLE - 1) || next_state != state) |
|||
cycle_cnt <= 16'd0; |
|||
else |
|||
cycle_cnt <= cycle_cnt + 16'd1; |
|||
end |
|||
|
|||
always@(posedge clk or negedge rst_n) |
|||
begin |
|||
if(rst_n == 1'b0) |
|||
tx_reg <= 1'b1; |
|||
else |
|||
case(state) |
|||
S_IDLE,S_STOP: |
|||
tx_reg <= 1'b1; |
|||
S_START: |
|||
tx_reg <= 1'b0; |
|||
S_SEND_BYTE: |
|||
tx_reg <= tx_data_latch[bit_cnt]; |
|||
default: |
|||
tx_reg <= 1'b1; |
|||
endcase |
|||
end |
|||
|
|||
endmodule |
|||
@ -1,35 +0,0 @@ |
|||
`timescale 1ns / 1ns |
|||
////////////////////////////////////////////////////////////////////////////////// |
|||
// Module Name: vtf_led_test |
|||
////////////////////////////////////////////////////////////////////////////////// |
|||
|
|||
module vtf_led_test; |
|||
// Inputs |
|||
reg sys_clk; |
|||
reg rst_n; |
|||
|
|||
// Outputs |
|||
wire [3:0] led; |
|||
|
|||
// Instantiate the Unit Under Test (UUT) |
|||
led_test uut ( |
|||
.sys_clk(sys_clk), |
|||
.rst_n(rst_n), |
|||
.led(led) |
|||
); |
|||
|
|||
initial begin |
|||
// Initialize Inputs |
|||
sys_clk = 0; |
|||
rst_n = 0; |
|||
|
|||
// Wait 100 ns for global reset to finish |
|||
#1000; |
|||
rst_n = 1; |
|||
// Add stimulus here |
|||
#20000; |
|||
// $stop; |
|||
end |
|||
|
|||
always #10 sys_clk = ~ sys_clk; //20ns |
|||
endmodule |
|||
@ -0,0 +1,30 @@ |
|||
`timescale 1ns / 1ns |
|||
module test_baud_rate_gen; |
|||
// Inputs |
|||
reg clk_50m; |
|||
reg rst_n; |
|||
|
|||
wire rxclk_en; |
|||
wire txclk_en; |
|||
|
|||
baud_rate_gen baud_rate_gen_impl ( |
|||
.clk_50m (clk_50m), |
|||
.rxclk_en(rxclk_en), |
|||
.txclk_en(txclk_en) |
|||
); |
|||
|
|||
initial begin |
|||
// Initialize Inputs |
|||
clk_50m = 0; |
|||
rst_n = 0; |
|||
|
|||
#100; |
|||
rst_n = 1; |
|||
|
|||
#15; |
|||
|
|||
#100000; |
|||
$stop; |
|||
end |
|||
always #10 clk_50m = ~clk_50m; //20ns 50MHZ |
|||
endmodule |
|||
@ -0,0 +1,50 @@ |
|||
`timescale 1ns / 1ns |
|||
module test_top; |
|||
// Inputs |
|||
reg clk_50m; |
|||
reg rst_n; |
|||
|
|||
wire rxclk_en; |
|||
wire txclk_en; |
|||
|
|||
wire [3:0] led; |
|||
wire test_io3; |
|||
wire test_io4; |
|||
wire test_io5; |
|||
wire test_io6; |
|||
wire test_io7; |
|||
wire test_io8; |
|||
wire test_io9; |
|||
wire test_io10; |
|||
wire test_io11; |
|||
|
|||
Top top_impl ( |
|||
.sys_clk(clk_50m), |
|||
.rst_n(rst_n), |
|||
.led(led), |
|||
.test_io3(test_io3), |
|||
.test_io4(test_io4), |
|||
.test_io5(test_io5), |
|||
.test_io6(test_io6), |
|||
.test_io7(test_io7), |
|||
.test_io8(test_io8), |
|||
.test_io9(test_io9), |
|||
.test_io10(test_io10), |
|||
.test_io11(test_io11) |
|||
); |
|||
|
|||
initial begin |
|||
// Initialize Inputs |
|||
clk_50m = 0; |
|||
rst_n = 0; |
|||
|
|||
#100; |
|||
rst_n = 1; |
|||
|
|||
#15; |
|||
|
|||
#300000; |
|||
$stop; |
|||
end |
|||
always #10 clk_50m = ~clk_50m; //20ns 50MHZ |
|||
endmodule |
|||
@ -0,0 +1,51 @@ |
|||
`timescale 1ns / 1ns |
|||
module test_transmitter; |
|||
// Inputs |
|||
reg clk_50m; |
|||
reg rst_n; |
|||
|
|||
|
|||
reg [7:0] din; |
|||
reg wr_en; |
|||
wire tx; |
|||
wire tx_busy; |
|||
|
|||
wire rxclk_en; |
|||
wire txclk_en; |
|||
|
|||
|
|||
baud_rate_gen baud_rate_gen_impl ( |
|||
.clk_50m (clk_50m), |
|||
.rxclk_en(rxclk_en), |
|||
.txclk_en(txclk_en) |
|||
); |
|||
|
|||
transmitter transmitter_impl ( |
|||
.din(din), |
|||
.wr_en(wr_en), |
|||
.clk_50m(clk_50m), |
|||
.clken(txclk_en), |
|||
.tx(tx), |
|||
.tx_busy(tx_busy) |
|||
); |
|||
|
|||
initial begin |
|||
// Initialize Inputs |
|||
clk_50m = 0; |
|||
rst_n = 0; |
|||
|
|||
#10; |
|||
rst_n = 1; |
|||
|
|||
#11; |
|||
din = 8'h55; |
|||
wr_en = 1'b1; |
|||
|
|||
#15; |
|||
wr_en = 0; |
|||
|
|||
#300000; |
|||
$stop; |
|||
end |
|||
always #10 clk_50m = ~clk_50m; //20ns 50MHZ |
|||
endmodule |
|||
@ -0,0 +1,66 @@ |
|||
`timescale 1ns / 1ns |
|||
module test_uart_reg_reader; |
|||
// Inputs |
|||
reg clk_50m; |
|||
reg rst_n; |
|||
|
|||
reg [31:0] reg_data; |
|||
wire [7:0] reg_add; |
|||
wire reg_add_valid; |
|||
reg uart_rx_pin; |
|||
wire uart_tx_pin; |
|||
|
|||
uart_reg_reader uart_reg_reader_impl ( |
|||
.clk(clk_50m), |
|||
.rst_n(rst_n), |
|||
.reg_data(reg_data), |
|||
.reg_add(reg_add), |
|||
.reg_add_valid(reg_add_valid), |
|||
.uart_rx_pin(uart_rx_pin), |
|||
.uart_tx_pin(uart_tx_pin) |
|||
); |
|||
|
|||
|
|||
initial begin |
|||
// Initialize Inputs |
|||
clk_50m = 0; |
|||
rst_n = 0; |
|||
reg_data = 0; |
|||
uart_rx_pin = 1; |
|||
|
|||
#10; |
|||
rst_n = 1; |
|||
|
|||
#1000; |
|||
uart_rx_pin = 1; |
|||
|
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 0; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 1; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 0; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 1; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 0; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 1; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 0; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 1; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 0; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 1; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 0; |
|||
#(8.680 * 1000); |
|||
uart_rx_pin = 1; |
|||
|
|||
#(100 * 8.680 * 1000); |
|||
$stop; |
|||
end |
|||
always #10 clk_50m = ~clk_50m; //20ns 50MHZ |
|||
endmodule |
|||
Write
Preview
Loading…
Cancel
Save
Reference in new issue