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p_camera_light_source_timing_controller
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pango_fpga_blank_project
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fpga所有引脚均未初始化,空白工程,防止烧板
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2.1 MiB
Verilog
83.4%
C++
14.2%
VHDL
2.1%
Batchfile
0.2%
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master
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pango_fpga_blank_project
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pin.md
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