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@ -1,5 +1,5 @@ |
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/** |
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* Copyright (c) 2017 - 2021, Nordic Semiconductor ASA |
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* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA |
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* |
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* All rights reserved. |
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* |
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@ -3111,6 +3111,134 @@ |
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// </e> |
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// <e> NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver |
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//========================================================== |
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#ifndef NRFX_QSPI_ENABLED |
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#define NRFX_QSPI_ENABLED 0 |
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#endif |
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// <o> NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255> |
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#ifndef NRFX_QSPI_CONFIG_SCK_DELAY |
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#define NRFX_QSPI_CONFIG_SCK_DELAY 1 |
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#endif |
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// <o> NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. |
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#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET |
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#define NRFX_QSPI_CONFIG_XIP_OFFSET 0 |
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#endif |
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// <o> NRFX_QSPI_CONFIG_READOC - Number of data lines and opcode used for reading. |
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// <0=> FastRead |
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// <1=> Read2O |
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// <2=> Read2IO |
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// <3=> Read4O |
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// <4=> Read4IO |
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#ifndef NRFX_QSPI_CONFIG_READOC |
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#define NRFX_QSPI_CONFIG_READOC 0 |
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#endif |
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// <o> NRFX_QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing. |
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// <0=> PP |
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// <1=> PP2O |
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// <2=> PP4O |
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// <3=> PP4IO |
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#ifndef NRFX_QSPI_CONFIG_WRITEOC |
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#define NRFX_QSPI_CONFIG_WRITEOC 0 |
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#endif |
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// <o> NRFX_QSPI_CONFIG_ADDRMODE - Addressing mode. |
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// <0=> 24bit |
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// <1=> 32bit |
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#ifndef NRFX_QSPI_CONFIG_ADDRMODE |
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#define NRFX_QSPI_CONFIG_ADDRMODE 0 |
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#endif |
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// <o> NRFX_QSPI_CONFIG_MODE - SPI mode. |
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// <0=> Mode 0 |
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// <1=> Mode 1 |
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#ifndef NRFX_QSPI_CONFIG_MODE |
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#define NRFX_QSPI_CONFIG_MODE 0 |
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#endif |
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// <o> NRFX_QSPI_CONFIG_FREQUENCY - Frequency divider. |
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// <0=> 32MHz/1 |
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// <1=> 32MHz/2 |
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// <2=> 32MHz/3 |
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// <3=> 32MHz/4 |
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// <4=> 32MHz/5 |
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// <5=> 32MHz/6 |
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// <6=> 32MHz/7 |
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// <7=> 32MHz/8 |
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// <8=> 32MHz/9 |
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// <9=> 32MHz/10 |
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// <10=> 32MHz/11 |
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// <11=> 32MHz/12 |
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// <12=> 32MHz/13 |
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// <13=> 32MHz/14 |
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// <14=> 32MHz/15 |
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// <15=> 32MHz/16 |
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#ifndef NRFX_QSPI_CONFIG_FREQUENCY |
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#define NRFX_QSPI_CONFIG_FREQUENCY 15 |
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#endif |
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// <s> NRFX_QSPI_PIN_SCK - SCK pin value. |
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#ifndef NRFX_QSPI_PIN_SCK |
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#define NRFX_QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED |
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#endif |
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// <s> NRFX_QSPI_PIN_CSN - CSN pin value. |
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#ifndef NRFX_QSPI_PIN_CSN |
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#define NRFX_QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED |
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#endif |
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// <s> NRFX_QSPI_PIN_IO0 - IO0 pin value. |
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#ifndef NRFX_QSPI_PIN_IO0 |
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#define NRFX_QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED |
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#endif |
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// <s> NRFX_QSPI_PIN_IO1 - IO1 pin value. |
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#ifndef NRFX_QSPI_PIN_IO1 |
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#define NRFX_QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED |
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#endif |
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// <s> NRFX_QSPI_PIN_IO2 - IO2 pin value. |
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#ifndef NRFX_QSPI_PIN_IO2 |
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#define NRFX_QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED |
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#endif |
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// <s> NRFX_QSPI_PIN_IO3 - IO3 pin value. |
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#ifndef NRFX_QSPI_PIN_IO3 |
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#define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED |
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#endif |
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// <o> NRFX_QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority |
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// <0=> 0 (highest) |
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// <1=> 1 |
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// <2=> 2 |
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// <3=> 3 |
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// <4=> 4 |
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// <5=> 5 |
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// <6=> 6 |
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// <7=> 7 |
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#ifndef NRFX_QSPI_CONFIG_IRQ_PRIORITY |
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#define NRFX_QSPI_CONFIG_IRQ_PRIORITY 6 |
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#endif |
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// </e> |
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// <e> NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver |
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//========================================================== |
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#ifndef NRFX_RNG_ENABLED |
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@ -7606,7 +7734,7 @@ |
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// <e> NRF_LOG_BACKEND_RTT_ENABLED - nrf_log_backend_rtt - Log RTT backend |
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//========================================================== |
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#ifndef NRF_LOG_BACKEND_RTT_ENABLED |
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#define NRF_LOG_BACKEND_RTT_ENABLED 0 |
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#define NRF_LOG_BACKEND_RTT_ENABLED 1 |
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#endif |
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// <o> NRF_LOG_BACKEND_RTT_TEMP_BUFFER_SIZE - Size of buffer for partially processed strings. |
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// <i> Size of the buffer is a trade-off between RAM usage and processing. |
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@ -7636,10 +7764,55 @@ |
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// </e> |
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// <e> NRF_LOG_BACKEND_UART_ENABLED - nrf_log_backend_uart - Log UART backend |
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//========================================================== |
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#ifndef NRF_LOG_BACKEND_UART_ENABLED |
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#define NRF_LOG_BACKEND_UART_ENABLED 1 |
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#endif |
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// <o> NRF_LOG_BACKEND_UART_TX_PIN - UART TX pin |
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#ifndef NRF_LOG_BACKEND_UART_TX_PIN |
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#define NRF_LOG_BACKEND_UART_TX_PIN 2 |
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#endif |
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// <o> NRF_LOG_BACKEND_UART_BAUDRATE - Default Baudrate |
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// <323584=> 1200 baud |
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// <643072=> 2400 baud |
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// <1290240=> 4800 baud |
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// <2576384=> 9600 baud |
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// <3862528=> 14400 baud |
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// <5152768=> 19200 baud |
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// <7716864=> 28800 baud |
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// <10289152=> 38400 baud |
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// <15400960=> 57600 baud |
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// <20615168=> 76800 baud |
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// <30801920=> 115200 baud |
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// <61865984=> 230400 baud |
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// <67108864=> 250000 baud |
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// <121634816=> 460800 baud |
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// <251658240=> 921600 baud |
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// <268435456=> 1000000 baud |
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#ifndef NRF_LOG_BACKEND_UART_BAUDRATE |
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#define NRF_LOG_BACKEND_UART_BAUDRATE 30801920 |
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#endif |
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// <o> NRF_LOG_BACKEND_UART_TEMP_BUFFER_SIZE - Size of buffer for partially processed strings. |
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// <i> Size of the buffer is a trade-off between RAM usage and processing. |
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// <i> if buffer is smaller then strings will often be fragmented. |
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// <i> It is recommended to use size which will fit typical log and only the |
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// <i> longer one will be fragmented. |
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#ifndef NRF_LOG_BACKEND_UART_TEMP_BUFFER_SIZE |
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#define NRF_LOG_BACKEND_UART_TEMP_BUFFER_SIZE 64 |
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#endif |
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// </e> |
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// <e> NRF_LOG_ENABLED - nrf_log - Logger |
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//========================================================== |
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#ifndef NRF_LOG_ENABLED |
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#define NRF_LOG_ENABLED 0 |
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#define NRF_LOG_ENABLED 1 |
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#endif |
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// <h> Log message pool - Configuration of log message pool |
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@ -10590,7 +10763,7 @@ |
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#ifndef NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED |
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#define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 0 |
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#define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1 |
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#endif |
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// </h> |
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// <i> Requested BLE GAP data length to be negotiated. |
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#ifndef NRF_SDH_BLE_GAP_DATA_LENGTH |
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#define NRF_SDH_BLE_GAP_DATA_LENGTH 251 |
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#define NRF_SDH_BLE_GAP_DATA_LENGTH 27 |
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#endif |
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// <o> NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links. |
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