33 changed files with 183 additions and 21692 deletions
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54.mxproject
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4.settings/language.settings.xml
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52Core/Inc/adc.h
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52Core/Inc/i2c.h
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4Core/Inc/stm32f4xx_hal_conf.h
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4Core/Inc/stm32f4xx_it.h
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5Core/Inc/tim.h
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3Core/Inc/usart.h
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130Core/Src/adc.c
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7Core/Src/dma.c
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38Core/Src/gpio.c
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116Core/Src/i2c.c
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6Core/Src/main.c
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60Core/Src/stm32f4xx_it.c
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168Core/Src/tim.c
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156Core/Src/usart.c
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898Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h
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407Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h
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741Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h
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115Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h
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4779Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h
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1890Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h
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2110Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c
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1112Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c
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7524Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c
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182Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c
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922Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c
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10README.md
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BINTMC5160_V2.pdf
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231graphite_digester_tmc5160.ioc
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2graphite_digester_tmc5160.launch
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45usrc/board.h
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48usrc/main.cpp
54
.mxproject
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@ -1,52 +0,0 @@ |
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/* USER CODE BEGIN Header */ |
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/** |
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****************************************************************************** |
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* @file adc.h |
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* @brief This file contains all the function prototypes for |
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* the adc.c file |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2023 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file |
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* in the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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* |
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****************************************************************************** |
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*/ |
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/* USER CODE END Header */ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __ADC_H__ |
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#define __ADC_H__ |
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|
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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|
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/* Includes ------------------------------------------------------------------*/ |
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#include "main.h" |
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|
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/* USER CODE BEGIN Includes */ |
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/* USER CODE END Includes */ |
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extern ADC_HandleTypeDef hadc1; |
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/* USER CODE BEGIN Private defines */ |
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/* USER CODE END Private defines */ |
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void MX_ADC1_Init(void); |
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/* USER CODE BEGIN Prototypes */ |
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/* USER CODE END Prototypes */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __ADC_H__ */ |
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@ -1,52 +0,0 @@ |
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/* USER CODE BEGIN Header */ |
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/** |
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****************************************************************************** |
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* @file i2c.h |
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* @brief This file contains all the function prototypes for |
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* the i2c.c file |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2023 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file |
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* in the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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* |
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****************************************************************************** |
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*/ |
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/* USER CODE END Header */ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __I2C_H__ |
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#define __I2C_H__ |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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|
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/* Includes ------------------------------------------------------------------*/ |
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#include "main.h" |
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|
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/* USER CODE BEGIN Includes */ |
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/* USER CODE END Includes */ |
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extern I2C_HandleTypeDef hi2c1; |
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/* USER CODE BEGIN Private defines */ |
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/* USER CODE END Private defines */ |
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void MX_I2C1_Init(void); |
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/* USER CODE BEGIN Prototypes */ |
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/* USER CODE END Prototypes */ |
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#ifdef __cplusplus |
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} |
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#endif |
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#endif /* __I2C_H__ */ |
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@ -1,130 +0,0 @@ |
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/* USER CODE BEGIN Header */ |
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/** |
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****************************************************************************** |
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* @file adc.c |
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* @brief This file provides code for the configuration |
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* of the ADC instances. |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2023 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file |
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* in the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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* |
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****************************************************************************** |
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*/ |
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/* USER CODE END Header */ |
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/* Includes ------------------------------------------------------------------*/ |
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#include "adc.h" |
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/* USER CODE BEGIN 0 */ |
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/* USER CODE END 0 */ |
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ADC_HandleTypeDef hadc1; |
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|
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/* ADC1 init function */ |
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void MX_ADC1_Init(void) |
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{ |
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/* USER CODE BEGIN ADC1_Init 0 */ |
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/* USER CODE END ADC1_Init 0 */ |
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ADC_ChannelConfTypeDef sConfig = {0}; |
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/* USER CODE BEGIN ADC1_Init 1 */ |
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/* USER CODE END ADC1_Init 1 */ |
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/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) |
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*/ |
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hadc1.Instance = ADC1; |
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hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; |
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hadc1.Init.Resolution = ADC_RESOLUTION_12B; |
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hadc1.Init.ScanConvMode = DISABLE; |
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hadc1.Init.ContinuousConvMode = DISABLE; |
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hadc1.Init.DiscontinuousConvMode = DISABLE; |
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hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; |
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hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; |
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hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; |
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hadc1.Init.NbrOfConversion = 1; |
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hadc1.Init.DMAContinuousRequests = DISABLE; |
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hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; |
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if (HAL_ADC_Init(&hadc1) != HAL_OK) |
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{ |
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Error_Handler(); |
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} |
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|
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/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. |
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*/ |
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sConfig.Channel = ADC_CHANNEL_8; |
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sConfig.Rank = 1; |
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sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; |
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if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) |
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{ |
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Error_Handler(); |
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} |
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/* USER CODE BEGIN ADC1_Init 2 */ |
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/* USER CODE END ADC1_Init 2 */ |
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} |
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void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) |
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{ |
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GPIO_InitTypeDef GPIO_InitStruct = {0}; |
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if(adcHandle->Instance==ADC1) |
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{ |
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/* USER CODE BEGIN ADC1_MspInit 0 */ |
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/* USER CODE END ADC1_MspInit 0 */ |
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/* ADC1 clock enable */ |
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__HAL_RCC_ADC1_CLK_ENABLE(); |
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__HAL_RCC_GPIOB_CLK_ENABLE(); |
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/**ADC1 GPIO Configuration |
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PB0 ------> ADC1_IN8 |
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PB1 ------> ADC1_IN9 |
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*/ |
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GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; |
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GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; |
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GPIO_InitStruct.Pull = GPIO_NOPULL; |
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); |
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/* USER CODE BEGIN ADC1_MspInit 1 */ |
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/* USER CODE END ADC1_MspInit 1 */ |
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} |
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} |
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void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) |
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{ |
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if(adcHandle->Instance==ADC1) |
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{ |
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/* USER CODE BEGIN ADC1_MspDeInit 0 */ |
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/* USER CODE END ADC1_MspDeInit 0 */ |
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/* Peripheral clock disable */ |
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__HAL_RCC_ADC1_CLK_DISABLE(); |
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/**ADC1 GPIO Configuration |
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PB0 ------> ADC1_IN8 |
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PB1 ------> ADC1_IN9 |
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*/ |
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HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1); |
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/* USER CODE BEGIN ADC1_MspDeInit 1 */ |
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/* USER CODE END ADC1_MspDeInit 1 */ |
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} |
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} |
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/* USER CODE BEGIN 1 */ |
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/* USER CODE END 1 */ |
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@ -1,116 +0,0 @@ |
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/* USER CODE BEGIN Header */ |
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/** |
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****************************************************************************** |
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* @file i2c.c |
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* @brief This file provides code for the configuration |
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* of the I2C instances. |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2023 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file |
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* in the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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* |
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****************************************************************************** |
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*/ |
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/* USER CODE END Header */ |
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/* Includes ------------------------------------------------------------------*/ |
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#include "i2c.h" |
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/* USER CODE BEGIN 0 */ |
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/* USER CODE END 0 */ |
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I2C_HandleTypeDef hi2c1; |
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/* I2C1 init function */ |
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void MX_I2C1_Init(void) |
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{ |
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/* USER CODE BEGIN I2C1_Init 0 */ |
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/* USER CODE END I2C1_Init 0 */ |
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/* USER CODE BEGIN I2C1_Init 1 */ |
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/* USER CODE END I2C1_Init 1 */ |
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hi2c1.Instance = I2C1; |
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hi2c1.Init.ClockSpeed = 100000; |
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hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2; |
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hi2c1.Init.OwnAddress1 = 0; |
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hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; |
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hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; |
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hi2c1.Init.OwnAddress2 = 0; |
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hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; |
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hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; |
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if (HAL_I2C_Init(&hi2c1) != HAL_OK) |
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{ |
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Error_Handler(); |
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} |
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/* USER CODE BEGIN I2C1_Init 2 */ |
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/* USER CODE END I2C1_Init 2 */ |
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} |
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void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) |
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{ |
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GPIO_InitTypeDef GPIO_InitStruct = {0}; |
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if(i2cHandle->Instance==I2C1) |
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{ |
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/* USER CODE BEGIN I2C1_MspInit 0 */ |
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/* USER CODE END I2C1_MspInit 0 */ |
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__HAL_RCC_GPIOB_CLK_ENABLE(); |
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/**I2C1 GPIO Configuration |
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PB6 ------> I2C1_SCL |
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PB7 ------> I2C1_SDA |
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*/ |
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GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; |
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GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; |
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GPIO_InitStruct.Pull = GPIO_NOPULL; |
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
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GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; |
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HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); |
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/* I2C1 clock enable */ |
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__HAL_RCC_I2C1_CLK_ENABLE(); |
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/* USER CODE BEGIN I2C1_MspInit 1 */ |
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/* USER CODE END I2C1_MspInit 1 */ |
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} |
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} |
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void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) |
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{ |
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if(i2cHandle->Instance==I2C1) |
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{ |
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/* USER CODE BEGIN I2C1_MspDeInit 0 */ |
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/* USER CODE END I2C1_MspDeInit 0 */ |
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/* Peripheral clock disable */ |
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__HAL_RCC_I2C1_CLK_DISABLE(); |
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/**I2C1 GPIO Configuration |
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PB6 ------> I2C1_SCL |
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PB7 ------> I2C1_SDA |
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*/ |
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HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6); |
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HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7); |
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/* USER CODE BEGIN I2C1_MspDeInit 1 */ |
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/* USER CODE END I2C1_MspDeInit 1 */ |
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} |
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} |
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/* USER CODE BEGIN 1 */ |
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/* USER CODE END 1 */ |
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@ -1,898 +0,0 @@ |
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/** |
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****************************************************************************** |
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* @file stm32f4xx_hal_adc.h |
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* @author MCD Application Team |
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* @brief Header file containing functions prototypes of ADC HAL library. |
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****************************************************************************** |
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* @attention |
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* |
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* Copyright (c) 2017 STMicroelectronics. |
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* All rights reserved. |
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* |
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* This software is licensed under terms that can be found in the LICENSE file |
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* in the root directory of this software component. |
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* If no LICENSE file comes with this software, it is provided AS-IS. |
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* |
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****************************************************************************** |
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*/ |
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/* Define to prevent recursive inclusion -------------------------------------*/ |
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#ifndef __STM32F4xx_ADC_H |
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#define __STM32F4xx_ADC_H |
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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|
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/* Includes ------------------------------------------------------------------*/ |
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#include "stm32f4xx_hal_def.h" |
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/* Include low level driver */ |
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#include "stm32f4xx_ll_adc.h" |
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/** @addtogroup STM32F4xx_HAL_Driver |
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* @{ |
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*/ |
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/** @addtogroup ADC |
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* @{ |
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*/ |
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/* Exported types ------------------------------------------------------------*/ |
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/** @defgroup ADC_Exported_Types ADC Exported Types |
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* @{ |
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*/ |
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/** |
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* @brief Structure definition of ADC and regular group initialization |
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* @note Parameters of this structure are shared within 2 scopes: |
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* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. |
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* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. |
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* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. |
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* ADC state can be either: |
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* - For all parameters: ADC disabled |
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* - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. |
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* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. |
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* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
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* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). |
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*/ |
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typedef struct |
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{ |
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uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for |
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all the ADCs. |
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This parameter can be a value of @ref ADC_ClockPrescaler */ |
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uint32_t Resolution; /*!< Configures the ADC resolution. |
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This parameter can be a value of @ref ADC_Resolution */ |
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uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) |
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or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). |
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This parameter can be a value of @ref ADC_Data_align */ |
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uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. |
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This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. |
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If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). |
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Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). |
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If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). |
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Scan direction is upward: from rank1 to rank 'n'. |
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This parameter can be set to ENABLE or DISABLE */ |
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uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. |
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This parameter can be a value of @ref ADC_EOCSelection. |
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Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. |
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Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) |
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or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. |
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Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). |
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If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ |
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FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, |
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after the selected trigger occurred (software start or external trigger). |
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This parameter can be set to ENABLE or DISABLE. */ |
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uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. |
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To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. |
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This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ |
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FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). |
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Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
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Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
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This parameter can be set to ENABLE or DISABLE. */ |
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uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. |
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If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. |
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This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ |
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uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. |
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If set to ADC_SOFTWARE_START, external triggers are disabled. |
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If set to external trigger source, triggering is on event rising edge by default. |
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This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ |
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uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. |
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If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. |
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This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ |
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FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) |
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or in Continuous mode (DMA transfer unlimited, whatever number of conversions). |
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Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. |
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Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). |
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This parameter can be set to ENABLE or DISABLE. */ |
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}ADC_InitTypeDef; |
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|
|||
/** |
|||
* @brief Structure definition of ADC channel for regular group |
|||
* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. |
|||
* ADC can be either disabled or enabled without conversion on going on regular group. |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. |
|||
This parameter can be a value of @ref ADC_channels */ |
|||
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. |
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ |
|||
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. |
|||
Unit: ADC clock cycles |
|||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). |
|||
This parameter can be a value of @ref ADC_sampling_times |
|||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. |
|||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. |
|||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
|||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
|||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ |
|||
uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ |
|||
}ADC_ChannelConfTypeDef; |
|||
|
|||
/** |
|||
* @brief ADC Configuration multi-mode structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. |
|||
This parameter can be a value of @ref ADC_analog_watchdog_selection */ |
|||
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
|||
This parameter must be a 12-bit value. */ |
|||
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
|||
This parameter must be a 12-bit value. */ |
|||
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. |
|||
This parameter has an effect only if watchdog mode is configured on single channel |
|||
This parameter can be a value of @ref ADC_channels */ |
|||
FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured |
|||
is interrupt mode or in polling mode. |
|||
This parameter can be set to ENABLE or DISABLE */ |
|||
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ |
|||
}ADC_AnalogWDGConfTypeDef; |
|||
|
|||
/** |
|||
* @brief HAL ADC state machine: ADC states definition (bitfields) |
|||
*/ |
|||
/* States of ADC global scope */ |
|||
#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ |
|||
#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ |
|||
#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ |
|||
#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ |
|||
|
|||
/* States of ADC errors */ |
|||
#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ |
|||
#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ |
|||
#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ |
|||
|
|||
/* States of ADC group regular */ |
|||
#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, |
|||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ |
|||
#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ |
|||
#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */ |
|||
|
|||
/* States of ADC group injected */ |
|||
#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, |
|||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ |
|||
#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ |
|||
|
|||
/* States of ADC analog watchdogs */ |
|||
#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ |
|||
#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */ |
|||
#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */ |
|||
|
|||
/* States of ADC multi-mode */ |
|||
#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */ |
|||
|
|||
|
|||
/** |
|||
* @brief ADC handle Structure definition |
|||
*/ |
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
typedef struct __ADC_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif |
|||
{ |
|||
ADC_TypeDef *Instance; /*!< Register base address */ |
|||
|
|||
ADC_InitTypeDef Init; /*!< ADC required parameters */ |
|||
|
|||
__IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ |
|||
|
|||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< ADC locking object */ |
|||
|
|||
__IO uint32_t State; /*!< ADC communication state */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< ADC Error code */ |
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ |
|||
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ |
|||
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ |
|||
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ |
|||
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ |
|||
void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ |
|||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
|||
}ADC_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
/** |
|||
* @brief HAL ADC Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ |
|||
HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ |
|||
HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ |
|||
HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ |
|||
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ |
|||
HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */ |
|||
HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */ |
|||
} HAL_ADC_CallbackIDTypeDef; |
|||
|
|||
/** |
|||
* @brief HAL ADC Callback pointer definition |
|||
*/ |
|||
typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ |
|||
|
|||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup ADC_Exported_Constants ADC Exported Constants |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Error_Code ADC Error Code |
|||
* @{ |
|||
*/ |
|||
#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ |
|||
#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, |
|||
enable/disable, erroneous state */ |
|||
#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ |
|||
#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ |
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler |
|||
* @{ |
|||
*/ |
|||
#define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U |
|||
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) |
|||
#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) |
|||
#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases |
|||
* @{ |
|||
*/ |
|||
#define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U |
|||
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) |
|||
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) |
|||
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) |
|||
#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) |
|||
#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) |
|||
#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) |
|||
#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) |
|||
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) |
|||
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) |
|||
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Resolution ADC Resolution |
|||
* @{ |
|||
*/ |
|||
#define ADC_RESOLUTION_12B 0x00000000U |
|||
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) |
|||
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) |
|||
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular |
|||
* @{ |
|||
*/ |
|||
#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U |
|||
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) |
|||
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) |
|||
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular |
|||
* @{ |
|||
*/ |
|||
/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ |
|||
/* compatibility with other STM32 devices. */ |
|||
#define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U |
|||
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) |
|||
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) |
|||
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2) |
|||
#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3) |
|||
#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) |
|||
#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL) |
|||
#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Data_align ADC Data Align |
|||
* @{ |
|||
*/ |
|||
#define ADC_DATAALIGN_RIGHT 0x00000000U |
|||
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_channels ADC Common Channels |
|||
* @{ |
|||
*/ |
|||
#define ADC_CHANNEL_0 0x00000000U |
|||
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) |
|||
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) |
|||
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) |
|||
#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) |
|||
#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) |
|||
#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) |
|||
#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) |
|||
#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) |
|||
#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) |
|||
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) |
|||
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) |
|||
|
|||
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) |
|||
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_sampling_times ADC Sampling Times |
|||
* @{ |
|||
*/ |
|||
#define ADC_SAMPLETIME_3CYCLES 0x00000000U |
|||
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) |
|||
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) |
|||
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) |
|||
#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) |
|||
#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) |
|||
#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) |
|||
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_EOCSelection ADC EOC Selection |
|||
* @{ |
|||
*/ |
|||
#define ADC_EOC_SEQ_CONV 0x00000000U |
|||
#define ADC_EOC_SINGLE_CONV 0x00000001U |
|||
#define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_Event_type ADC Event Type |
|||
* @{ |
|||
*/ |
|||
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) |
|||
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection |
|||
* @{ |
|||
*/ |
|||
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) |
|||
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) |
|||
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) |
|||
#define ADC_ANALOGWATCHDOG_NONE 0x00000000U |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_interrupts_definition ADC Interrupts Definition |
|||
* @{ |
|||
*/ |
|||
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) |
|||
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) |
|||
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) |
|||
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_flags_definition ADC Flags Definition |
|||
* @{ |
|||
*/ |
|||
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) |
|||
#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) |
|||
#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) |
|||
#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) |
|||
#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) |
|||
#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADC_channels_type ADC Channels Type |
|||
* @{ |
|||
*/ |
|||
#define ADC_ALL_CHANNELS 0x00000001U |
|||
#define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */ |
|||
#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup ADC_Exported_Macros ADC Exported Macros |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset ADC handle state |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ |
|||
do{ \ |
|||
(__HANDLE__)->State = HAL_ADC_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ |
|||
((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
|||
#endif |
|||
|
|||
/** |
|||
* @brief Enable the ADC peripheral. |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) |
|||
|
|||
/** |
|||
* @brief Disable the ADC peripheral. |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) |
|||
|
|||
/** |
|||
* @brief Enable the ADC end of conversion interrupt. |
|||
* @param __HANDLE__ specifies the ADC Handle. |
|||
* @param __INTERRUPT__ ADC Interrupt. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) |
|||
|
|||
/** |
|||
* @brief Disable the ADC end of conversion interrupt. |
|||
* @param __HANDLE__ specifies the ADC Handle. |
|||
* @param __INTERRUPT__ ADC interrupt. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) |
|||
|
|||
/** @brief Check if the specified ADC interrupt source is enabled or disabled. |
|||
* @param __HANDLE__ specifies the ADC Handle. |
|||
* @param __INTERRUPT__ specifies the ADC interrupt source to check. |
|||
* @retval The new state of __IT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) |
|||
|
|||
/** |
|||
* @brief Clear the ADC's pending flags. |
|||
* @param __HANDLE__ specifies the ADC Handle. |
|||
* @param __FLAG__ ADC flag. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) |
|||
|
|||
/** |
|||
* @brief Get the selected ADC's flag status. |
|||
* @param __HANDLE__ specifies the ADC Handle. |
|||
* @param __FLAG__ ADC flag. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Include ADC HAL Extension module */ |
|||
#include "stm32f4xx_hal_adc_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup ADC_Exported_Functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group1 |
|||
* @{ |
|||
*/ |
|||
/* Initialization/de-initialization functions ***********************************/ |
|||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
|||
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
|||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
|||
|
|||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) |
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); |
|||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group2 |
|||
* @{ |
|||
*/ |
|||
/* I/O operation functions ******************************************************/ |
|||
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
|||
|
|||
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
|||
|
|||
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
|||
|
|||
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
|||
|
|||
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
|||
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
|||
|
|||
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
|||
|
|||
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
|||
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
|||
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
|||
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group3 |
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions *************************************************/ |
|||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
|||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_Exported_Functions_Group4 |
|||
* @{ |
|||
*/ |
|||
/* Peripheral State functions ***************************************************/ |
|||
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
|||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup ADC_Private_Constants ADC Private Constants |
|||
* @{ |
|||
*/ |
|||
/* Delay for ADC stabilization time. */ |
|||
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
|||
/* Unit: us */ |
|||
#define ADC_STAB_DELAY_US 3U |
|||
/* Delay for temperature sensor stabilization time. */ |
|||
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
|||
/* Unit: us */ |
|||
#define ADC_TEMPSENSOR_DELAY_US 10U |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macro ------------------------------------------------------------*/ |
|||
|
|||
/** @defgroup ADC_Private_Macros ADC Private Macros |
|||
* @{ |
|||
*/ |
|||
/* Macro reserved for internal HAL driver usage, not intended to be used in |
|||
code of final user */ |
|||
|
|||
/** |
|||
* @brief Verification of ADC state: enabled or disabled |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval SET (ADC enabled) or RESET (ADC disabled) |
|||
*/ |
|||
#define ADC_IS_ENABLE(__HANDLE__) \ |
|||
((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ |
|||
) ? SET : RESET) |
|||
|
|||
/** |
|||
* @brief Test if conversion trigger of regular group is software start |
|||
* or external trigger. |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval SET (software start) or RESET (external trigger) |
|||
*/ |
|||
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ |
|||
(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) |
|||
|
|||
/** |
|||
* @brief Test if conversion trigger of injected group is software start |
|||
* or external trigger. |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval SET (software start) or RESET (external trigger) |
|||
*/ |
|||
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ |
|||
(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) |
|||
|
|||
/** |
|||
* @brief Simultaneously clears and sets specific bits of the handle State |
|||
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), |
|||
* the first parameter is the ADC handle State, the second parameter is the |
|||
* bit field to clear, the third and last parameter is the bit field to set. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_STATE_CLR_SET MODIFY_REG |
|||
|
|||
/** |
|||
* @brief Clear ADC error code (set it to error code: "no error") |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ |
|||
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
|||
|
|||
|
|||
#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ |
|||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ |
|||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ |
|||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8)) |
|||
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ |
|||
((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) |
|||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ |
|||
((RESOLUTION) == ADC_RESOLUTION_10B) || \ |
|||
((RESOLUTION) == ADC_RESOLUTION_8B) || \ |
|||
((RESOLUTION) == ADC_RESOLUTION_6B)) |
|||
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) |
|||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ |
|||
((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \ |
|||
((REGTRIG) == ADC_SOFTWARE_START)) |
|||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
|||
((ALIGN) == ADC_DATAALIGN_LEFT)) |
|||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_15CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_28CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_56CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_84CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_112CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_144CYCLES) || \ |
|||
((TIME) == ADC_SAMPLETIME_480CYCLES)) |
|||
#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \ |
|||
((EOCSelection) == ADC_EOC_SEQ_CONV) || \ |
|||
((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV)) |
|||
#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ |
|||
((EVENT) == ADC_OVR_EVENT)) |
|||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ |
|||
((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) |
|||
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ |
|||
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ |
|||
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) |
|||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU) |
|||
|
|||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) |
|||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U))) |
|||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) |
|||
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ |
|||
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \ |
|||
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \ |
|||
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \ |
|||
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU))) |
|||
|
|||
/** |
|||
* @brief Set ADC Regular channel sequence length. |
|||
* @param _NbrOfConversion_ Regular channel sequence length. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U) |
|||
|
|||
/** |
|||
* @brief Set the ADC's sample time for channel numbers between 10 and 18. |
|||
* @param _SAMPLETIME_ Sample time parameter. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) |
|||
|
|||
/** |
|||
* @brief Set the ADC's sample time for channel numbers between 0 and 9. |
|||
* @param _SAMPLETIME_ Sample time parameter. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) |
|||
|
|||
/** |
|||
* @brief Set the selected regular channel rank for rank between 1 and 6. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @param _RANKNB_ Rank number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) |
|||
|
|||
/** |
|||
* @brief Set the selected regular channel rank for rank between 7 and 12. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @param _RANKNB_ Rank number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) |
|||
|
|||
/** |
|||
* @brief Set the selected regular channel rank for rank between 13 and 16. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @param _RANKNB_ Rank number. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) |
|||
|
|||
/** |
|||
* @brief Enable ADC continuous conversion mode. |
|||
* @param _CONTINUOUS_MODE_ Continuous mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U) |
|||
|
|||
/** |
|||
* @brief Configures the number of discontinuous conversions for the regular group channels. |
|||
* @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos) |
|||
|
|||
/** |
|||
* @brief Enable ADC scan mode. |
|||
* @param _SCANCONV_MODE_ Scan conversion mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U) |
|||
|
|||
/** |
|||
* @brief Enable the ADC end of conversion selection. |
|||
* @param _EOCSelection_MODE_ End of conversion selection mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U) |
|||
|
|||
/** |
|||
* @brief Enable the ADC DMA continuous request. |
|||
* @param _DMAContReq_MODE_ DMA continuous request mode. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U) |
|||
|
|||
/** |
|||
* @brief Return resolution bits in CR1 register. |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval None |
|||
*/ |
|||
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup ADC_Private_Functions ADC Private Functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /*__STM32F4xx_ADC_H */ |
|||
|
|||
|
|||
@ -1,407 +0,0 @@ |
|||
/** |
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_adc_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of ADC HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_ADC_EX_H |
|||
#define __STM32F4xx_ADC_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADCEx |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Exported_Types ADC Exported Types |
|||
* @{ |
|||
*/ |
|||
|
|||
/** |
|||
* @brief ADC Configuration injected Channel structure definition |
|||
* @note Parameters of this structure are shared within 2 scopes: |
|||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset |
|||
* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, |
|||
* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. |
|||
* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. |
|||
* ADC state can be either: |
|||
* - For all parameters: ADC disabled |
|||
* - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. |
|||
* - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure |
|||
This parameter can be a value of @ref ADC_channels |
|||
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ |
|||
uint32_t InjectedRank; /*!< Rank in the injected group sequencer |
|||
This parameter must be a value of @ref ADCEx_injected_rank |
|||
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ |
|||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. |
|||
Unit: ADC clock cycles |
|||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). |
|||
This parameter can be a value of @ref ADC_sampling_times |
|||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. |
|||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. |
|||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
|||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
|||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ |
|||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). |
|||
Offset value must be a positive number. |
|||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), |
|||
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
|||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. |
|||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. |
|||
This parameter must be a number between Min_Data = 1 and Max_Data = 4. |
|||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
|||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
|||
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). |
|||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
|||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
|||
This parameter can be set to ENABLE or DISABLE. |
|||
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. |
|||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
|||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
|||
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one |
|||
This parameter can be set to ENABLE or DISABLE. |
|||
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) |
|||
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) |
|||
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. |
|||
To maintain JAUTO always enabled, DMA must be configured in circular mode. |
|||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
|||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
|||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. |
|||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. |
|||
If set to external trigger source, triggering is on event rising edge. |
|||
This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected |
|||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). |
|||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) |
|||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
|||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
|||
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. |
|||
This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. |
|||
If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. |
|||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to |
|||
configure a channel on injected group can impact the configuration of other channels previously set. */ |
|||
}ADC_InjectionConfTypeDef; |
|||
|
|||
/** |
|||
* @brief ADC Configuration multi-mode structure definition |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. |
|||
This parameter can be a value of @ref ADCEx_Common_mode */ |
|||
uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. |
|||
This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ |
|||
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. |
|||
This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ |
|||
}ADC_MultiModeTypeDef; |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Exported_Constants ADC Exported Constants |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_Common_mode ADC Common Mode |
|||
* @{ |
|||
*/ |
|||
#define ADC_MODE_INDEPENDENT 0x00000000U |
|||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) |
|||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) |
|||
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) |
|||
#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) |
|||
#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) |
|||
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1)) |
|||
#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) |
|||
#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) |
|||
#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode |
|||
* @{ |
|||
*/ |
|||
#define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */ |
|||
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ |
|||
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ |
|||
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected |
|||
* @{ |
|||
*/ |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) |
|||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected |
|||
* @{ |
|||
*/ |
|||
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U |
|||
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) |
|||
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL) |
|||
#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_injected_rank ADC Injected Rank |
|||
* @{ |
|||
*/ |
|||
#define ADC_INJECTED_RANK_1 0x00000001U |
|||
#define ADC_INJECTED_RANK_2 0x00000002U |
|||
#define ADC_INJECTED_RANK_3 0x00000003U |
|||
#define ADC_INJECTED_RANK_4 0x00000004U |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup ADCEx_channels ADC Specific Channels |
|||
* @{ |
|||
*/ |
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ |
|||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ |
|||
defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ |
|||
defined(STM32F412Cx) |
|||
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) |
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx || |
|||
STM32F412Vx || STM32F412Rx || STM32F412Cx */ |
|||
|
|||
#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ |
|||
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
|||
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ |
|||
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) |
|||
#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/** @defgroup ADC_Exported_Macros ADC Exported Macros |
|||
* @{ |
|||
*/ |
|||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
|||
/** |
|||
* @brief Disable internal path of ADC channel Vbat |
|||
* @note Use case of this macro: |
|||
* On devices STM32F42x and STM32F43x, ADC internal channels |
|||
* Vbat and VrefInt share the same internal path, only |
|||
* one of them can be enabled.This macro is to be used when ADC |
|||
* channels Vbat and VrefInt are selected, and must be called |
|||
* before starting conversion of ADC channel VrefInt in order |
|||
* to disable ADC channel Vbat. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() (ADC->CCR &= ~(ADC_CCR_VBATE)) |
|||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup ADCEx_Exported_Functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADCEx_Exported_Functions_Group1 |
|||
* @{ |
|||
*/ |
|||
|
|||
/* I/O operation functions ******************************************************/ |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); |
|||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); |
|||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
|||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc); |
|||
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); |
|||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); |
|||
|
|||
/* Peripheral Control functions *************************************************/ |
|||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); |
|||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode); |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Private_Constants ADC Private Constants |
|||
* @{ |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Private_Macros ADC Private Macros |
|||
* @{ |
|||
*/ |
|||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ |
|||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ |
|||
defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ |
|||
defined(STM32F412Cx) |
|||
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18) |
|||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || |
|||
STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ |
|||
|
|||
#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \ |
|||
defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \ |
|||
defined(STM32F469xx) || defined(STM32F479xx) |
|||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ |
|||
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)) |
|||
#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
|||
|
|||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ |
|||
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ |
|||
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ |
|||
((MODE) == ADC_DUALMODE_INJECSIMULT) || \ |
|||
((MODE) == ADC_DUALMODE_REGSIMULT) || \ |
|||
((MODE) == ADC_DUALMODE_INTERL) || \ |
|||
((MODE) == ADC_DUALMODE_ALTERTRIG) || \ |
|||
((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \ |
|||
((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \ |
|||
((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \ |
|||
((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \ |
|||
((MODE) == ADC_TRIPLEMODE_INTERL) || \ |
|||
((MODE) == ADC_TRIPLEMODE_ALTERTRIG)) |
|||
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \ |
|||
((MODE) == ADC_DMAACCESSMODE_1) || \ |
|||
((MODE) == ADC_DMAACCESSMODE_2) || \ |
|||
((MODE) == ADC_DMAACCESSMODE_3)) |
|||
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \ |
|||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING)) |
|||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ |
|||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \ |
|||
((INJTRIG) == ADC_INJECTED_SOFTWARE_START)) |
|||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U)) |
|||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= 4U)) |
|||
|
|||
/** |
|||
* @brief Set the selected injected Channel rank. |
|||
* @param _CHANNELNB_ Channel number. |
|||
* @param _RANKNB_ Rank number. |
|||
* @param _JSQR_JL_ Sequence length. |
|||
* @retval None |
|||
*/ |
|||
#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_)))) |
|||
|
|||
/** |
|||
* @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1 |
|||
* if available (ADC2, ADC3 availability depends on STM32 product) |
|||
* @param __HANDLE__ ADC handle |
|||
* @retval Common control register ADC123 or ADC1 |
|||
*/ |
|||
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
|||
#define ADC_COMMON_REGISTER(__HANDLE__) ADC123_COMMON |
|||
#else |
|||
#define ADC_COMMON_REGISTER(__HANDLE__) ADC1_COMMON |
|||
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx || STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup ADCEx_Private_Functions ADC Private Functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /*__STM32F4xx_ADC_EX_H */ |
|||
|
|||
|
|||
@ -1,741 +0,0 @@ |
|||
/** |
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_i2c.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of I2C HAL module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_I2C_H |
|||
#define __STM32F4xx_HAL_I2C_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2C |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/** @defgroup I2C_Exported_Types I2C Exported Types |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition |
|||
* @brief I2C Configuration Structure definition |
|||
* @{ |
|||
*/ |
|||
typedef struct |
|||
{ |
|||
uint32_t ClockSpeed; /*!< Specifies the clock frequency. |
|||
This parameter must be set to a value lower than 400kHz */ |
|||
|
|||
uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. |
|||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ |
|||
|
|||
uint32_t OwnAddress1; /*!< Specifies the first device own address. |
|||
This parameter can be a 7-bit or 10-bit address. */ |
|||
|
|||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. |
|||
This parameter can be a value of @ref I2C_addressing_mode */ |
|||
|
|||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. |
|||
This parameter can be a value of @ref I2C_dual_addressing_mode */ |
|||
|
|||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected |
|||
This parameter can be a 7-bit address. */ |
|||
|
|||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. |
|||
This parameter can be a value of @ref I2C_general_call_addressing_mode */ |
|||
|
|||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. |
|||
This parameter can be a value of @ref I2C_nostretch_mode */ |
|||
|
|||
} I2C_InitTypeDef; |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HAL_state_structure_definition HAL state structure definition |
|||
* @brief HAL State structure definition |
|||
* @note HAL I2C State value coding follow below described bitmap : |
|||
* b7-b6 Error information |
|||
* 00 : No Error |
|||
* 01 : Abort (Abort user request on going) |
|||
* 10 : Timeout |
|||
* 11 : Error |
|||
* b5 Peripheral initialization status |
|||
* 0 : Reset (Peripheral not initialized) |
|||
* 1 : Init done (Peripheral initialized and ready to use. HAL I2C Init function called) |
|||
* b4 (not used) |
|||
* x : Should be set to 0 |
|||
* b3 |
|||
* 0 : Ready or Busy (No Listen mode ongoing) |
|||
* 1 : Listen (Peripheral in Address Listen Mode) |
|||
* b2 Intrinsic process state |
|||
* 0 : Ready |
|||
* 1 : Busy (Peripheral busy with some configuration or internal operations) |
|||
* b1 Rx state |
|||
* 0 : Ready (no Rx operation ongoing) |
|||
* 1 : Busy (Rx operation ongoing) |
|||
* b0 Tx state |
|||
* 0 : Ready (no Tx operation ongoing) |
|||
* 1 : Busy (Tx operation ongoing) |
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ |
|||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ |
|||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ |
|||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ |
|||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
|||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ |
|||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission |
|||
process is ongoing */ |
|||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception |
|||
process is ongoing */ |
|||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ |
|||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ |
|||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ |
|||
|
|||
} HAL_I2C_StateTypeDef; |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition |
|||
* @brief HAL Mode structure definition |
|||
* @note HAL I2C Mode value coding follow below described bitmap :\n |
|||
* b7 (not used)\n |
|||
* x : Should be set to 0\n |
|||
* b6\n |
|||
* 0 : None\n |
|||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n |
|||
* b5\n |
|||
* 0 : None\n |
|||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n |
|||
* b4\n |
|||
* 0 : None\n |
|||
* 1 : Master (HAL I2C communication is in Master Mode)\n |
|||
* b3-b2-b1-b0 (not used)\n |
|||
* xxxx : Should be set to 0000 |
|||
* @{ |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ |
|||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ |
|||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ |
|||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ |
|||
|
|||
} HAL_I2C_ModeTypeDef; |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition |
|||
* @brief I2C Error Code definition |
|||
* @{ |
|||
*/ |
|||
#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ |
|||
#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ |
|||
#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ |
|||
#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ |
|||
#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ |
|||
#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ |
|||
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ |
|||
#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */ |
|||
#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */ |
|||
#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */ |
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */ |
|||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition |
|||
* @brief I2C handle Structure definition |
|||
* @{ |
|||
*/ |
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
typedef struct __I2C_HandleTypeDef |
|||
#else |
|||
typedef struct |
|||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|||
{ |
|||
I2C_TypeDef *Instance; /*!< I2C registers base address */ |
|||
|
|||
I2C_InitTypeDef Init; /*!< I2C communication parameters */ |
|||
|
|||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ |
|||
|
|||
uint16_t XferSize; /*!< I2C transfer size */ |
|||
|
|||
__IO uint16_t XferCount; /*!< I2C transfer counter */ |
|||
|
|||
__IO uint32_t XferOptions; /*!< I2C transfer options */ |
|||
|
|||
__IO uint32_t PreviousState; /*!< I2C communication Previous state and mode |
|||
context for internal usage */ |
|||
|
|||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ |
|||
|
|||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ |
|||
|
|||
HAL_LockTypeDef Lock; /*!< I2C locking object */ |
|||
|
|||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ |
|||
|
|||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ |
|||
|
|||
__IO uint32_t ErrorCode; /*!< I2C Error code */ |
|||
|
|||
__IO uint32_t Devaddress; /*!< I2C Target device address */ |
|||
|
|||
__IO uint32_t Memaddress; /*!< I2C Target memory address */ |
|||
|
|||
__IO uint32_t MemaddSize; /*!< I2C Target memory address size */ |
|||
|
|||
__IO uint32_t EventCount; /*!< I2C Event counter */ |
|||
|
|||
|
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ |
|||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ |
|||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ |
|||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ |
|||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ |
|||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ |
|||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ |
|||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ |
|||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ |
|||
|
|||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ |
|||
|
|||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ |
|||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ |
|||
|
|||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|||
} I2C_HandleTypeDef; |
|||
|
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
/** |
|||
* @brief HAL I2C Callback ID enumeration definition |
|||
*/ |
|||
typedef enum |
|||
{ |
|||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ |
|||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ |
|||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ |
|||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ |
|||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ |
|||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ |
|||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ |
|||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ |
|||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ |
|||
|
|||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ |
|||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ |
|||
|
|||
} HAL_I2C_CallbackIDTypeDef; |
|||
|
|||
/** |
|||
* @brief HAL I2C Callback pointer definition |
|||
*/ |
|||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ |
|||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ |
|||
|
|||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
|
|||
/** @defgroup I2C_Exported_Constants I2C Exported Constants |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode |
|||
* @{ |
|||
*/ |
|||
#define I2C_DUTYCYCLE_2 0x00000000U |
|||
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_addressing_mode I2C addressing mode |
|||
* @{ |
|||
*/ |
|||
#define I2C_ADDRESSINGMODE_7BIT 0x00004000U |
|||
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode |
|||
* @{ |
|||
*/ |
|||
#define I2C_DUALADDRESS_DISABLE 0x00000000U |
|||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode |
|||
* @{ |
|||
*/ |
|||
#define I2C_GENERALCALL_DISABLE 0x00000000U |
|||
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_nostretch_mode I2C nostretch mode |
|||
* @{ |
|||
*/ |
|||
#define I2C_NOSTRETCH_DISABLE 0x00000000U |
|||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size |
|||
* @{ |
|||
*/ |
|||
#define I2C_MEMADD_SIZE_8BIT 0x00000001U |
|||
#define I2C_MEMADD_SIZE_16BIT 0x00000010U |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_XferDirection_definition I2C XferDirection definition |
|||
* @{ |
|||
*/ |
|||
#define I2C_DIRECTION_RECEIVE 0x00000000U |
|||
#define I2C_DIRECTION_TRANSMIT 0x00000001U |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_XferOptions_definition I2C XferOptions definition |
|||
* @{ |
|||
*/ |
|||
#define I2C_FIRST_FRAME 0x00000001U |
|||
#define I2C_FIRST_AND_NEXT_FRAME 0x00000002U |
|||
#define I2C_NEXT_FRAME 0x00000004U |
|||
#define I2C_FIRST_AND_LAST_FRAME 0x00000008U |
|||
#define I2C_LAST_FRAME_NO_STOP 0x00000010U |
|||
#define I2C_LAST_FRAME 0x00000020U |
|||
|
|||
/* List of XferOptions in usage of : |
|||
* 1- Restart condition in all use cases (direction change or not) |
|||
*/ |
|||
#define I2C_OTHER_FRAME (0x00AA0000U) |
|||
#define I2C_OTHER_AND_LAST_FRAME (0xAA000000U) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition |
|||
* @brief I2C Interrupt definition |
|||
* Elements values convention: 0xXXXXXXXX |
|||
* - XXXXXXXX : Interrupt control mask |
|||
* @{ |
|||
*/ |
|||
#define I2C_IT_BUF I2C_CR2_ITBUFEN |
|||
#define I2C_IT_EVT I2C_CR2_ITEVTEN |
|||
#define I2C_IT_ERR I2C_CR2_ITERREN |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @defgroup I2C_Flag_definition I2C Flag definition |
|||
* @{ |
|||
*/ |
|||
|
|||
#define I2C_FLAG_OVR 0x00010800U |
|||
#define I2C_FLAG_AF 0x00010400U |
|||
#define I2C_FLAG_ARLO 0x00010200U |
|||
#define I2C_FLAG_BERR 0x00010100U |
|||
#define I2C_FLAG_TXE 0x00010080U |
|||
#define I2C_FLAG_RXNE 0x00010040U |
|||
#define I2C_FLAG_STOPF 0x00010010U |
|||
#define I2C_FLAG_ADD10 0x00010008U |
|||
#define I2C_FLAG_BTF 0x00010004U |
|||
#define I2C_FLAG_ADDR 0x00010002U |
|||
#define I2C_FLAG_SB 0x00010001U |
|||
#define I2C_FLAG_DUALF 0x00100080U |
|||
#define I2C_FLAG_GENCALL 0x00100010U |
|||
#define I2C_FLAG_TRA 0x00100004U |
|||
#define I2C_FLAG_BUSY 0x00100002U |
|||
#define I2C_FLAG_MSL 0x00100001U |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macros -----------------------------------------------------------*/ |
|||
|
|||
/** @defgroup I2C_Exported_Macros I2C Exported Macros |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @brief Reset I2C handle state. |
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
|||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \ |
|||
(__HANDLE__)->MspInitCallback = NULL; \ |
|||
(__HANDLE__)->MspDeInitCallback = NULL; \ |
|||
} while(0) |
|||
#else |
|||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) |
|||
#endif |
|||
|
|||
/** @brief Enable or disable the specified I2C interrupts. |
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2C_IT_BUF: Buffer interrupt enable |
|||
* @arg I2C_IT_EVT: Event interrupt enable |
|||
* @arg I2C_IT_ERR: Error interrupt enable |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)) |
|||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) |
|||
|
|||
/** @brief Checks if the specified I2C interrupt source is enabled or disabled. |
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @param __INTERRUPT__ specifies the I2C interrupt source to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2C_IT_BUF: Buffer interrupt enable |
|||
* @arg I2C_IT_EVT: Event interrupt enable |
|||
* @arg I2C_IT_ERR: Error interrupt enable |
|||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
|||
|
|||
/** @brief Checks whether the specified I2C flag is set or not. |
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @param __FLAG__ specifies the flag to check. |
|||
* This parameter can be one of the following values: |
|||
* @arg I2C_FLAG_OVR: Overrun/Underrun flag |
|||
* @arg I2C_FLAG_AF: Acknowledge failure flag |
|||
* @arg I2C_FLAG_ARLO: Arbitration lost flag |
|||
* @arg I2C_FLAG_BERR: Bus error flag |
|||
* @arg I2C_FLAG_TXE: Data register empty flag |
|||
* @arg I2C_FLAG_RXNE: Data register not empty flag |
|||
* @arg I2C_FLAG_STOPF: Stop detection flag |
|||
* @arg I2C_FLAG_ADD10: 10-bit header sent flag |
|||
* @arg I2C_FLAG_BTF: Byte transfer finished flag |
|||
* @arg I2C_FLAG_ADDR: Address sent flag |
|||
* Address matched flag |
|||
* @arg I2C_FLAG_SB: Start bit flag |
|||
* @arg I2C_FLAG_DUALF: Dual flag |
|||
* @arg I2C_FLAG_GENCALL: General call header flag |
|||
* @arg I2C_FLAG_TRA: Transmitter/Receiver flag |
|||
* @arg I2C_FLAG_BUSY: Bus busy flag |
|||
* @arg I2C_FLAG_MSL: Master/Slave flag |
|||
* @retval The new state of __FLAG__ (TRUE or FALSE). |
|||
*/ |
|||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \ |
|||
(((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \ |
|||
(((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)) |
|||
|
|||
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. |
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @param __FLAG__ specifies the flag to clear. |
|||
* This parameter can be any combination of the following values: |
|||
* @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) |
|||
* @arg I2C_FLAG_AF: Acknowledge failure flag |
|||
* @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) |
|||
* @arg I2C_FLAG_BERR: Bus error flag |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) |
|||
|
|||
/** @brief Clears the I2C ADDR pending flag. |
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg = 0x00U; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR1; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR2; \ |
|||
UNUSED(tmpreg); \ |
|||
} while(0) |
|||
|
|||
/** @brief Clears the I2C STOPF pending flag. |
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ |
|||
do{ \ |
|||
__IO uint32_t tmpreg = 0x00U; \ |
|||
tmpreg = (__HANDLE__)->Instance->SR1; \ |
|||
SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE); \ |
|||
UNUSED(tmpreg); \ |
|||
} while(0) |
|||
|
|||
/** @brief Enable the specified I2C peripheral. |
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) |
|||
|
|||
/** @brief Disable the specified I2C peripheral. |
|||
* @param __HANDLE__ specifies the I2C Handle. |
|||
* @retval None |
|||
*/ |
|||
#define __HAL_I2C_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE) |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Include I2C HAL Extension module */ |
|||
#include "stm32f4xx_hal_i2c_ex.h" |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup I2C_Exported_Functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions |
|||
* @{ |
|||
*/ |
|||
/* Initialization and de-initialization functions******************************/ |
|||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); |
|||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); |
|||
|
|||
/* Callbacks Register/UnRegister functions ***********************************/ |
|||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); |
|||
|
|||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); |
|||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); |
|||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions |
|||
* @{ |
|||
*/ |
|||
/* IO operation functions ****************************************************/ |
|||
/******* Blocking mode: Polling */ |
|||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); |
|||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
|||
|
|||
/******* Non-Blocking mode: Interrupt */ |
|||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
|
|||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); |
|||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); |
|||
|
|||
/******* Non-Blocking mode: DMA */ |
|||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); |
|||
|
|||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
|||
* @{ |
|||
*/ |
|||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ |
|||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); |
|||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); |
|||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions |
|||
* @{ |
|||
*/ |
|||
/* Peripheral State, Mode and Error functions *********************************/ |
|||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); |
|||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); |
|||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup I2C_Private_Constants I2C Private Constants |
|||
* @{ |
|||
*/ |
|||
#define I2C_FLAG_MASK 0x0000FFFFU |
|||
#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */ |
|||
#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup I2C_Private_Macros I2C Private Macros |
|||
* @{ |
|||
*/ |
|||
|
|||
#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST)) |
|||
#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR) |
|||
#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) |
|||
#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) |
|||
#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U)) |
|||
#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9)) |
|||
#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ |
|||
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ |
|||
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) |
|||
|
|||
#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0))) |
|||
#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) |
|||
|
|||
#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) |
|||
#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) |
|||
#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) |
|||
|
|||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) |
|||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) |
|||
|
|||
/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters |
|||
* @{ |
|||
*/ |
|||
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ |
|||
((CYCLE) == I2C_DUTYCYCLE_16_9)) |
|||
#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ |
|||
((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) |
|||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ |
|||
((ADDRESS) == I2C_DUALADDRESS_ENABLE)) |
|||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ |
|||
((CALL) == I2C_GENERALCALL_ENABLE)) |
|||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ |
|||
((STRETCH) == I2C_NOSTRETCH_ENABLE)) |
|||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ |
|||
((SIZE) == I2C_MEMADD_SIZE_16BIT)) |
|||
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U)) |
|||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) |
|||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) |
|||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ |
|||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ |
|||
((REQUEST) == I2C_NEXT_FRAME) || \ |
|||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ |
|||
((REQUEST) == I2C_LAST_FRAME) || \ |
|||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ |
|||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) |
|||
|
|||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ |
|||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) |
|||
|
|||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) |
|||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Private functions ---------------------------------------------------------*/ |
|||
/** @defgroup I2C_Private_Functions I2C Private Functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
|
|||
#endif /* __STM32F4xx_HAL_I2C_H */ |
|||
|
|||
@ -1,115 +0,0 @@ |
|||
/** |
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_i2c_ex.h |
|||
* @author MCD Application Team |
|||
* @brief Header file of I2C HAL Extension module. |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
|
|||
/* Define to prevent recursive inclusion -------------------------------------*/ |
|||
#ifndef __STM32F4xx_HAL_I2C_EX_H |
|||
#define __STM32F4xx_HAL_I2C_EX_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
|
|||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) |
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal_def.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2CEx |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Exported types ------------------------------------------------------------*/ |
|||
/* Exported constants --------------------------------------------------------*/ |
|||
/** @defgroup I2CEx_Exported_Constants I2C Exported Constants |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup I2CEx_Analog_Filter I2C Analog Filter |
|||
* @{ |
|||
*/ |
|||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U |
|||
#define I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Exported macro ------------------------------------------------------------*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup I2CEx_Exported_Functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup I2CEx_Exported_Functions_Group1 |
|||
* @{ |
|||
*/ |
|||
/* Peripheral Control functions ************************************************/ |
|||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); |
|||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/** @defgroup I2CEx_Private_Constants I2C Private Constants |
|||
* @{ |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/* Private macros ------------------------------------------------------------*/ |
|||
/** @defgroup I2CEx_Private_Macros I2C Private Macros |
|||
* @{ |
|||
*/ |
|||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ |
|||
((FILTER) == I2C_ANALOGFILTER_DISABLE)) |
|||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
#endif |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif /* __STM32F4xx_HAL_I2C_EX_H */ |
|||
|
|||
|
|||
4779
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h
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1890
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h
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2110
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c
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1112
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c
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7524
Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c
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File diff suppressed because it is too large
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@ -1,182 +0,0 @@ |
|||
/** |
|||
****************************************************************************** |
|||
* @file stm32f4xx_hal_i2c_ex.c |
|||
* @author MCD Application Team |
|||
* @brief I2C Extension HAL module driver. |
|||
* This file provides firmware functions to manage the following |
|||
* functionalities of I2C extension peripheral: |
|||
* + Extension features functions |
|||
* |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2016 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
@verbatim |
|||
============================================================================== |
|||
##### I2C peripheral extension features ##### |
|||
============================================================================== |
|||
|
|||
[..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/ |
|||
429xx/439xx devices contains the following additional features : |
|||
|
|||
(+) Possibility to disable or enable Analog Noise Filter |
|||
(+) Use of a configured Digital Noise Filter |
|||
|
|||
##### How to use this driver ##### |
|||
============================================================================== |
|||
[..] This driver provides functions to configure Noise Filter |
|||
(#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config() |
|||
(#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() |
|||
|
|||
@endverbatim |
|||
*/ |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_hal.h" |
|||
|
|||
/** @addtogroup STM32F4xx_HAL_Driver |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @defgroup I2CEx I2CEx |
|||
* @brief I2C HAL module driver |
|||
* @{ |
|||
*/ |
|||
|
|||
#ifdef HAL_I2C_MODULE_ENABLED |
|||
|
|||
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) |
|||
/* Private typedef -----------------------------------------------------------*/ |
|||
/* Private define ------------------------------------------------------------*/ |
|||
/* Private macro -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private function prototypes -----------------------------------------------*/ |
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @defgroup I2CEx_Exported_Functions I2C Exported Functions |
|||
* @{ |
|||
*/ |
|||
|
|||
|
|||
/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions |
|||
* @brief Extension features functions |
|||
* |
|||
@verbatim |
|||
=============================================================================== |
|||
##### Extension features functions ##### |
|||
=============================================================================== |
|||
[..] This section provides functions allowing to: |
|||
(+) Configure Noise Filters |
|||
|
|||
@endverbatim |
|||
* @{ |
|||
*/ |
|||
|
|||
/** |
|||
* @brief Configures I2C Analog noise filter. |
|||
* @param hi2c pointer to a I2C_HandleTypeDef structure that contains |
|||
* the configuration information for the specified I2Cx peripheral. |
|||
* @param AnalogFilter new state of the Analog filter. |
|||
* @retval HAL status |
|||
*/ |
|||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) |
|||
{ |
|||
/* Check the parameters */ |
|||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
|||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); |
|||
|
|||
if (hi2c->State == HAL_I2C_STATE_READY) |
|||
{ |
|||
hi2c->State = HAL_I2C_STATE_BUSY; |
|||
|
|||
/* Disable the selected I2C peripheral */ |
|||
__HAL_I2C_DISABLE(hi2c); |
|||
|
|||
/* Reset I2Cx ANOFF bit */ |
|||
hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); |
|||
|
|||
/* Disable the analog filter */ |
|||
hi2c->Instance->FLTR |= AnalogFilter; |
|||
|
|||
__HAL_I2C_ENABLE(hi2c); |
|||
|
|||
hi2c->State = HAL_I2C_STATE_READY; |
|||
|
|||
return HAL_OK; |
|||
} |
|||
else |
|||
{ |
|||
return HAL_BUSY; |
|||
} |
|||
} |
|||
|
|||
/** |
|||
* @brief Configures I2C Digital noise filter. |
|||
* @param hi2c pointer to a I2C_HandleTypeDef structure that contains |
|||
* the configuration information for the specified I2Cx peripheral. |
|||
* @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. |
|||
* @retval HAL status |
|||
*/ |
|||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) |
|||
{ |
|||
uint16_t tmpreg = 0; |
|||
|
|||
/* Check the parameters */ |
|||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
|||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); |
|||
|
|||
if (hi2c->State == HAL_I2C_STATE_READY) |
|||
{ |
|||
hi2c->State = HAL_I2C_STATE_BUSY; |
|||
|
|||
/* Disable the selected I2C peripheral */ |
|||
__HAL_I2C_DISABLE(hi2c); |
|||
|
|||
/* Get the old register value */ |
|||
tmpreg = hi2c->Instance->FLTR; |
|||
|
|||
/* Reset I2Cx DNF bit [3:0] */ |
|||
tmpreg &= ~(I2C_FLTR_DNF); |
|||
|
|||
/* Set I2Cx DNF coefficient */ |
|||
tmpreg |= DigitalFilter; |
|||
|
|||
/* Store the new register value */ |
|||
hi2c->Instance->FLTR = tmpreg; |
|||
|
|||
__HAL_I2C_ENABLE(hi2c); |
|||
|
|||
hi2c->State = HAL_I2C_STATE_READY; |
|||
|
|||
return HAL_OK; |
|||
} |
|||
else |
|||
{ |
|||
return HAL_BUSY; |
|||
} |
|||
} |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
#endif |
|||
|
|||
#endif /* HAL_I2C_MODULE_ENABLED */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
@ -1,922 +0,0 @@ |
|||
/** |
|||
****************************************************************************** |
|||
* @file stm32f4xx_ll_adc.c |
|||
* @author MCD Application Team |
|||
* @brief ADC LL module driver |
|||
****************************************************************************** |
|||
* @attention |
|||
* |
|||
* Copyright (c) 2017 STMicroelectronics. |
|||
* All rights reserved. |
|||
* |
|||
* This software is licensed under terms that can be found in the LICENSE file |
|||
* in the root directory of this software component. |
|||
* If no LICENSE file comes with this software, it is provided AS-IS. |
|||
* |
|||
****************************************************************************** |
|||
*/ |
|||
#if defined(USE_FULL_LL_DRIVER) |
|||
|
|||
/* Includes ------------------------------------------------------------------*/ |
|||
#include "stm32f4xx_ll_adc.h" |
|||
#include "stm32f4xx_ll_bus.h" |
|||
|
|||
#ifdef USE_FULL_ASSERT |
|||
#include "stm32_assert.h" |
|||
#else |
|||
#define assert_param(expr) ((void)0U) |
|||
#endif |
|||
|
|||
/** @addtogroup STM32F4xx_LL_Driver |
|||
* @{ |
|||
*/ |
|||
|
|||
#if defined (ADC1) || defined (ADC2) || defined (ADC3) |
|||
|
|||
/** @addtogroup ADC_LL ADC |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Private types -------------------------------------------------------------*/ |
|||
/* Private variables ---------------------------------------------------------*/ |
|||
/* Private constants ---------------------------------------------------------*/ |
|||
/* Private macros ------------------------------------------------------------*/ |
|||
|
|||
/** @addtogroup ADC_LL_Private_Macros |
|||
* @{ |
|||
*/ |
|||
|
|||
/* Check of parameters for configuration of ADC hierarchical scope: */ |
|||
/* common to several ADC instances. */ |
|||
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ |
|||
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ |
|||
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ |
|||
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \ |
|||
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ |
|||
) |
|||
|
|||
/* Check of parameters for configuration of ADC hierarchical scope: */ |
|||
/* ADC instance. */ |
|||
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ |
|||
( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ |
|||
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ |
|||
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ |
|||
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
|||
( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
|||
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ |
|||
( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
|||
|| ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ |
|||
( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
|||
|| ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
|||
) |
|||
|
|||
/* Check of parameters for configuration of ADC hierarchical scope: */ |
|||
/* ADC group regular */ |
|||
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
|||
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ |
|||
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
|||
) |
|||
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
|||
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
|||
|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
|||
( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
|||
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ |
|||
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ |
|||
( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ |
|||
|| ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
|||
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
|||
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
|||
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
|||
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
|||
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
|||
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
|||
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
|||
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
|||
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
|||
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
|||
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
|||
) |
|||
|
|||
/* Check of parameters for configuration of ADC hierarchical scope: */ |
|||
/* ADC group injected */ |
|||
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
|||
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ |
|||
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ |
|||
( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ |
|||
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ |
|||
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
|||
( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
|||
|| ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
|||
( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
|||
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
|||
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
|||
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
|||
( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
|||
|| ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
|||
) |
|||
|
|||
#if defined(ADC_MULTIMODE_SUPPORT) |
|||
/* Check of parameters for configuration of ADC hierarchical scope: */ |
|||
/* multimode. */ |
|||
#if defined(ADC3) |
|||
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ |
|||
( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \ |
|||
) |
|||
#else |
|||
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ |
|||
( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ |
|||
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ |
|||
) |
|||
#endif |
|||
|
|||
#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ |
|||
( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ |
|||
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \ |
|||
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \ |
|||
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \ |
|||
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \ |
|||
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \ |
|||
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ |
|||
( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \ |
|||
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \ |
|||
) |
|||
|
|||
#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ |
|||
( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ |
|||
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ |
|||
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ |
|||
) |
|||
|
|||
#endif /* ADC_MULTIMODE_SUPPORT */ |
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
|
|||
/* Private function prototypes -----------------------------------------------*/ |
|||
|
|||
/* Exported functions --------------------------------------------------------*/ |
|||
/** @addtogroup ADC_LL_Exported_Functions |
|||
* @{ |
|||
*/ |
|||
|
|||
/** @addtogroup ADC_LL_EF_Init |
|||
* @{ |
|||
*/ |
|||
|
|||
/** |
|||
* @brief De-initialize registers of all ADC instances belonging to |
|||
* the same ADC common instance to their default reset values. |
|||
* @param ADCxy_COMMON ADC common instance |
|||
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
|||
* @retval An ErrorStatus enumeration value: |
|||
* - SUCCESS: ADC common registers are de-initialized |
|||
* - ERROR: not applicable |
|||
*/ |
|||
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
|||
{ |
|||
/* Check the parameters */ |
|||
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
|||
|
|||
|
|||
/* Force reset of ADC clock (core clock) */ |
|||
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); |
|||
|
|||
/* Release reset of ADC clock (core clock) */ |
|||
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); |
|||
|
|||
return SUCCESS; |
|||
} |
|||
|
|||
/** |
|||
* @brief Initialize some features of ADC common parameters |
|||
* (all ADC instances belonging to the same ADC common instance) |
|||
* and multimode (for devices with several ADC instances available). |
|||
* @note The setting of ADC common parameters is conditioned to |
|||
* ADC instances state: |
|||
* All ADC instances belonging to the same ADC common instance |
|||
* must be disabled. |
|||
* @param ADCxy_COMMON ADC common instance |
|||
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
|||
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
|||
* @retval An ErrorStatus enumeration value: |
|||
* - SUCCESS: ADC common registers are initialized |
|||
* - ERROR: ADC common registers are not initialized |
|||
*/ |
|||
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
|||
{ |
|||
ErrorStatus status = SUCCESS; |
|||
|
|||
/* Check the parameters */ |
|||
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
|||
assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); |
|||
|
|||
#if defined(ADC_MULTIMODE_SUPPORT) |
|||
assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); |
|||
if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) |
|||
{ |
|||
assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); |
|||
assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); |
|||
} |
|||
#endif /* ADC_MULTIMODE_SUPPORT */ |
|||
|
|||
/* Note: Hardware constraint (refer to description of functions */ |
|||
/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ |
|||
/* On this STM32 series, setting of these features is conditioned to */ |
|||
/* ADC state: */ |
|||
/* All ADC instances of the ADC common group must be disabled. */ |
|||
if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) |
|||
{ |
|||
/* Configuration of ADC hierarchical scope: */ |
|||
/* - common to several ADC */ |
|||
/* (all ADC instances belonging to the same ADC common instance) */ |
|||
/* - Set ADC clock (conversion clock) */ |
|||
/* - multimode (if several ADC instances available on the */ |
|||
/* selected device) */ |
|||
/* - Set ADC multimode configuration */ |
|||
/* - Set ADC multimode DMA transfer */ |
|||
/* - Set ADC multimode: delay between 2 sampling phases */ |
|||
#if defined(ADC_MULTIMODE_SUPPORT) |
|||
if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) |
|||
{ |
|||
MODIFY_REG(ADCxy_COMMON->CCR, |
|||
ADC_CCR_ADCPRE |
|||
| ADC_CCR_MULTI |
|||
| ADC_CCR_DMA |
|||
| ADC_CCR_DDS |
|||
| ADC_CCR_DELAY |
|||
, |
|||
ADC_CommonInitStruct->CommonClock |
|||
| ADC_CommonInitStruct->Multimode |
|||
| ADC_CommonInitStruct->MultiDMATransfer |
|||
| ADC_CommonInitStruct->MultiTwoSamplingDelay |
|||
); |
|||
} |
|||
else |
|||
{ |
|||
MODIFY_REG(ADCxy_COMMON->CCR, |
|||
ADC_CCR_ADCPRE |
|||
| ADC_CCR_MULTI |
|||
| ADC_CCR_DMA |
|||
| ADC_CCR_DDS |
|||
| ADC_CCR_DELAY |
|||
, |
|||
ADC_CommonInitStruct->CommonClock |
|||
| LL_ADC_MULTI_INDEPENDENT |
|||
); |
|||
} |
|||
#else |
|||
LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); |
|||
#endif |
|||
} |
|||
else |
|||
{ |
|||
/* Initialization error: One or several ADC instances belonging to */ |
|||
/* the same ADC common instance are not disabled. */ |
|||
status = ERROR; |
|||
} |
|||
|
|||
return status; |
|||
} |
|||
|
|||
/** |
|||
* @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
|||
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
|||
* whose fields will be set to default values. |
|||
* @retval None |
|||
*/ |
|||
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
|||
{ |
|||
/* Set ADC_CommonInitStruct fields to default values */ |
|||
/* Set fields of ADC common */ |
|||
/* (all ADC instances belonging to the same ADC common instance) */ |
|||
ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; |
|||
|
|||
#if defined(ADC_MULTIMODE_SUPPORT) |
|||
/* Set fields of ADC multimode */ |
|||
ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; |
|||
ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; |
|||
ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; |
|||
#endif /* ADC_MULTIMODE_SUPPORT */ |
|||
} |
|||
|
|||
/** |
|||
* @brief De-initialize registers of the selected ADC instance |
|||
* to their default reset values. |
|||
* @note To reset all ADC instances quickly (perform a hard reset), |
|||
* use function @ref LL_ADC_CommonDeInit(). |
|||
* @param ADCx ADC instance |
|||
* @retval An ErrorStatus enumeration value: |
|||
* - SUCCESS: ADC registers are de-initialized |
|||
* - ERROR: ADC registers are not de-initialized |
|||
*/ |
|||
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
|||
{ |
|||
ErrorStatus status = SUCCESS; |
|||
|
|||
/* Check the parameters */ |
|||
assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
|||
|
|||
/* Disable ADC instance if not already disabled. */ |
|||
if(LL_ADC_IsEnabled(ADCx) == 1UL) |
|||
{ |
|||
/* Set ADC group regular trigger source to SW start to ensure to not */ |
|||
/* have an external trigger event occurring during the conversion stop */ |
|||
/* ADC disable process. */ |
|||
LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
|||
|
|||
/* Set ADC group injected trigger source to SW start to ensure to not */ |
|||
/* have an external trigger event occurring during the conversion stop */ |
|||
/* ADC disable process. */ |
|||
LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
|||
|
|||
/* Disable the ADC instance */ |
|||
LL_ADC_Disable(ADCx); |
|||
} |
|||
|
|||
/* Check whether ADC state is compliant with expected state */ |
|||
/* (hardware requirements of bits state to reset registers below) */ |
|||
if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL) |
|||
{ |
|||
/* ========== Reset ADC registers ========== */ |
|||
/* Reset register SR */ |
|||
CLEAR_BIT(ADCx->SR, |
|||
( LL_ADC_FLAG_STRT |
|||
| LL_ADC_FLAG_JSTRT |
|||
| LL_ADC_FLAG_EOCS |
|||
| LL_ADC_FLAG_OVR |
|||
| LL_ADC_FLAG_JEOS |
|||
| LL_ADC_FLAG_AWD1 ) |
|||
); |
|||
|
|||
/* Reset register CR1 */ |
|||
CLEAR_BIT(ADCx->CR1, |
|||
( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN |
|||
| ADC_CR1_JAWDEN |
|||
| ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
|||
| ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
|||
| ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
|||
| ADC_CR1_AWDCH ) |
|||
); |
|||
|
|||
/* Reset register CR2 */ |
|||
CLEAR_BIT(ADCx->CR2, |
|||
( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
|||
| ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
|||
| ADC_CR2_ALIGN | ADC_CR2_EOCS |
|||
| ADC_CR2_DDS | ADC_CR2_DMA |
|||
| ADC_CR2_CONT | ADC_CR2_ADON ) |
|||
); |
|||
|
|||
/* Reset register SMPR1 */ |
|||
CLEAR_BIT(ADCx->SMPR1, |
|||
( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 |
|||
| ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 |
|||
| ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) |
|||
); |
|||
|
|||
/* Reset register SMPR2 */ |
|||
CLEAR_BIT(ADCx->SMPR2, |
|||
( ADC_SMPR2_SMP9 |
|||
| ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 |
|||
| ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 |
|||
| ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) |
|||
); |
|||
|
|||
/* Reset register JOFR1 */ |
|||
CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); |
|||
/* Reset register JOFR2 */ |
|||
CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); |
|||
/* Reset register JOFR3 */ |
|||
CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); |
|||
/* Reset register JOFR4 */ |
|||
CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); |
|||
|
|||
/* Reset register HTR */ |
|||
SET_BIT(ADCx->HTR, ADC_HTR_HT); |
|||
/* Reset register LTR */ |
|||
CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); |
|||
|
|||
/* Reset register SQR1 */ |
|||
CLEAR_BIT(ADCx->SQR1, |
|||
( ADC_SQR1_L |
|||
| ADC_SQR1_SQ16 |
|||
| ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) |
|||
); |
|||
|
|||
/* Reset register SQR2 */ |
|||
CLEAR_BIT(ADCx->SQR2, |
|||
( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
|||
| ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) |
|||
); |
|||
|
|||
/* Reset register SQR3 */ |
|||
CLEAR_BIT(ADCx->SQR3, |
|||
( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
|||
| ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) |
|||
); |
|||
|
|||
/* Reset register JSQR */ |
|||
CLEAR_BIT(ADCx->JSQR, |
|||
( ADC_JSQR_JL |
|||
| ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
|||
| ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
|||
); |
|||
|
|||
/* Reset register DR */ |
|||
/* bits in access mode read only, no direct reset applicable */ |
|||
|
|||
/* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
|||
/* bits in access mode read only, no direct reset applicable */ |
|||
|
|||
/* Reset register CCR */ |
|||
CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); |
|||
} |
|||
|
|||
return status; |
|||
} |
|||
|
|||
/** |
|||
* @brief Initialize some features of ADC instance. |
|||
* @note These parameters have an impact on ADC scope: ADC instance. |
|||
* Affects both group regular and group injected (availability |
|||
* of ADC group injected depends on STM32 families). |
|||
* Refer to corresponding unitary functions into |
|||
* @ref ADC_LL_EF_Configuration_ADC_Instance . |
|||
* @note The setting of these parameters by function @ref LL_ADC_Init() |
|||
* is conditioned to ADC state: |
|||
* ADC instance must be disabled. |
|||
* This condition is applied to all ADC features, for efficiency |
|||
* and compatibility over all STM32 families. However, the different |
|||
* features can be set under different ADC state conditions |
|||
* (setting possible with ADC enabled without conversion on going, |
|||
* ADC enabled with conversion on going, ...) |
|||
* Each feature can be updated afterwards with a unitary function |
|||
* and potentially with ADC in a different state than disabled, |
|||
* refer to description of each function for setting |
|||
* conditioned to ADC state. |
|||
* @note After using this function, some other features must be configured |
|||
* using LL unitary functions. |
|||
* The minimum configuration remaining to be done is: |
|||
* - Set ADC group regular or group injected sequencer: |
|||
* map channel on the selected sequencer rank. |
|||
* Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
|||
* - Set ADC channel sampling time |
|||
* Refer to function LL_ADC_SetChannelSamplingTime(); |
|||
* @param ADCx ADC instance |
|||
* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
|||
* @retval An ErrorStatus enumeration value: |
|||
* - SUCCESS: ADC registers are initialized |
|||
* - ERROR: ADC registers are not initialized |
|||
*/ |
|||
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
|||
{ |
|||
ErrorStatus status = SUCCESS; |
|||
|
|||
/* Check the parameters */ |
|||
assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
|||
|
|||
assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); |
|||
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
|||
assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); |
|||
|
|||
/* Note: Hardware constraint (refer to description of this function): */ |
|||
/* ADC instance must be disabled. */ |
|||
if(LL_ADC_IsEnabled(ADCx) == 0UL) |
|||
{ |
|||
/* Configuration of ADC hierarchical scope: */ |
|||
/* - ADC instance */ |
|||
/* - Set ADC data resolution */ |
|||
/* - Set ADC conversion data alignment */ |
|||
MODIFY_REG(ADCx->CR1, |
|||
ADC_CR1_RES |
|||
| ADC_CR1_SCAN |
|||
, |
|||
ADC_InitStruct->Resolution |
|||
| ADC_InitStruct->SequencersScanMode |
|||
); |
|||
|
|||
MODIFY_REG(ADCx->CR2, |
|||
ADC_CR2_ALIGN |
|||
, |
|||
ADC_InitStruct->DataAlignment |
|||
); |
|||
|
|||
} |
|||
else |
|||
{ |
|||
/* Initialization error: ADC instance is not disabled. */ |
|||
status = ERROR; |
|||
} |
|||
return status; |
|||
} |
|||
|
|||
/** |
|||
* @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
|||
* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
|||
* whose fields will be set to default values. |
|||
* @retval None |
|||
*/ |
|||
void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
|||
{ |
|||
/* Set ADC_InitStruct fields to default values */ |
|||
/* Set fields of ADC instance */ |
|||
ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; |
|||
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
|||
|
|||
/* Enable scan mode to have a generic behavior with ADC of other */ |
|||
/* STM32 families, without this setting available: */ |
|||
/* ADC group regular sequencer and ADC group injected sequencer depend */ |
|||
/* only of their own configuration. */ |
|||
ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; |
|||
|
|||
} |
|||
|
|||
/** |
|||
* @brief Initialize some features of ADC group regular. |
|||
* @note These parameters have an impact on ADC scope: ADC group regular. |
|||
* Refer to corresponding unitary functions into |
|||
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
|||
* (functions with prefix "REG"). |
|||
* @note The setting of these parameters by function @ref LL_ADC_Init() |
|||
* is conditioned to ADC state: |
|||
* ADC instance must be disabled. |
|||
* This condition is applied to all ADC features, for efficiency |
|||
* and compatibility over all STM32 families. However, the different |
|||
* features can be set under different ADC state conditions |
|||
* (setting possible with ADC enabled without conversion on going, |
|||
* ADC enabled with conversion on going, ...) |
|||
* Each feature can be updated afterwards with a unitary function |
|||
* and potentially with ADC in a different state than disabled, |
|||
* refer to description of each function for setting |
|||
* conditioned to ADC state. |
|||
* @note After using this function, other features must be configured |
|||
* using LL unitary functions. |
|||
* The minimum configuration remaining to be done is: |
|||
* - Set ADC group regular or group injected sequencer: |
|||
* map channel on the selected sequencer rank. |
|||
* Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
|||
* - Set ADC channel sampling time |
|||
* Refer to function LL_ADC_SetChannelSamplingTime(); |
|||
* @param ADCx ADC instance |
|||
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
|||
* @retval An ErrorStatus enumeration value: |
|||
* - SUCCESS: ADC registers are initialized |
|||
* - ERROR: ADC registers are not initialized |
|||
*/ |
|||
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
|||
{ |
|||
ErrorStatus status = SUCCESS; |
|||
|
|||
/* Check the parameters */ |
|||
assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
|||
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
|||
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
|||
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
|||
{ |
|||
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
|||
} |
|||
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
|||
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
|||
|
|||
/* ADC group regular continuous mode and discontinuous mode */ |
|||
/* can not be enabled simultenaeously */ |
|||
assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) |
|||
|| (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); |
|||
|
|||
/* Note: Hardware constraint (refer to description of this function): */ |
|||
/* ADC instance must be disabled. */ |
|||
if(LL_ADC_IsEnabled(ADCx) == 0UL) |
|||
{ |
|||
/* Configuration of ADC hierarchical scope: */ |
|||
/* - ADC group regular */ |
|||
/* - Set ADC group regular trigger source */ |
|||
/* - Set ADC group regular sequencer length */ |
|||
/* - Set ADC group regular sequencer discontinuous mode */ |
|||
/* - Set ADC group regular continuous mode */ |
|||
/* - Set ADC group regular conversion data transfer: no transfer or */ |
|||
/* transfer by DMA, and DMA requests mode */ |
|||
/* Note: On this STM32 series, ADC trigger edge is set when starting */ |
|||
/* ADC conversion. */ |
|||
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
|||
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
|||
{ |
|||
MODIFY_REG(ADCx->CR1, |
|||
ADC_CR1_DISCEN |
|||
| ADC_CR1_DISCNUM |
|||
, |
|||
ADC_REG_InitStruct->SequencerDiscont |
|||
); |
|||
} |
|||
else |
|||
{ |
|||
MODIFY_REG(ADCx->CR1, |
|||
ADC_CR1_DISCEN |
|||
| ADC_CR1_DISCNUM |
|||
, |
|||
LL_ADC_REG_SEQ_DISCONT_DISABLE |
|||
); |
|||
} |
|||
|
|||
MODIFY_REG(ADCx->CR2, |
|||
ADC_CR2_EXTSEL |
|||
| ADC_CR2_EXTEN |
|||
| ADC_CR2_CONT |
|||
| ADC_CR2_DMA |
|||
| ADC_CR2_DDS |
|||
, |
|||
(ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) |
|||
| ADC_REG_InitStruct->ContinuousMode |
|||
| ADC_REG_InitStruct->DMATransfer |
|||
); |
|||
|
|||
/* Set ADC group regular sequencer length and scan direction */ |
|||
/* Note: Hardware constraint (refer to description of this function): */ |
|||
/* Note: If ADC instance feature scan mode is disabled */ |
|||
/* (refer to ADC instance initialization structure */ |
|||
/* parameter @ref SequencersScanMode */ |
|||
/* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
|||
/* this parameter is discarded. */ |
|||
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
|||
} |
|||
else |
|||
{ |
|||
/* Initialization error: ADC instance is not disabled. */ |
|||
status = ERROR; |
|||
} |
|||
return status; |
|||
} |
|||
|
|||
/** |
|||
* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
|||
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
|||
* whose fields will be set to default values. |
|||
* @retval None |
|||
*/ |
|||
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
|||
{ |
|||
/* Set ADC_REG_InitStruct fields to default values */ |
|||
/* Set fields of ADC group regular */ |
|||
/* Note: On this STM32 series, ADC trigger edge is set when starting */ |
|||
/* ADC conversion. */ |
|||
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
|||
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
|||
ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
|||
ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
|||
ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
|||
ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
|||
} |
|||
|
|||
/** |
|||
* @brief Initialize some features of ADC group injected. |
|||
* @note These parameters have an impact on ADC scope: ADC group injected. |
|||
* Refer to corresponding unitary functions into |
|||
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
|||
* (functions with prefix "INJ"). |
|||
* @note The setting of these parameters by function @ref LL_ADC_Init() |
|||
* is conditioned to ADC state: |
|||
* ADC instance must be disabled. |
|||
* This condition is applied to all ADC features, for efficiency |
|||
* and compatibility over all STM32 families. However, the different |
|||
* features can be set under different ADC state conditions |
|||
* (setting possible with ADC enabled without conversion on going, |
|||
* ADC enabled with conversion on going, ...) |
|||
* Each feature can be updated afterwards with a unitary function |
|||
* and potentially with ADC in a different state than disabled, |
|||
* refer to description of each function for setting |
|||
* conditioned to ADC state. |
|||
* @note After using this function, other features must be configured |
|||
* using LL unitary functions. |
|||
* The minimum configuration remaining to be done is: |
|||
* - Set ADC group injected sequencer: |
|||
* map channel on the selected sequencer rank. |
|||
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
|||
* - Set ADC channel sampling time |
|||
* Refer to function LL_ADC_SetChannelSamplingTime(); |
|||
* @param ADCx ADC instance |
|||
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
|||
* @retval An ErrorStatus enumeration value: |
|||
* - SUCCESS: ADC registers are initialized |
|||
* - ERROR: ADC registers are not initialized |
|||
*/ |
|||
ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
|||
{ |
|||
ErrorStatus status = SUCCESS; |
|||
|
|||
/* Check the parameters */ |
|||
assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
|||
assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
|||
assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
|||
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
|||
{ |
|||
assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
|||
} |
|||
assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
|||
|
|||
/* Note: Hardware constraint (refer to description of this function): */ |
|||
/* ADC instance must be disabled. */ |
|||
if(LL_ADC_IsEnabled(ADCx) == 0UL) |
|||
{ |
|||
/* Configuration of ADC hierarchical scope: */ |
|||
/* - ADC group injected */ |
|||
/* - Set ADC group injected trigger source */ |
|||
/* - Set ADC group injected sequencer length */ |
|||
/* - Set ADC group injected sequencer discontinuous mode */ |
|||
/* - Set ADC group injected conversion trigger: independent or */ |
|||
/* from ADC group regular */ |
|||
/* Note: On this STM32 series, ADC trigger edge is set when starting */ |
|||
/* ADC conversion. */ |
|||
/* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
|||
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
|||
{ |
|||
MODIFY_REG(ADCx->CR1, |
|||
ADC_CR1_JDISCEN |
|||
| ADC_CR1_JAUTO |
|||
, |
|||
ADC_INJ_InitStruct->SequencerDiscont |
|||
| ADC_INJ_InitStruct->TrigAuto |
|||
); |
|||
} |
|||
else |
|||
{ |
|||
MODIFY_REG(ADCx->CR1, |
|||
ADC_CR1_JDISCEN |
|||
| ADC_CR1_JAUTO |
|||
, |
|||
LL_ADC_REG_SEQ_DISCONT_DISABLE |
|||
| ADC_INJ_InitStruct->TrigAuto |
|||
); |
|||
} |
|||
|
|||
MODIFY_REG(ADCx->CR2, |
|||
ADC_CR2_JEXTSEL |
|||
| ADC_CR2_JEXTEN |
|||
, |
|||
(ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) |
|||
); |
|||
|
|||
/* Note: Hardware constraint (refer to description of this function): */ |
|||
/* Note: If ADC instance feature scan mode is disabled */ |
|||
/* (refer to ADC instance initialization structure */ |
|||
/* parameter @ref SequencersScanMode */ |
|||
/* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
|||
/* this parameter is discarded. */ |
|||
LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); |
|||
} |
|||
else |
|||
{ |
|||
/* Initialization error: ADC instance is not disabled. */ |
|||
status = ERROR; |
|||
} |
|||
return status; |
|||
} |
|||
|
|||
/** |
|||
* @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
|||
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
|||
* whose fields will be set to default values. |
|||
* @retval None |
|||
*/ |
|||
void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
|||
{ |
|||
/* Set ADC_INJ_InitStruct fields to default values */ |
|||
/* Set fields of ADC group injected */ |
|||
ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
|||
ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
|||
ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
|||
ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
|||
} |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* ADC1 || ADC2 || ADC3 */ |
|||
|
|||
/** |
|||
* @} |
|||
*/ |
|||
|
|||
#endif /* USE_FULL_LL_DRIVER */ |
|||
|
|||
@ -0,0 +1,10 @@ |
|||
|
|||
``` |
|||
引脚分配: |
|||
|
|||
PB10/PB11 uart3 舵机 串口通信 |
|||
PD0 左限位 高有效 |
|||
PD1 右限位 高有效 |
|||
|
|||
|
|||
``` |
|||
@ -1,20 +1,41 @@ |
|||
#pragma once |
|||
#define TMC_MOTOR_SPI hspi1 |
|||
#define TMC_DIAG1 PB0 |
|||
#define TMC_DIAG0 PB1 |
|||
// #define TMC_DIAG1 PB0 |
|||
// #define TMC_DIAG0 PB1 |
|||
|
|||
#define ID0_IO PC0 |
|||
#define ID1_IO PC1 |
|||
#define ID2_IO PC2 |
|||
#define ID3_IO PC3 |
|||
#define ID4_IO PC4 |
|||
|
|||
#define SENSOR_INT0 PD0 |
|||
#define SENSOR_INT1 PD1 |
|||
#define SENSOR_INT2 PD2 |
|||
#define SENSOR_INT3 PD3 |
|||
#define SENSOR_INT4 PD4 |
|||
#define SENSOR_INT5 PD5 |
|||
#define SENSOR_INT6 PD6 |
|||
#define SENSOR_INT7 PD7 |
|||
#define SENSOR_INT8 PD8 |
|||
#define SENSOR_INT9 PD9 |
|||
|
|||
|
|||
// MOTOR0 |
|||
#define MOTOR0_CSN PA4 |
|||
#define MOTOR0_ENN PE3 |
|||
#define MOTOR0_SPI_MODE_SELECT PinNull |
|||
#define MOTOR0_REFL PD13 |
|||
#define MOTOR0_REFR PD14 |
|||
#define MOTOR0_ENN PB7 |
|||
#define MOTOR0_SPI_MODE_SELECT PB4 |
|||
#define MOTOR0_REFL SENSOR_INT0 |
|||
#define MOTOR0_REFR SENSOR_INT1 |
|||
|
|||
|
|||
|
|||
|
|||
// MOTOR1 |
|||
#define MOTOR1_CSN PA8 |
|||
#define MOTOR1_ENN PE6 |
|||
#define MOTOR1_SPI_MODE_SELECT PinNull |
|||
#define MOTOR1_REFL PD11 |
|||
#define MOTOR1_REFR PD12 |
|||
// #define MOTOR1_CSN PA8 |
|||
// #define MOTOR1_ENN PE6 |
|||
// #define MOTOR1_SPI_MODE_SELECT PinNull |
|||
// #define MOTOR1_REFL PD11 |
|||
// #define MOTOR1_REFR PD12 |
|||
|
|||
#define MOTOR_CFG_FLASH_MARK "MOTOR_CFG_FLASH_MARK" |
|||
// #define MOTOR_CFG_FLASH_MARK "MOTOR_CFG_FLASH_MARK" |
|||
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