16 changed files with 517 additions and 30 deletions
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2.gitignore
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BINoutput_file_1.jic
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11output_file_1.map
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59run_led.eda.rpt
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2run_led.jdi
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10run_led.pin
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BINrun_led.pof
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10run_led.qsf
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BINrun_led.sof
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60run_led.sta.summary
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142source/light_ctrl_pluse_generator.v
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44source/shutter_pulse_generator.v
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92source/top_module.v
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49source/zutils_edge_detecter.v
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49source/zutils_pluse_width_detecter.v
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17source/zutils_reset_sig_gen.v
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BLOCK START ADDRESS END ADDRESS |
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Page_0 0x00000000 0x00059D8A |
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Notes: |
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- Data checksum for this conversion is 0x1A5E0C9C |
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- All the addresses in this file are byte addresses |
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@ -0,0 +1,59 @@ |
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EDA Netlist Writer report for run_led |
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Wed Feb 21 21:37:07 2024 |
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Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version |
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|
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|
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--------------------- |
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; Table of Contents ; |
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--------------------- |
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1. Legal Notice |
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2. EDA Netlist Writer Summary |
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3. EDA Netlist Writer Messages |
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|
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|
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|
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---------------- |
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; Legal Notice ; |
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---------------- |
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Copyright (C) 1991-2013 Altera Corporation |
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Your use of Altera Corporation's design tools, logic functions |
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and other software and tools, and its AMPP partner logic |
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functions, and any output files from any of the foregoing |
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(including device programming or simulation files), and any |
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associated documentation or information are expressly subject |
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to the terms and conditions of the Altera Program License |
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Subscription Agreement, Altera MegaCore Function License |
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Agreement, or other applicable license agreement, including, |
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without limitation, that your use is for the sole purpose of |
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programming logic devices manufactured by Altera and sold by |
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Altera or its authorized distributors. Please refer to the |
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applicable agreement for further details. |
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|
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|
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|
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+----------------------------------------------------------------------------------+ |
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; EDA Netlist Writer Summary ; |
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+---------------------------+------------------------------------------------------+ |
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; EDA Netlist Writer Status ; No Output Files Generated - Wed Feb 21 21:37:07 2024 ; |
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; Revision Name ; run_led ; |
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; Top-level Entity Name ; top_module ; |
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; Family ; Cyclone IV E ; |
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+---------------------------+------------------------------------------------------+ |
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|
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|
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+-----------------------------+ |
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; EDA Netlist Writer Messages ; |
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+-----------------------------+ |
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Info: ******************************************************************* |
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Info: Running Quartus II 64-Bit EDA Netlist Writer |
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Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version |
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Info: Processing started: Wed Feb 21 21:37:06 2024 |
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Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off run_led -c run_led |
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Warning (199027): Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script. |
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Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 1 warning |
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Info: Peak virtual memory: 4556 megabytes |
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Info: Processing ended: Wed Feb 21 21:37:07 2024 |
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Info: Elapsed time: 00:00:01 |
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Info: Total CPU time (on all processors): 00:00:00 |
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|
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@ -0,0 +1,142 @@ |
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module light_ctrl_pluse_generator ( |
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input clk, |
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input rst_n, |
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|
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input wire [31:0] pluse_width, |
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input wire [31:0] pluse_interval, |
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|
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// 触发输入引脚 |
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input trigger, //触发输入 |
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|
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output reg output_1, //指示灯通断控制输出 |
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output reg output_2, //指示灯通断控制输出 |
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output reg output_3, //指示灯通断控制输出 |
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output reg output_4 //指示灯通断控制输出 |
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|
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); |
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|
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wire trigger_r_edge; |
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wire trigger_f_edge; |
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|
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zutils_edge_detecter tigger_signal_in ( |
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.clk(clk), |
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.rst_n(rst_n), |
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.in_signal(trigger), |
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.in_signal_rising_edge(trigger_r_edge), |
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.in_signal_falling_edge(trigger_f_edge) |
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); |
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|
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reg [31:0] state; |
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reg [31:0] pluse_width_cache; |
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reg [31:0] pluse_interval_cache; |
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reg [31:0] cnt; |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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state <= 0; |
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output_1 <= 0; |
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output_2 <= 0; |
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output_3 <= 0; |
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output_4 <= 0; |
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end else begin |
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case (state) |
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0: begin |
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if (trigger_r_edge) begin |
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|
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if (pluse_width <= 250) begin // 100ns |
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pluse_width_cache <= 250; // 100ns |
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end else begin |
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pluse_width_cache <= pluse_width; // |
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end |
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|
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if (pluse_interval <= 5) begin // 100ns |
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pluse_interval_cache <= 5; // 100ns |
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end else begin |
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pluse_interval_cache <= pluse_interval; // |
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end |
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|
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state <= 1; |
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output_1 <= 1; |
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cnt <= 0; |
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end |
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end |
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1: begin |
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if (cnt >= pluse_width_cache) begin |
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output_1 <= 0; |
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state <= 2; |
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cnt <= 0; |
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end else begin |
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cnt <= cnt + 1; |
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end |
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end |
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2: begin |
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if (cnt >= pluse_interval_cache) begin |
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output_2 <= 1; |
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state <= 3; |
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cnt <= 0; |
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end else begin |
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cnt <= cnt + 1; |
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end |
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end |
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|
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3: begin |
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if (cnt >= pluse_width_cache) begin |
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output_2 <= 0; |
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state <= 4; |
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cnt <= 0; |
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end else begin |
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cnt <= cnt + 1; |
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end |
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end |
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|
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4: begin |
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if (cnt >= pluse_interval_cache) begin |
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output_3 <= 1; |
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state <= 5; |
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cnt <= 0; |
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end else begin |
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cnt <= cnt + 1; |
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end |
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end |
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|
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5: begin |
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if (cnt >= pluse_width_cache) begin |
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output_3 <= 0; |
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state <= 6; |
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cnt <= 0; |
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end else begin |
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cnt <= cnt + 1; |
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end |
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end |
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|
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6: begin |
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if (cnt >= pluse_interval_cache) begin |
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output_4 <= 1; |
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state <= 7; |
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cnt <= 0; |
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end else begin |
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cnt <= cnt + 1; |
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end |
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end |
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|
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7: begin |
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if (cnt >= pluse_width_cache) begin |
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output_4 <= 0; |
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state <= 0; |
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cnt <= 0; |
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end else begin |
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cnt <= cnt + 1; |
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end |
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end |
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|
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default: begin |
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state <= 0; |
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end |
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|
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endcase |
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end |
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end |
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|
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endmodule |
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@ -0,0 +1,44 @@ |
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|
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module shutter_pulse_generator ( |
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input clk, |
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input rst_n, |
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|
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input wire [31:0] pluse_width, |
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// 触发输入引脚 |
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input trigger, //触发输入 |
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output wire output_sig //指示灯通断控制输出 |
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); |
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|
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reg [31:0] cnt; |
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reg output_sig_0; |
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reg [31:0] pluse_width_cache; |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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cnt <= 0; |
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output_sig_0 <= 0; |
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end else begin |
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if (trigger) begin |
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if (cnt == 0) begin |
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cnt <= cnt + 1; |
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pluse_width_cache <= pluse_width; |
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output_sig_0 <= 0; |
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end else begin |
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if (cnt <= pluse_width_cache) begin |
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cnt <= cnt + 1; |
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output_sig_0 <= 0; |
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end else begin |
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cnt <= cnt; |
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output_sig_0 <= 1; |
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end |
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end |
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end else begin |
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cnt <= 0; |
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output_sig_0 <= 0; |
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end |
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end |
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end |
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assign output_sig = output_sig_0 & trigger; |
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endmodule |
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@ -0,0 +1,49 @@ |
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module zutils_edge_detecter ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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input wire in_signal, |
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output reg in_signal_last, |
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output reg in_signal_rising_edge, |
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output reg in_signal_falling_edge, |
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output reg in_signal_edge |
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); |
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|
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// initial begin |
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// in_signal_last = 0; |
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// in_signal_rising_edge = 0; |
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// in_signal_falling_edge = 0; |
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// in_signal_edge = 0; |
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// end |
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|
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|
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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in_signal_last <= 0; |
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end else begin |
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in_signal_last <= in_signal; |
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end |
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end |
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|
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always @(posedge clk or negedge rst_n) begin |
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if (!rst_n) begin |
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in_signal_rising_edge <= 0; |
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in_signal_falling_edge <= 0; |
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in_signal_edge <= 0; |
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end else begin |
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if (in_signal_last == 0 && in_signal == 1) begin |
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in_signal_rising_edge <= 1; |
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in_signal_falling_edge <= 0; |
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in_signal_edge <= 1; |
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end else if (in_signal_last == 1 && in_signal == 0) begin |
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in_signal_rising_edge <= 0; |
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in_signal_falling_edge <= 1; |
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in_signal_edge <= 1; |
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end else begin |
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in_signal_rising_edge <= 0; |
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in_signal_falling_edge <= 0; |
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in_signal_edge <= 0; |
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end |
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end |
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end |
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endmodule |
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@ -0,0 +1,49 @@ |
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module zutils_pluse_width_detecter ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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input wire in_signal, |
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output reg [31:0] in_signal_pluse_width |
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); |
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|
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wire rising_edge; |
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wire falling_edge; |
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|
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zutils_edge_detecter _signal_in ( |
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.clk(CLK), |
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.rst_n(RSTn), |
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.in_signal(in_signal), |
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.in_signal_rising_edge(rising_edge), |
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.in_signal_falling_edge(falling_edge) |
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); |
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|
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reg [31:0] pluse_width_cnt; |
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reg state; |
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|
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always @(posedge CLK or negedge RSTn) begin |
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if (!RSTn) begin |
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in_signal_pluse_width <= 1; |
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pluse_width_cnt <= 1; |
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state <= 0; |
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end else begin |
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|
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if (!state) begin |
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if (rising_edge) begin |
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pluse_width_cnt <= 0; |
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state <= 1; |
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end |
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end else begin |
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pluse_width_cnt <= pluse_width_cnt + 1; |
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if (falling_edge) begin |
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in_signal_pluse_width <= pluse_width_cnt; |
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state <= 0; |
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end |
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end |
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|
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end |
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end |
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|
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|
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|
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|
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|
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endmodule |
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@ -0,0 +1,17 @@ |
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module zutils_reset_sig_gen ( |
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input clk, //clock input |
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output reg rst_n_out |
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); |
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|
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reg [31:0] counter = 0; |
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always @(posedge clk) begin |
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if (counter < 31'd1000000) begin |
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rst_n_out <= 0; |
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counter <= counter + 1; |
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end else begin |
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counter <= counter; |
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rst_n_out <= 1; |
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end |
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end |
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|
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endmodule |
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