diff --git a/.gitignore b/.gitignore index a0b2d4f..977419a 100644 --- a/.gitignore +++ b/.gitignore @@ -8,3 +8,5 @@ run_led.fit.summary run_led.flow.rpt run_led.map.summary run_led.sta.rpt +output_file.jic +output_file.map diff --git a/output_file_1.jic b/output_file_1.jic new file mode 100644 index 0000000..1dbe9b5 Binary files /dev/null and b/output_file_1.jic differ diff --git a/output_file_1.map b/output_file_1.map new file mode 100644 index 0000000..9afc258 --- /dev/null +++ b/output_file_1.map @@ -0,0 +1,11 @@ +BLOCK START ADDRESS END ADDRESS + +Page_0 0x00000000 0x00059D8A + + + +Notes: + +- Data checksum for this conversion is 0x1A5E0C9C + +- All the addresses in this file are byte addresses \ No newline at end of file diff --git a/run_led.eda.rpt b/run_led.eda.rpt new file mode 100644 index 0000000..d46d25b --- /dev/null +++ b/run_led.eda.rpt @@ -0,0 +1,59 @@ +EDA Netlist Writer report for run_led +Wed Feb 21 21:37:07 2024 +Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+------------------------------------------------------+ +; EDA Netlist Writer Status ; No Output Files Generated - Wed Feb 21 21:37:07 2024 ; +; Revision Name ; run_led ; +; Top-level Entity Name ; top_module ; +; Family ; Cyclone IV E ; ++---------------------------+------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit EDA Netlist Writer + Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version + Info: Processing started: Wed Feb 21 21:37:06 2024 +Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off run_led -c run_led +Warning (199027): Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script. +Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4556 megabytes + Info: Processing ended: Wed Feb 21 21:37:07 2024 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/run_led.jdi b/run_led.jdi index 7ccc0ab..14cab09 100644 --- a/run_led.jdi +++ b/run_led.jdi @@ -1,6 +1,6 @@ - + diff --git a/run_led.pin b/run_led.pin index 6f049a7..f072b58 100644 --- a/run_led.pin +++ b/run_led.pin @@ -100,7 +100,7 @@ VCCINT : 29 : power : : 1.2V RESERVED_INPUT : 30 : : : : 2 : RESERVED_INPUT : 31 : : : : 2 : RESERVED_INPUT : 32 : : : : 2 : -debug_light[0] : 33 : output : 3.3-V LVTTL : : 2 : Y +camera_shutter_out : 33 : output : 3.3-V LVTTL : : 2 : Y RESERVED_INPUT : 34 : : : : 2 : VCCA1 : 35 : power : : 2.5V : : GNDA1 : 36 : gnd : : : : @@ -120,7 +120,7 @@ RESERVED_INPUT : 49 : : : lt_on_off_ctrl_1 : 50 : output : 3.3-V LVTTL : : 3 : Y lt_on_off_ctrl_2 : 51 : output : 3.3-V LVTTL : : 3 : Y RESERVED_INPUT : 52 : : : : 3 : -RESERVED_INPUT : 53 : : : : 3 : +tp5 : 53 : output : 3.3-V LVTTL : : 3 : N RESERVED_INPUT : 54 : : : : 4 : RESERVED_INPUT : 55 : : : : 4 : VCCIO4 : 56 : power : : 3.3V : 4 : @@ -177,7 +177,7 @@ stm32_pc6 : 106 : input : 3.3-V LVTTL : VCCA2 : 107 : power : : 2.5V : : GNDA2 : 108 : gnd : : : : VCCD_PLL2 : 109 : power : : 1.2V : : -camera_shutter_out : 110 : output : 3.3-V LVTTL : : 7 : N +debug_light[0] : 110 : output : 3.3-V LVTTL : : 7 : Y RESERVED_INPUT : 111 : : : : 7 : RESERVED_INPUT : 112 : : : : 7 : RESERVED_INPUT : 113 : : : : 7 : @@ -193,7 +193,7 @@ VCCIO7 : 122 : power : : 3.3V GND : 123 : gnd : : : : RESERVED_INPUT : 124 : : : : 7 : RESERVED_INPUT : 125 : : : : 7 : -tp5 : 126 : output : 3.3-V LVTTL : : 7 : N +RESERVED_INPUT : 126 : : : : 7 : RESERVED_INPUT : 127 : : : : 7 : RESERVED_INPUT : 128 : : : : 8 : RESERVED_INPUT : 129 : : : : 8 : @@ -211,5 +211,5 @@ GND : 140 : gnd : : stm32_pa3 : 141 : input : 3.3-V LVTTL : : 8 : Y stm32_pa2 : 142 : input : 3.3-V LVTTL : : 8 : Y stm32_pa1 : 143 : input : 3.3-V LVTTL : : 8 : Y -stm32_pa0 : 144 : output : 3.3-V LVTTL : : 8 : Y +stm32_pa0 : 144 : input : 3.3-V LVTTL : : 8 : Y GND : EPAD : : : : : diff --git a/run_led.pof b/run_led.pof index 2bf8f9f..67ef784 100644 Binary files a/run_led.pof and b/run_led.pof differ diff --git a/run_led.qsf b/run_led.qsf index 0b04ac7..5dd00d3 100644 --- a/run_led.qsf +++ b/run_led.qsf @@ -58,14 +58,13 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF -set_global_assignment -name VERILOG_FILE source/top_module.v set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_location_assignment PIN_7 -to debug_light[2] set_location_assignment PIN_10 -to debug_light[1] -set_location_assignment PIN_33 -to debug_light[0] +set_location_assignment PIN_110 -to debug_light[0] set_location_assignment PIN_23 -to clk set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 set_location_assignment PIN_58 -to lt_intensity_1 @@ -90,4 +89,11 @@ set_location_assignment PIN_28 -to trigger_input0 set_location_assignment PIN_135 -to tp6 set_location_assignment PIN_136 -to tp7 set_location_assignment PIN_137 -to tp8 +set_location_assignment PIN_33 -to camera_shutter_out +set_global_assignment -name VERILOG_FILE source/shutter_pulse_generator.v +set_global_assignment -name VERILOG_FILE source/zutils_reset_sig_gen.v +set_global_assignment -name VERILOG_FILE source/zutils_pluse_width_detecter.v +set_global_assignment -name VERILOG_FILE source/zutils_edge_detecter.v +set_global_assignment -name VERILOG_FILE source/light_ctrl_pluse_generator.v +set_global_assignment -name VERILOG_FILE source/top_module.v set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/run_led.sof b/run_led.sof index 0eddfef..9c35700 100644 Binary files a/run_led.sof and b/run_led.sof differ diff --git a/run_led.sta.summary b/run_led.sta.summary index 33f7436..43ae4b1 100644 --- a/run_led.sta.summary +++ b/run_led.sta.summary @@ -2,4 +2,64 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ +Type : Slow 1200mV 85C Model Setup 'clk' +Slack : -4.581 +TNS : -421.206 + +Type : Slow 1200mV 85C Model Hold 'clk' +Slack : 0.433 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Recovery 'clk' +Slack : -1.252 +TNS : -31.619 + +Type : Slow 1200mV 85C Model Removal 'clk' +Slack : 0.694 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk' +Slack : -3.000 +TNS : -169.544 + +Type : Slow 1200mV 0C Model Setup 'clk' +Slack : -4.240 +TNS : -386.456 + +Type : Slow 1200mV 0C Model Hold 'clk' +Slack : 0.382 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Recovery 'clk' +Slack : -1.111 +TNS : -26.036 + +Type : Slow 1200mV 0C Model Removal 'clk' +Slack : 0.625 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk' +Slack : -3.000 +TNS : -169.544 + +Type : Fast 1200mV 0C Model Setup 'clk' +Slack : -1.267 +TNS : -110.384 + +Type : Fast 1200mV 0C Model Hold 'clk' +Slack : 0.179 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Recovery 'clk' +Slack : -0.045 +TNS : -0.090 + +Type : Fast 1200mV 0C Model Removal 'clk' +Slack : 0.305 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk' +Slack : -3.000 +TNS : -151.106 + ------------------------------------------------------------ diff --git a/source/light_ctrl_pluse_generator.v b/source/light_ctrl_pluse_generator.v new file mode 100644 index 0000000..c473b05 --- /dev/null +++ b/source/light_ctrl_pluse_generator.v @@ -0,0 +1,142 @@ + +module light_ctrl_pluse_generator ( + input clk, + input rst_n, + + input wire [31:0] pluse_width, + input wire [31:0] pluse_interval, + + // 触发输入引脚 + input trigger, //触发输入 + + output reg output_1, //指示灯通断控制输出 + output reg output_2, //指示灯通断控制输出 + output reg output_3, //指示灯通断控制输出 + output reg output_4 //指示灯通断控制输出 + +); + + wire trigger_r_edge; + wire trigger_f_edge; + + zutils_edge_detecter tigger_signal_in ( + .clk(clk), + .rst_n(rst_n), + .in_signal(trigger), + .in_signal_rising_edge(trigger_r_edge), + .in_signal_falling_edge(trigger_f_edge) + ); + + reg [31:0] state; + reg [31:0] pluse_width_cache; + reg [31:0] pluse_interval_cache; + reg [31:0] cnt; + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + state <= 0; + output_1 <= 0; + output_2 <= 0; + output_3 <= 0; + output_4 <= 0; + end else begin + case (state) + 0: begin + if (trigger_r_edge) begin + + if (pluse_width <= 250) begin // 100ns + pluse_width_cache <= 250; // 100ns + end else begin + pluse_width_cache <= pluse_width; // + end + + if (pluse_interval <= 5) begin // 100ns + pluse_interval_cache <= 5; // 100ns + end else begin + pluse_interval_cache <= pluse_interval; // + end + + state <= 1; + output_1 <= 1; + cnt <= 0; + end + end + 1: begin + if (cnt >= pluse_width_cache) begin + output_1 <= 0; + state <= 2; + cnt <= 0; + end else begin + cnt <= cnt + 1; + end + end + 2: begin + if (cnt >= pluse_interval_cache) begin + output_2 <= 1; + state <= 3; + cnt <= 0; + end else begin + cnt <= cnt + 1; + end + end + + 3: begin + if (cnt >= pluse_width_cache) begin + output_2 <= 0; + state <= 4; + cnt <= 0; + end else begin + cnt <= cnt + 1; + end + end + + 4: begin + if (cnt >= pluse_interval_cache) begin + output_3 <= 1; + state <= 5; + cnt <= 0; + end else begin + cnt <= cnt + 1; + end + end + + 5: begin + if (cnt >= pluse_width_cache) begin + output_3 <= 0; + state <= 6; + cnt <= 0; + end else begin + cnt <= cnt + 1; + end + end + + 6: begin + if (cnt >= pluse_interval_cache) begin + output_4 <= 1; + state <= 7; + cnt <= 0; + end else begin + cnt <= cnt + 1; + end + end + + 7: begin + if (cnt >= pluse_width_cache) begin + output_4 <= 0; + state <= 0; + cnt <= 0; + end else begin + cnt <= cnt + 1; + end + end + + default: begin + state <= 0; + end + + endcase + end + end + + +endmodule diff --git a/source/shutter_pulse_generator.v b/source/shutter_pulse_generator.v new file mode 100644 index 0000000..a041db3 --- /dev/null +++ b/source/shutter_pulse_generator.v @@ -0,0 +1,44 @@ + +module shutter_pulse_generator ( + input clk, + input rst_n, + + input wire [31:0] pluse_width, + // 触发输入引脚 + input trigger, //触发输入 + output wire output_sig //指示灯通断控制输出 +); + + reg [31:0] cnt; + reg output_sig_0; + reg [31:0] pluse_width_cache; + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + cnt <= 0; + output_sig_0 <= 0; + end else begin + if (trigger) begin + if (cnt == 0) begin + cnt <= cnt + 1; + pluse_width_cache <= pluse_width; + output_sig_0 <= 0; + end else begin + if (cnt <= pluse_width_cache) begin + cnt <= cnt + 1; + output_sig_0 <= 0; + end else begin + cnt <= cnt; + output_sig_0 <= 1; + end + end + end else begin + cnt <= 0; + output_sig_0 <= 0; + end + end + end + + assign output_sig = output_sig_0 & trigger; + +endmodule diff --git a/source/top_module.v b/source/top_module.v index b7a4b65..2cf1dcc 100644 --- a/source/top_module.v +++ b/source/top_module.v @@ -8,14 +8,13 @@ module top_module ( input stm32_pc8, // 灯光强度控制PWM input stm32_pc9, // 灯光强度控制PWM - input stm32_pa1, // 快门控制 - input stm32_pa2, // 快门控制 - input stm32_pa3, // 快门控制 - input stm32_pa4, // 快门控制 - input stm32_pa5, // 快门控制 + input stm32_pa0, + input stm32_pa1, + input stm32_pa2, + input stm32_pa3, + input stm32_pa4, + input stm32_pa5, - //output_to_stm32 - output stm32_pa0, // 输入捕获 //光强控制引脚 output lt_intensity_1, //灯光强度控制输出 @@ -31,11 +30,9 @@ module top_module ( output camera_shutter_out, //相机快门控制输出 - // 触发输入引脚 input trigger_input0, //触发输入 - //测试引脚 // output spi2_miso, //用于测试的SPI输出 @@ -47,23 +44,74 @@ module top_module ( output [2:0] debug_light ); + + /******************************************************************************* + * 复位信号生成器 * + *******************************************************************************/ + wire rst_n; + zutils_reset_sig_gen reset_sig_gen0 ( + .clk(clk), + .rst_n_out(rst_n) + ); + + + + + wire [31:0] pluse_width; // 脉冲宽度 + wire [31:0] pluse_interval; //脉冲间隙 + wire [31:0] pluse_shutter_delay; //快门延迟 + + + zutils_pluse_width_detecter pluse_width_detecter0 ( + .clk(clk), + .rst_n(rst_n), + .in_signal(stm32_pa0), + .in_signal_pluse_width(pluse_width) + ); + + zutils_pluse_width_detecter pluse_width_detecter1 ( + .clk(clk), + .rst_n(rst_n), + .in_signal(stm32_pa1), + .in_signal_pluse_width(pluse_interval) + ); + + zutils_pluse_width_detecter pluse_width_detecter2 ( + .clk(clk), + .rst_n(rst_n), + .in_signal(stm32_pa2), + .in_signal_pluse_width(pluse_shutter_delay) + ); + + + light_ctrl_pluse_generator light_ctrl_pluse_generator0 ( + .clk(clk), + .rst_n(rst_n), + .trigger(trigger_input0), + .pluse_width(pluse_width), + .pluse_interval(pluse_interval), + .output_1(lt_on_off_ctrl_1), + .output_2(lt_on_off_ctrl_2), + .output_3(lt_on_off_ctrl_3), + .output_4(lt_on_off_ctrl_4) + ); + + + wire shutter_ctrl_0; + shutter_pulse_generator shutter_pulse_generator0 ( + .clk(clk), + .rst_n(rst_n), + .pluse_width(pluse_shutter_delay), + .trigger(lt_on_off_ctrl_1 | lt_on_off_ctrl_2 | lt_on_off_ctrl_3 | lt_on_off_ctrl_4), + .output_sig(shutter_ctrl_0) + ); + + + assign camera_shutter_out = shutter_ctrl_0; assign lt_intensity_1 = stm32_pc6; assign lt_intensity_2 = stm32_pc7; assign lt_intensity_3 = stm32_pc8; assign lt_intensity_4 = stm32_pc9; - assign lt_on_off_ctrl_1 = stm32_pa1; - assign lt_on_off_ctrl_2 = stm32_pa2; - assign lt_on_off_ctrl_3 = stm32_pa3; - assign lt_on_off_ctrl_4 = stm32_pa4; - assign camera_shutter_out = stm32_pa5; - - assign stm32_pa0 = !trigger_input0; - - assign debug_light[0] = 1; - assign debug_light[1] = 0; - assign debug_light[2] = 0; - - assign tp8 = !trigger_input0; endmodule diff --git a/source/zutils_edge_detecter.v b/source/zutils_edge_detecter.v new file mode 100644 index 0000000..91040bd --- /dev/null +++ b/source/zutils_edge_detecter.v @@ -0,0 +1,49 @@ +module zutils_edge_detecter ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + input wire in_signal, + output reg in_signal_last, + output reg in_signal_rising_edge, + output reg in_signal_falling_edge, + output reg in_signal_edge +); + + // initial begin + // in_signal_last = 0; + // in_signal_rising_edge = 0; + // in_signal_falling_edge = 0; + // in_signal_edge = 0; + // end + + + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + in_signal_last <= 0; + end else begin + in_signal_last <= in_signal; + end + end + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + in_signal_rising_edge <= 0; + in_signal_falling_edge <= 0; + in_signal_edge <= 0; + end else begin + if (in_signal_last == 0 && in_signal == 1) begin + in_signal_rising_edge <= 1; + in_signal_falling_edge <= 0; + in_signal_edge <= 1; + end else if (in_signal_last == 1 && in_signal == 0) begin + in_signal_rising_edge <= 0; + in_signal_falling_edge <= 1; + in_signal_edge <= 1; + end else begin + in_signal_rising_edge <= 0; + in_signal_falling_edge <= 0; + in_signal_edge <= 0; + end + end + end +endmodule diff --git a/source/zutils_pluse_width_detecter.v b/source/zutils_pluse_width_detecter.v new file mode 100644 index 0000000..d7c449a --- /dev/null +++ b/source/zutils_pluse_width_detecter.v @@ -0,0 +1,49 @@ +module zutils_pluse_width_detecter ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + input wire in_signal, + output reg [31:0] in_signal_pluse_width +); + + wire rising_edge; + wire falling_edge; + + zutils_edge_detecter _signal_in ( + .clk(CLK), + .rst_n(RSTn), + .in_signal(in_signal), + .in_signal_rising_edge(rising_edge), + .in_signal_falling_edge(falling_edge) + ); + + reg [31:0] pluse_width_cnt; + reg state; + + always @(posedge CLK or negedge RSTn) begin + if (!RSTn) begin + in_signal_pluse_width <= 1; + pluse_width_cnt <= 1; + state <= 0; + end else begin + + if (!state) begin + if (rising_edge) begin + pluse_width_cnt <= 0; + state <= 1; + end + end else begin + pluse_width_cnt <= pluse_width_cnt + 1; + if (falling_edge) begin + in_signal_pluse_width <= pluse_width_cnt; + state <= 0; + end + end + + end + end + + + + + +endmodule diff --git a/source/zutils_reset_sig_gen.v b/source/zutils_reset_sig_gen.v new file mode 100644 index 0000000..1b50957 --- /dev/null +++ b/source/zutils_reset_sig_gen.v @@ -0,0 +1,17 @@ +module zutils_reset_sig_gen ( + input clk, //clock input + output reg rst_n_out +); + + reg [31:0] counter = 0; + always @(posedge clk) begin + if (counter < 31'd1000000) begin + rst_n_out <= 0; + counter <= counter + 1; + end else begin + counter <= counter; + rst_n_out <= 1; + end + end + +endmodule