diff --git a/iflytop_xsync_protocol.h b/iflytop_xsync_protocol.h
index e076f05..cff50d1 100644
--- a/iflytop_xsync_protocol.h
+++ b/iflytop_xsync_protocol.h
@@ -152,60 +152,11 @@ typedef enum {
   kxsync_reg_stm32_netmask                          = XYSNC_REG_STM32_CONFIG_START_ADD + 3,
   kxsync_reg_stm32_config0                          = XYSNC_REG_STM32_CONFIG_START_ADD + 4,  // bit0: timecode report enable, bit1: camera sync report enable
   kxsync_reg_stm32_camera_sync_signal_count         = XYSNC_REG_STM32_CONFIG_START_ADD + 5,  // 写任意数值之后清零
-  kxsync_reg_stm32_camera_sync_signal_report_period = XYSNC_REG_STM32_CONFIG_START_ADD + 6,  // 多少帧上报一次
+  // kxsync_reg_stm32_camera_sync_signal_report_period = XYSNC_REG_STM32_CONFIG_START_ADD + 6,  // 多少帧上报一次
 
   kxsync_reg_stm32_action0     = XYSNC_REG_STM32_CONFIG_START_ADD + 14,  // action reg
   kxsync_reg_stm32_action_val0 = XYSNC_REG_STM32_CONFIG_START_ADD + 15,  // action val reg
 
-  /**
-   * @brief
-   *  REG 48(32)  FPGA配置寄存器0
-   */
-  kxsync_fpga_reg_test_reg0 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 0,
-  kxsync_fpga_reg_test_reg1 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 1,
-  kxsync_fpga_reg_test_reg2 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 2,
-  kxsync_fpga_reg_test_reg3 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 3,
-  kxsync_fpga_reg_test_reg4 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 4,
-  kxsync_fpga_reg_test_reg5 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 5,
-  kxsync_fpga_reg_test_reg6 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 6,
-  kxsync_fpga_reg_test_reg7 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 7,
-  kxsync_fpga_reg_test_reg8 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 8,
-  kxsync_fpga_reg_test_reg9 = XYSNC_REG_FPGA_REG_START + 16 * 0 + 9,
-  kxsync_fpga_reg_test_rega = XYSNC_REG_FPGA_REG_START + 16 * 0 + 10,
-  kxsync_fpga_reg_test_regb = XYSNC_REG_FPGA_REG_START + 16 * 0 + 11,
-  kxsync_fpga_reg_test_regc = XYSNC_REG_FPGA_REG_START + 16 * 0 + 12,
-  kxsync_fpga_reg_test_regd = XYSNC_REG_FPGA_REG_START + 16 * 0 + 13,
-  kxsync_fpga_reg_test_rege = XYSNC_REG_FPGA_REG_START + 16 * 0 + 14,
-  kxsync_fpga_reg_test_regf = XYSNC_REG_FPGA_REG_START + 16 * 0 + 15,
-
-  /**
-   * @brief TTL输出模块
-   */
-
-  kxsync_reg_ttlout1_input_sig_slt       = REG_ADD_OFF_TTLOUT1 + 0,
-  kxsync_reg_ttlout1_output_sig_slt      = REG_ADD_OFF_TTLOUT1 + 1,
-  kxsync_reg_ttlout1_config              = REG_ADD_OFF_TTLOUT1 + 2,
-  kxsync_reg_ttlout1_pulse_mode_duration = REG_ADD_OFF_TTLOUT1 + 3,
-  kxsync_reg_ttlout1_pulse_mode_delay    = REG_ADD_OFF_TTLOUT1 + 4,
-
-  kxsync_reg_ttlout2_input_sig_slt       = REG_ADD_OFF_TTLOUT2 + 0,
-  kxsync_reg_ttlout2_output_sig_slt      = REG_ADD_OFF_TTLOUT2 + 1,
-  kxsync_reg_ttlout2_config              = REG_ADD_OFF_TTLOUT2 + 2,
-  kxsync_reg_ttlout2_pulse_mode_duration = REG_ADD_OFF_TTLOUT2 + 3,
-  kxsync_reg_ttlout2_pulse_mode_delay    = REG_ADD_OFF_TTLOUT2 + 4,
-
-  kxsync_reg_ttlout3_input_sig_slt       = REG_ADD_OFF_TTLOUT3 + 0,
-  kxsync_reg_ttlout3_output_sig_slt      = REG_ADD_OFF_TTLOUT3 + 1,
-  kxsync_reg_ttlout3_config              = REG_ADD_OFF_TTLOUT3 + 2,
-  kxsync_reg_ttlout3_pulse_mode_duration = REG_ADD_OFF_TTLOUT3 + 3,
-  kxsync_reg_ttlout3_pulse_mode_delay    = REG_ADD_OFF_TTLOUT3 + 4,
-
-  kxsync_reg_ttlout4_input_sig_slt       = REG_ADD_OFF_TTLOUT4 + 0,
-  kxsync_reg_ttlout4_output_sig_slt      = REG_ADD_OFF_TTLOUT4 + 1,
-  kxsync_reg_ttlout4_config              = REG_ADD_OFF_TTLOUT4 + 2,
-  kxsync_reg_ttlout4_pulse_mode_duration = REG_ADD_OFF_TTLOUT4 + 3,
-  kxsync_reg_ttlout4_pulse_mode_delay    = REG_ADD_OFF_TTLOUT4 + 4,
-
 } xsync_reg_add_t;
 
 #define KXSYNC_REG_STM32_CONFIG0_MASK_TIMECODE_REPORT_ENABLE    0x01