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#pragma once
#include <fstream>
#include <functional>
#include <iostream>
#include <list>
#include <map>
#include <memory>
#include <set>
#include <sstream>
#include <string>
#include <vector>
namespace xsync {namespace reg {using namespace std;
#define REG_ADD_OFF_STM32 (0x0000)
#define REG_ADD_OFF_STM32_CONFIG_START_ADD (0x0010)
#define REG_ADD_OFF_FPGA_TEST (0x00020)
// 控制中心寄存器地址
#define REG_ADD_OFF_SIG_GENERATOR (0x00030)
// 输入组件
#define REG_ADD_OFF_TTLIN1 (0x0100)
#define REG_ADD_OFF_TIMECODE_IN (0x0140)
#define REG_ADD_OFF_GENLOCK_IN (0x0150)
// 输出组件
#define REG_ADD_OFF_TTLOUT1 (0x0200)
#define REG_ADD_OFF_TTLOUT2 (0x0210)
#define REG_ADD_OFF_TTLOUT3 (0x0220)
#define REG_ADD_OFF_TTLOUT4 (0x0230)
#define REG_ADD_OFF_TIMECODE_OUT (0x0240)
#define REG_ADD_OFF_GENLOCK_OUT (0x0250)
#define REG_ADD_OFF_CAMERA_SYNC_OUT (0x0260)
// 调试组件
#define REG_ADD_OFF_DEBUGER (0x0300)
typedef enum { /**
* @brief * REG 0(16) 设备信息基础寄存器 */ ksoftware_version = 0, kmanufacturer0 = 1, kmanufacturer1 = 2, kproduct_type_id = 3, ksn_id0 = 4, ksn_id1 = 5, ksn_id2 = 6, kmac0 = 7, kmac1 = 8,
/**
* @brief * REG 16(32) STM32配置寄存器0 */ kstm32_obtaining_ip_mode = REG_ADD_OFF_STM32_CONFIG_START_ADD + 0, kstm32_ip = REG_ADD_OFF_STM32_CONFIG_START_ADD + 1, kstm32_gw = REG_ADD_OFF_STM32_CONFIG_START_ADD + 2, kstm32_netmask = REG_ADD_OFF_STM32_CONFIG_START_ADD + 3, kstm32_config0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 4, // bit0: timecode report enable, bit1: camera sync report enable
kstm32_camera_sync_signal_count = REG_ADD_OFF_STM32_CONFIG_START_ADD + 5, // 写任意数值之后清零
kstm32_camera_sync_signal_count_report_period = REG_ADD_OFF_STM32_CONFIG_START_ADD + 6, // 上报周期，单位为帧数
kstm32_action0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 14, // action reg
kstm32_action_val0 = REG_ADD_OFF_STM32_CONFIG_START_ADD + 15, // action val reg
/**
* @brief * REG 48(32) FPGA配置寄存器0 */ kfpga_test_reg0 = REG_ADD_OFF_FPGA_TEST + 0, kfpga_test_reg1 = REG_ADD_OFF_FPGA_TEST + 1, kfpga_test_reg2 = REG_ADD_OFF_FPGA_TEST + 2, kfpga_test_reg3 = REG_ADD_OFF_FPGA_TEST + 3, kfpga_test_reg4 = REG_ADD_OFF_FPGA_TEST + 4, kfpga_test_reg5 = REG_ADD_OFF_FPGA_TEST + 5, kfpga_test_reg6 = REG_ADD_OFF_FPGA_TEST + 6, kfpga_test_reg7 = REG_ADD_OFF_FPGA_TEST + 7, kfpga_test_reg8 = REG_ADD_OFF_FPGA_TEST + 8, kfpga_test_reg9 = REG_ADD_OFF_FPGA_TEST + 9, kfpga_test_rega = REG_ADD_OFF_FPGA_TEST + 10, kfpga_test_regb = REG_ADD_OFF_FPGA_TEST + 11, kfpga_test_regc = REG_ADD_OFF_FPGA_TEST + 12, kfpga_test_regd = REG_ADD_OFF_FPGA_TEST + 13, kfpga_test_rege = REG_ADD_OFF_FPGA_TEST + 14, kfpga_test_regf = REG_ADD_OFF_FPGA_TEST + 15,
/**
* @brief 信号发生器模块 */ kSigGenerator_ctl = REG_ADD_OFF_SIG_GENERATOR + 0, // 控制模式选择寄存器
kSigGenerator_genlock_format = REG_ADD_OFF_SIG_GENERATOR + 2, // genlock格式寄存器
kSigGenerator_timecode_format = REG_ADD_OFF_SIG_GENERATOR + 3, // timecode格式寄存器
kSigGenerator_control_trigger_reg = REG_ADD_OFF_SIG_GENERATOR + 4, // StartSigCtrl[0]
kSigGenerator_timecode0 = REG_ADD_OFF_SIG_GENERATOR + 6, // timecode0
kSigGenerator_timecode1 = REG_ADD_OFF_SIG_GENERATOR + 7, // timecode1
kSigGenerator_timecode_start0 = REG_ADD_OFF_SIG_GENERATOR + 8, // 时码启动寄存器0
kSigGenerator_timecode_start1 = REG_ADD_OFF_SIG_GENERATOR + 9, // 时码启动寄存器1
kSigGenerator_work_state = REG_ADD_OFF_SIG_GENERATOR + 12, // 工作状态 read only
/**
* @brief TTL输出模块 */ kttlout1_input_sig_slt = REG_ADD_OFF_TTLOUT1 + 0, kttlout1_output_sig_slt = REG_ADD_OFF_TTLOUT1 + 1, kttlout1_config = REG_ADD_OFF_TTLOUT1 + 2, kttlout1_pulse_mode_duration = REG_ADD_OFF_TTLOUT1 + 3, kttlout1_pulse_mode_delay = REG_ADD_OFF_TTLOUT1 + 4,
kttlout2_input_sig_slt = REG_ADD_OFF_TTLOUT2 + 0, kttlout2_output_sig_slt = REG_ADD_OFF_TTLOUT2 + 1, kttlout2_config = REG_ADD_OFF_TTLOUT2 + 2, kttlout2_pulse_mode_duration = REG_ADD_OFF_TTLOUT2 + 3, kttlout2_pulse_mode_delay = REG_ADD_OFF_TTLOUT2 + 4,
kttlout3_input_sig_slt = REG_ADD_OFF_TTLOUT3 + 0, kttlout3_output_sig_slt = REG_ADD_OFF_TTLOUT3 + 1, kttlout3_config = REG_ADD_OFF_TTLOUT3 + 2, kttlout3_pulse_mode_duration = REG_ADD_OFF_TTLOUT3 + 3, kttlout3_pulse_mode_delay = REG_ADD_OFF_TTLOUT3 + 4,
kttlout4_input_sig_slt = REG_ADD_OFF_TTLOUT4 + 0, kttlout4_output_sig_slt = REG_ADD_OFF_TTLOUT4 + 1, kttlout4_config = REG_ADD_OFF_TTLOUT4 + 2, kttlout4_pulse_mode_duration = REG_ADD_OFF_TTLOUT4 + 3, kttlout4_pulse_mode_delay = REG_ADD_OFF_TTLOUT4 + 4,
/**
* @brief 时码输出控制模块 * REG_ADD_OFF_TIMECODE_OUT */
ktimecode_out_timecode_select = REG_ADD_OFF_TIMECODE_OUT + 0, ktimecode_out_timecode0 = REG_ADD_OFF_TIMECODE_OUT + 1, ktimecode_out_timecode1 = REG_ADD_OFF_TIMECODE_OUT + 2, ktimecode_out_timecode_format = REG_ADD_OFF_TIMECODE_OUT + 3, ktimecode_out_bnc_outut_level_select = REG_ADD_OFF_TIMECODE_OUT + 4, ktimecode_out_headphone_outut_level_select = REG_ADD_OFF_TIMECODE_OUT + 5,
kcamera_sync_out_camera_sync_select = REG_ADD_OFF_CAMERA_SYNC_OUT + 0,
/*******************************************************************************
* 时码输入模块 * *******************************************************************************/
ktimecode_in_timecode_sig_selt = REG_ADD_OFF_TIMECODE_IN + 0, ktimecode_in_timecode_format = REG_ADD_OFF_TIMECODE_IN + 1, ktimecode_in_timecode0 = REG_ADD_OFF_TIMECODE_IN + 2, ktimecode_in_timecode1 = REG_ADD_OFF_TIMECODE_IN + 3,
/*******************************************************************************
* TTL输入模块 * *******************************************************************************/
kttlin_en = REG_ADD_OFF_TTLIN1 + 0, kttlin1_devide_factor = REG_ADD_OFF_TTLIN1 + 1, kttlin2_devide_factor = REG_ADD_OFF_TTLIN1 + 2, kttlin3_devide_factor = REG_ADD_OFF_TTLIN1 + 3, kttlin4_devide_factor = REG_ADD_OFF_TTLIN1 + 4, kttlin1_filter_factor = REG_ADD_OFF_TTLIN1 + 5, kttlin2_filter_factor = REG_ADD_OFF_TTLIN1 + 6, kttlin3_filter_factor = REG_ADD_OFF_TTLIN1 + 7, kttlin4_filter_factor = REG_ADD_OFF_TTLIN1 + 8,
} RegAdd_t;
} // namespace reg
} // namespace xsync
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