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update ttlin module logic

master
zhaohe 1 year ago
parent
852470380e
commit
9315e9914a
4 changed files with 70 additions and 109 deletions
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  1. 97
      xsync.cpp
  2. 20
      xsync.hpp
  3. 2
      xsync_packet.hpp
  4. 60
      xsync_regs.hpp

97
xsync.cpp
View File

@ -1139,84 +1139,39 @@ xs_error_code_t Xsync::TimecodeInputModule_getTimecode(XsyncTimecode_t &timecode
return ecode;
}
xs_error_code_t Xsync::TTLInputModule_setEn(int32_t index, bool en) {
uint32_t readbak = 0;
DO_XSYNC(reg_read(reg::kttlin_en, readbak, 10));
if (en) {
readbak |= (1 << index);
} else {
readbak &= ~(1 << index);
}
DO_XSYNC(reg_write(reg::kttlin_en, readbak, readbak, 10));
return kxs_ec_success;
}
xs_error_code_t Xsync::TTLInputModule_getEn(int32_t index, bool &en) {
uint32_t readbak = 0;
DO_XSYNC(reg_read(reg::kttlin_en, readbak, 10));
en = (readbak & (1 << index)) != 0;
return kxs_ec_success;
}
#define FREQ_CNT_TO_FREQ(cnt) ((cnt != 0) ? (uint32_t)(1.0 / (cnt * 1.0 / (10 * 1000 * 1000)) + 0.5) : 0 ) //+0.5是因为c++ 小数强转成整数时是取整，而非四舍五入
xs_error_code_t Xsync::TTLInputModule_setFilterFactor(int32_t index, uint32_t factor) {
uint32_t readbak = 0;
if (index == 1) {
DO_XSYNC(reg_write(reg::kttlin1_filter_factor, factor, readbak, 10));
} else if (index == 2) {
DO_XSYNC(reg_write(reg::kttlin2_filter_factor, factor, readbak, 10));
} else if (index == 3) {
DO_XSYNC(reg_write(reg::kttlin3_filter_factor, factor, readbak, 10));
} else if (index == 4) {
DO_XSYNC(reg_write(reg::kttlin4_filter_factor, factor, readbak, 10));
} else {
return kxs_ec_param_error;
/**
* @brief 读取TTL输入模块的频率
*
* @param index
* @param freq
* @return xs_error_code_t
*/
xs_error_code_t Xsync::TTLInputModule1_detectFreq(uint32_t &freq) {
uint32_t freq_cnt = 0;
DO_XSYNC(reg_read(reg::k_ttlin1_freq_detector_reg, freq_cnt, 10));
if (freq_cnt == 0) {
freq = 0;
}
freq = FREQ_CNT_TO_FREQ(freq_cnt);
return kxs_ec_success;
}
xs_error_code_t Xsync::TTLInputModule_getFilterFactor(int32_t index, uint32_t &factor) {
uint32_t readbak = 0;
if (index == 1) {
DO_XSYNC(reg_read(reg::kttlin1_filter_factor, readbak, 10));
} else if (index == 2) {
DO_XSYNC(reg_read(reg::kttlin2_filter_factor, readbak, 10));
} else if (index == 3) {
DO_XSYNC(reg_read(reg::kttlin3_filter_factor, readbak, 10));
} else if (index == 4) {
DO_XSYNC(reg_read(reg::kttlin4_filter_factor, readbak, 10));
} else {
return kxs_ec_param_error;
}
factor = readbak;
xs_error_code_t Xsync::TTLInputModule2_detectFreq(uint32_t &freq) {
uint32_t freq_cnt = 0;
DO_XSYNC(reg_read(reg::k_ttlin2_freq_detector_reg, freq_cnt, 10));
freq = FREQ_CNT_TO_FREQ(freq_cnt);
return kxs_ec_success;
}
xs_error_code_t Xsync::TTLInputModule_setDivideFactor(int32_t index, uint32_t factor) {
uint32_t readbak = 0;
if (index == 1) {
DO_XSYNC(reg_write(reg::kttlin1_devide_factor, factor, readbak, 10));
} else if (index == 2) {
DO_XSYNC(reg_write(reg::kttlin2_devide_factor, factor, readbak, 10));
} else if (index == 3) {
DO_XSYNC(reg_write(reg::kttlin3_devide_factor, factor, readbak, 10));
} else if (index == 4) {
DO_XSYNC(reg_write(reg::kttlin4_devide_factor, factor, readbak, 10));
} else {
return kxs_ec_param_error;
}
xs_error_code_t Xsync::TTLInputModule3_detectFreq(uint32_t &freq) {
uint32_t freq_cnt = 0;
DO_XSYNC(reg_read(reg::k_ttlin3_freq_detector_reg, freq_cnt, 10));
freq = FREQ_CNT_TO_FREQ(freq_cnt);
return kxs_ec_success;
}
xs_error_code_t Xsync::TTLInputModule_getDivideFactor(int32_t index, uint32_t &factor) {
uint32_t readbak = 0;
if (index == 1) {
DO_XSYNC(reg_read(reg::kttlin1_devide_factor, readbak, 10));
} else if (index == 2) {
DO_XSYNC(reg_read(reg::kttlin2_devide_factor, readbak, 10));
} else if (index == 3) {
DO_XSYNC(reg_read(reg::kttlin3_devide_factor, readbak, 10));
} else if (index == 4) {
DO_XSYNC(reg_read(reg::kttlin4_devide_factor, readbak, 10));
} else {
return kxs_ec_param_error;
}
factor = readbak;
xs_error_code_t Xsync::TTLInputModule4_detectFreq(uint32_t &freq) {
uint32_t freq_cnt = 0;
DO_XSYNC(reg_read(reg::k_ttlin4_freq_detector_reg, freq_cnt, 10));
freq = FREQ_CNT_TO_FREQ(freq_cnt);
return kxs_ec_success;
}

20
xsync.hpp
View File

@ -282,15 +282,17 @@ class Xsync {
* TTL输入模块 *
*******************************************************************************/
xs_error_code_t TTLInputModule_setEn(int32_t index, bool en);
xs_error_code_t TTLInputModule_getEn(int32_t index, bool &en);
xs_error_code_t TTLInputModule_setFilterFactor(int32_t index, uint32_t factor);
xs_error_code_t TTLInputModule_getFilterFactor(int32_t index, uint32_t &factor);
xs_error_code_t TTLInputModule_setDivideFactor(int32_t index, uint32_t factor);
xs_error_code_t TTLInputModule_getDivideFactor(int32_t index, uint32_t &factor);
/**
* @brief 读取TTL输入模块的频率
*
* @param index
* @param freq
* @return xs_error_code_t
*/
xs_error_code_t TTLInputModule1_detectFreq(uint32_t &freq);
xs_error_code_t TTLInputModule2_detectFreq(uint32_t &freq);
xs_error_code_t TTLInputModule3_detectFreq(uint32_t &freq);
xs_error_code_t TTLInputModule4_detectFreq(uint32_t &freq);
/*******************************************************************************
* 信号生成器模块 *
*******************************************************************************/

2
xsync_packet.hpp
View File

@ -31,6 +31,7 @@ typedef struct {
uint32_t eventid;
uint32_t data[];
} iflytop_xsync_event_report_packet_t;
#pragma pack()
typedef enum {
ktimecode_report_event = 0,
@ -66,4 +67,5 @@ typedef enum {
} xsync_stm32_action_t;
typedef enum { obtaining_ip_mode_type_static = 0, obtaining_ip_mode_type_dhcp = 1 } obtaining_ip_mode_t;
} // namespace xsync

60
xsync_regs.hpp
View File

@ -15,11 +15,11 @@ using namespace std;
#define REG_ADD_OFF_STM32 (0x0000)
#define REG_ADD_OFF_STM32_CONFIG_START_ADD (0x0010)
#define REG_ADD_OFF_FPGA_TEST (0x00020)
#define REGADDOFF__FPGA_INFO (0x00020)
// 控制中心寄存器地址
#define REG_ADD_OFF_SIG_GENERATOR (0x00030)
// 输入组件
#define REG_ADD_OFF_TTLIN1 (0x0100)
#define REGADDOFF__TTLIN (0x0100)
#define REG_ADD_OFF_TIMECODE_IN (0x0140)
#define REG_ADD_OFF_GENLOCK_IN (0x0150)
// 输出组件
@ -66,22 +66,22 @@ typedef enum {
* @brief
* REG 48(32) FPGA配置寄存器0
*/
kfpga_test_reg0 = REG_ADD_OFF_FPGA_TEST + 0,
kfpga_test_reg1 = REG_ADD_OFF_FPGA_TEST + 1,
kfpga_test_reg2 = REG_ADD_OFF_FPGA_TEST + 2,
kfpga_test_reg3 = REG_ADD_OFF_FPGA_TEST + 3,
kfpga_test_reg4 = REG_ADD_OFF_FPGA_TEST + 4,
kfpga_test_reg5 = REG_ADD_OFF_FPGA_TEST + 5,
kfpga_test_reg6 = REG_ADD_OFF_FPGA_TEST + 6,
kfpga_test_reg7 = REG_ADD_OFF_FPGA_TEST + 7,
kfpga_test_reg8 = REG_ADD_OFF_FPGA_TEST + 8,
kfpga_test_reg9 = REG_ADD_OFF_FPGA_TEST + 9,
kfpga_test_rega = REG_ADD_OFF_FPGA_TEST + 10,
kfpga_test_regb = REG_ADD_OFF_FPGA_TEST + 11,
kfpga_test_regc = REG_ADD_OFF_FPGA_TEST + 12,
kfpga_test_regd = REG_ADD_OFF_FPGA_TEST + 13,
kfpga_test_rege = REG_ADD_OFF_FPGA_TEST + 14,
kfpga_test_regf = REG_ADD_OFF_FPGA_TEST + 15,
kfpga_info_reg0 = REGADDOFF__FPGA_INFO + 0,
kfpga_info_reg1 = REGADDOFF__FPGA_INFO + 1,
kfpga_info_reg2 = REGADDOFF__FPGA_INFO + 2,
kfpga_info_reg3 = REGADDOFF__FPGA_INFO + 3,
kfpga_info_reg4 = REGADDOFF__FPGA_INFO + 4,
kfpga_info_reg5 = REGADDOFF__FPGA_INFO + 5,
kfpga_info_reg6 = REGADDOFF__FPGA_INFO + 6,
kfpga_info_reg7 = REGADDOFF__FPGA_INFO + 7,
kfpga_info_reg8 = REGADDOFF__FPGA_INFO + 8,
kfpga_info_reg9 = REGADDOFF__FPGA_INFO + 9,
kfpga_info_rega = REGADDOFF__FPGA_INFO + 10,
kfpga_info_regb = REGADDOFF__FPGA_INFO + 11,
kfpga_info_regc = REGADDOFF__FPGA_INFO + 12,
kfpga_info_regd = REGADDOFF__FPGA_INFO + 13,
kfpga_info_rege = REGADDOFF__FPGA_INFO + 14,
kfpga_info_regf = REGADDOFF__FPGA_INFO + 15,
/**
* @brief 信号发生器模块
@ -150,17 +150,19 @@ typedef enum {
* TTL输入模块 *
*******************************************************************************/
kttlin_en = REG_ADD_OFF_TTLIN1 + 0,
kttlin1_devide_factor = REG_ADD_OFF_TTLIN1 + 1,
kttlin2_devide_factor = REG_ADD_OFF_TTLIN1 + 2,
kttlin3_devide_factor = REG_ADD_OFF_TTLIN1 + 3,
kttlin4_devide_factor = REG_ADD_OFF_TTLIN1 + 4,
kttlin1_filter_factor = REG_ADD_OFF_TTLIN1 + 5,
kttlin2_filter_factor = REG_ADD_OFF_TTLIN1 + 6,
kttlin3_filter_factor = REG_ADD_OFF_TTLIN1 + 7,
kttlin4_filter_factor = REG_ADD_OFF_TTLIN1 + 8,
} RegAdd_t;
k_ttlin_en_reg = REGADDOFF__TTLIN + 0,
k_ttlin1_freq_detector_reg = REGADDOFF__TTLIN + 1,
k_ttlin2_freq_detector_reg = REGADDOFF__TTLIN + 2,
k_ttlin3_freq_detector_reg = REGADDOFF__TTLIN + 3,
k_ttlin4_freq_detector_reg = REGADDOFF__TTLIN + 4,
k_ttlin1_filter_factor_reg = REGADDOFF__TTLIN + 5,
k_ttlin2_filter_factor_reg = REGADDOFF__TTLIN + 6,
k_ttlin3_filter_factor_reg = REGADDOFF__TTLIN + 7,
k_ttlin4_filter_factor_reg = REGADDOFF__TTLIN + 8,
}
RegAdd_t;
} // namespace reg
} // namespace xsync
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