xsync_fpge/source/src/sys/sys_clock.v

`include "../config.v"
module sys_clock #(
    parameter REG_START_ADD  = 0,
    parameter SYS_CLOCK_FREQ = 10000000
) (
    input clk,   //clock input
    input rst_n, //asynchronous reset input, low active

    //寄存器读写接口
    input       [31:0] addr,
    input       [31:0] wr_data,
    input              wr_en,
    output wire [31:0] rd_data,

    input  [31:0] signal_in,
    output        sys_clock
);

  /*******************************************************************************
   *                                 寄存器列表                                  *
   *******************************************************************************/
  reg  [31:0] reg1_sig_src;  //!信号源选择
  reg  [31:0] reg2_freq_division_ctrl;  //!分频控制
  reg  [31:0] reg3_freq_multiplication_ctrl;  //!倍频控制
  reg  [31:0] reg4_freq_detect_bias;  //!频率探测滤波系数
  reg  [31:0] reg5_trigger_edge_select;  //!触发电平
  wire [31:0] regE_infreq_detect;  //!输入频率探测
  wire [31:0] regF_outfreq_detect;  //!输出频率探测

  wire [31:0] reg_wr_index;  //!寄存器写入时相对地址
  wire        signal_in_choose;  //!选择的信号源
  wire        signal_in_af_pll;


  //!TTLOUT_寄存器自动赋值选择器
  zutils_register_advanced #(
      .REG_START_ADD(REG_START_ADD)
  ) _register (
      .clk    (clk),
      .rst_n  (rst_n),
      .addr   (addr),
      .wr_data(wr_data),
      .wr_en  (wr_en),
      .rd_data(rd_data),
      .reg1   (reg1_sig_src),
      .reg2   (reg2_freq_division_ctrl),
      .reg3   (reg3_freq_multiplication_ctrl),
      .reg4   (reg4_freq_detect_bias),
      .reg5   (reg5_trigger_edge_select),

      .regE      (regE_infreq_detect),
      .regF      (regF_outfreq_detect),
      .reg_wr_sig(reg_wr_sig),
      .reg_index (reg_wr_index)
  );

  //!寄存器写入逻辑
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin

      reg1_sig_src                  <= `SIGNAL_INTERNAL_CLOCK_SIG;  //!默认为内部时钟
      reg2_freq_division_ctrl       <= 0;
      reg3_freq_multiplication_ctrl <= 0;
      reg4_freq_detect_bias         <= `FREQ_DETECT_BIAS_DEFAULT;
    end else begin
      if (reg_wr_sig) begin
        case (reg_wr_index)
          1: reg1_sig_src <= wr_data;
          2: reg2_freq_division_ctrl <= wr_data;
          3: reg3_freq_multiplication_ctrl <= wr_data;
          4: reg4_freq_detect_bias <= wr_data;
          5: reg5_trigger_edge_select <= wr_data;
          default: begin
          end
        endcase
      end
    end
  end

  //!信号选择器
  zutils_multiplexer_32t1 signal_in_multiplexer (
      .chooseindex(reg1_sig_src),
      .signal     (signal_in),
      .signalout  (signal_in_choose)
  );

  //!pll信号处理
  zsimple_pll _simple_pll (
      .clk                (clk),
      .rst_n              (rst_n),
      .insignal           (signal_in_choose),
      .trigger_eage_type  (reg5_trigger_edge_select),
      .freq_detect_bias   (reg4_freq_detect_bias),
      .freq_division      (reg2_freq_division_ctrl),
      .freq_multiplication(reg3_freq_multiplication_ctrl),
      .polarity_ctrl      (1'd0),
      .cfg_change         (reg_wr_sig),
      .outsignal          (signal_in_af_pll)
  );

  zutils_freq_detector_v2 in_freq_detector (
      .clk             (clk),
      .rst_n           (rst_n),
      .freq_detect_bias(reg4_freq_detect_bias),
      .pluse_input     (signal_in_choose),
      .pluse_width_cnt (regE_infreq_detect)
  );

  zutils_freq_detector_v2 output_freq_detector (
      .clk             (clk),
      .rst_n           (rst_n),
      .freq_detect_bias(reg4_freq_detect_bias),
      .pluse_input     (sys_clock),
      .pluse_width_cnt (regF_outfreq_detect)
  );
  assign sys_clock = signal_in_af_pll;

endmodule