xsync_fpge/source/src/uart_reg_reader.v

module uart_reg_reader #(
    parameter CLK_FRE   = 50,     //clock frequency(Mhz)
    parameter BAUD_RATE = 115200  //serial baud rate
) (
    input              clk,            //clock input
    input              rst_n,          //asynchronous reset input, low active
    input  wire [31:0] reg_data,       //received serial data 
    output reg  [31:0] reg_add,
    output reg         reg_add_valid,
    input  wire        uart_rx_pin,
    output wire        uart_tx_pin
);
  //
  //           overtime
  //   |----------------------^
  //   v                      | 
  //  IDLE ---------------> READ REG ADD  --------------->  READ_REG ---------------> SEND_REG_DATA
  //  ^                                                                                    |
  //  |------------------------------------------------------------------------------------v
  //
  //    
  //
  //
  parameter STATE_IDLE = 0;
  parameter STATE_READ_REG_ADD = 1;
  parameter STATE_READ_REG = 2;
  parameter STATE_SEND_REG_DATA = 3;
  parameter STATE_WAIT_SEND_END = 4;

  wire [7:0] rx_data;
  wire       rx_data_valid;
  wire       rx_data_ready;

  wire       tx_data_ready;
  reg  [7:0] tx_data = 0;
  reg        tx_data_valid = 0;

  reg  [7:0] state = 0;
  reg  [7:0] rxpacket_num = 0;
  reg  [7:0] txpacket_num = 0;
  reg  [7:0] rxdatacache = 0;  //接收数据buffer

  uart_rx #(
      .CLK_FRE  (CLK_FRE),
      .BAUD_RATE(BAUD_RATE)
  ) uart_rx_impl (
      .clk          (clk),            // input
      .rst_n        (rst_n),          // input
      .rx_data      (rx_data),        // output
      .rx_data_valid(rx_data_valid),  // output
      .rx_data_ready(rx_data_ready),  // input
      .rx_pin       (uart_rx_pin)     // input
  );

  uart_tx #(
      .CLK_FRE  (CLK_FRE),
      .BAUD_RATE(BAUD_RATE)
  ) uart_tx_impl (
      .clk          (clk),            // input
      .rst_n        (rst_n),          // input
      .tx_data      (tx_data),        // input
      .tx_data_valid(tx_data_valid),  // input
      .tx_data_ready(tx_data_ready),  // output
      .tx_pin       (uart_tx_pin)     // output
  );


  assign rx_data_ready = 1'b1;
  reg [ 7:0] substep = 0;
  reg [31:0] reg_data_cache = 0;


  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      state <= STATE_IDLE;
      rxpacket_num <= 0;
      txpacket_num <= 0;
      substep <= 0;
      reg_add <= 0;
      reg_add_valid <= 0;
    end else begin
      case (state)
        STATE_IDLE: begin
          rxpacket_num <= 0;
          txpacket_num <= 0;
          substep <= 0;
          state <= STATE_READ_REG_ADD;
        end
        STATE_READ_REG_ADD: begin
          if (rxpacket_num == 1) begin
            state <= STATE_READ_REG;
          end else if (rx_data_valid) begin
            rxdatacache  <= rx_data;
            rxpacket_num <= rxpacket_num + 1;
          end
        end
        STATE_READ_REG: begin
          case (substep)
            0: begin
              reg_add_valid <= 1;
              reg_add[7:0] <= rxdatacache;
              substep <= 1;
            end
            1: begin
              tx_data_valid <= 0;
              substep <= 0;
              state <= STATE_SEND_REG_DATA;
            end
          endcase
        end
        STATE_SEND_REG_DATA: begin
          case (substep)
            0: begin
              case (txpacket_num)
                0: begin
                  tx_data[7:0] <= reg_data_cache[7:0];
                end
                1: begin
                  tx_data[7:0] <= reg_data_cache[15:8];
                end
                2: begin
                  tx_data[7:0] <= reg_data_cache[23:16];
                end
                3: begin
                  tx_data[7:0] <= reg_data_cache[31:24];
                end
                default: begin
                  tx_data[7:0] <= 0;
                end
              endcase
              tx_data_valid <= 1;
              txpacket_num <= txpacket_num + 1;
              substep <= 1;
            end
            1: begin
              tx_data_valid <= 0;
              substep <= 2;
            end
            2: begin
              if (tx_data_ready) begin
                if (txpacket_num != 4) begin
                  substep <= 0;
                end else begin
                  substep <= 0;
                  state   <= STATE_IDLE;
                end
              end
            end
          endcase
        end
        default begin
          state <= STATE_IDLE;
        end
      endcase
    end
  end
endmodule