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添加延时模块

master
zhaohe 1 year ago
parent
d14023b805
commit
030eb27861
27 changed files with 1992 additions and 71 deletions
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  1. 2
      ip_backup/20240321095414/ShiftRegister/.last_generated
  2. 92
      ip_backup/20240321095414/ShiftRegister/ShiftRegister.idf
  3. 83
      ip_backup/20240321095414/ShiftRegister/ShiftRegister.v
  4. 168
      ip_backup/20240321095414/ShiftRegister/ShiftRegister_tb.v
  5. 15
      ip_backup/20240321095414/ShiftRegister/ShiftRegister_tmpl.v
  6. 27
      ip_backup/20240321095414/ShiftRegister/ShiftRegister_tmpl.vhdl
  7. 21
      ip_backup/20240321095414/ShiftRegister/generate.log
  8. 111
      ip_backup/20240321095414/ShiftRegister/rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v
  9. 111
      ip_backup/20240321095414/ShiftRegister/rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v
  10. 2
      ipcore/ShiftRegister/.last_generated
  11. 92
      ipcore/ShiftRegister/ShiftRegister.idf
  12. 83
      ipcore/ShiftRegister/ShiftRegister.v
  13. 168
      ipcore/ShiftRegister/ShiftRegister_tb.v
  14. 15
      ipcore/ShiftRegister/ShiftRegister_tmpl.v
  15. 27
      ipcore/ShiftRegister/ShiftRegister_tmpl.vhdl
  16. 21
      ipcore/ShiftRegister/generate.log
  17. 111
      ipcore/ShiftRegister/rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v
  18. 111
      ipcore/ShiftRegister/rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v
  19. 94
      led_test.pds
  20. 1
      source/src/config.v
  21. 4
      source/src/output/camera_sync_signal_output.v
  22. 4
      source/src/spi_reg_bus.v
  23. 266
      source/src/sys_signal_delayer.v
  24. 129
      source/src/top.v
  25. 77
      source/src/zutils/zutils_pluse_delayer.v
  26. 104
      source/src/zutils/zutils_sig_delayer.v
  27. 124
      source/src/zutils/zutils_sig_delayer_v2.v

2
ip_backup/20240321095414/ShiftRegister/.last_generated
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2024-03-20 17:08
rev_1

92
ip_backup/20240321095414/ShiftRegister/ShiftRegister.idf
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<?xml version="1.0" encoding="UTF-8"?>
<ip_inst>
<header>
<vendor>Pango</vendor>
<id>06100103</id>
<display_name>Distributed Shift Register</display_name>
<name>Distributed Shift Register</name>
<version>1.2</version>
<instance>ShiftRegister</instance>
<family>Logos</family>
<device>PGL22G</device>
<package>MBG324</package>
<speedgrade>-6</speedgrade>
<generator version="2021.1-SP7" build="86875">IP Compiler</generator>
</header>
<param_list>
<param>
<name>DATA_WIDTH</name>
<value>1</value>
</param>
<param>
<name>SHIFT_REG_TYPE</name>
<value>dynamic_latency</value>
</param>
<param>
<name>VARIABLE_MAX_DEPTH</name>
<value>1024</value>
</param>
<param>
<name>RST_TYPE</name>
<value>ASYNC</value>
</param>
<param>
<name>FIXED_DEPTH</name>
<value>1024</value>
</param>
<param>
<name>SHIFT_REG_TYPE_BOOL</name>
<value>true</value>
</param>
</param_list>
<pin_list>
<pin>
<name>din</name>
<text>din</text>
<dir>input</dir>
<pos>left</pos>
</pin>
<pin>
<name>addr</name>
<text>addr</text>
<dir>input</dir>
<pos>left</pos>
<msb>9</msb>
<lsb>0</lsb>
</pin>
<pin>
<name>clk</name>
<text>clk</text>
<dir>input</dir>
<pos>left</pos>
</pin>
<pin>
<name>rst</name>
<text>rst</text>
<dir>input</dir>
<pos>left</pos>
</pin>
<pin>
<name>dout</name>
<text>dout</text>
<dir>output</dir>
<pos>right</pos>
</pin>
</pin_list>
<synthesis>
<script><![CDATA[set_option -vlog_std v2001]]></script>
<script><![CDATA[set_option -disable_io_insertion 1]]></script>
</synthesis>
<file_list>
<output>
<file pathname="generate.log" format="log" description="Generate Log"/>
<file pathname="ShiftRegister_tmpl.v" format="verilog" description="Instantiation Template"/>
<file pathname="ShiftRegister_tmpl.vhdl" format="vhdl" description="Instantiation Template"/>
</output>
<source>
<file pathname="rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v"/>
<file pathname="rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v"/>
<file pathname="ShiftRegister.v"/>
</source>
</file_list>
</ip_inst>

83
ip_backup/20240321095414/ShiftRegister/ShiftRegister.v
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// Created by IP Generator (Version 2021.1-SP7 build 86875)
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2014 PANGO MICROSYSTEMS, INC
// ALL RIGHTS REVERVED.
//
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
//
//////////////////////////////////////////////////////////////////////////////
//
// Library:
// Filename:ShiftRegister.v
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module ShiftRegister
(
din ,
addr ,
clk ,
rst ,
dout
);
localparam FIXED_DEPTH = 1024 ; // @IPC int 1,1024
localparam VARIABLE_MAX_DEPTH = 1024 ; // @IPC int 1,1024
localparam DATA_WIDTH = 1 ; // @IPC int 1,256
localparam SHIFT_REG_TYPE = "dynamic_latency" ; // @IPC enum fixed_latency,dynamic_latency
localparam SHIFT_REG_TYPE_BOOL = 1 ; // @IPC bool
localparam RST_TYPE = "ASYNC" ; // @IPC enum ASYNC,SYNC
localparam DEPTH = (SHIFT_REG_TYPE=="fixed_latency" ) ? FIXED_DEPTH :
(SHIFT_REG_TYPE=="dynamic_latency") ? VARIABLE_MAX_DEPTH : 0;
localparam ADDR_WIDTH = (DEPTH<=16) ? 4 :
(DEPTH<=32) ? 5 :
(DEPTH<=64) ? 6 :
(DEPTH<=128) ? 7 :
(DEPTH<=256) ? 8 :
(DEPTH<=512) ? 9 : 10 ;
input wire [DATA_WIDTH-1:0] din ;
input wire [ADDR_WIDTH-1:0] addr ;
input wire clk ;
input wire rst ;
output wire [DATA_WIDTH-1:0] dout ;
ipm_distributed_shiftregister_v1_2_ShiftRegister
#(
.FIXED_DEPTH (FIXED_DEPTH ) ,
.VARIABLE_MAX_DEPTH (VARIABLE_MAX_DEPTH ) ,
.DATA_WIDTH (DATA_WIDTH ) ,
.SHIFT_REG_TYPE (SHIFT_REG_TYPE ) ,
.RST_TYPE (RST_TYPE )
)u_ipm_distributed_shiftregister_ShiftRegister
(
.din (din ) ,
.addr (addr ) ,
.clk (clk ) ,
.rst (rst ) ,
.dout (dout )
);
endmodule

168
ip_backup/20240321095414/ShiftRegister/ShiftRegister_tb.v
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// Created by IP Generator (Version 2021.1-SP7 build 86875)
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2014 PANGO MICROSYSTEMS, INC
// ALL RIGHTS REVERVED.
//
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
//
//////////////////////////////////////////////////////////////////////////////
//
// Library:
// Filename:TB ShiftRegister_tb.v
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ShiftRegister_tb ();
localparam T_CLK_PERIOD = 10 ; //clock a half perid
localparam T_RST_TIME = 200 ; //reset time
localparam FIXED_DEPTH = 1024 ; // @IPC int 1,1024
localparam VARIABLE_MAX_DEPTH = 1024 ; // @IPC int 1,1024
localparam DATA_WIDTH = 1 ; // @IPC int 1,256
localparam SHIFT_REG_TYPE = "dynamic_latency" ; // @IPC enum fixed_latency,dynamic_latency
localparam SHIFT_REG_TYPE_BOOL = 1 ; // @IPC bool
localparam RST_TYPE = "ASYNC" ; // @IPC enum ASYNC,SYNC
localparam DEPTH = (SHIFT_REG_TYPE=="fixed_latency") ? FIXED_DEPTH :
(SHIFT_REG_TYPE=="dynamic_latency") ? VARIABLE_MAX_DEPTH : 0;
localparam ADDR_WIDTH = (DEPTH<=16) ? 4 :
(DEPTH<=32) ? 5 :
(DEPTH<=64) ? 6 :
(DEPTH<=128) ? 7 :
(DEPTH<=256) ? 8 :
(DEPTH<=512) ? 9 : 10 ;
// variable declaration
reg clk_tb ;
reg tb_rst ;
reg [ADDR_WIDTH-1:0] tb_addr ;
reg [ADDR_WIDTH-1:0] addr ;
reg [DATA_WIDTH-1:0] tb_wrdata ;
wire [DATA_WIDTH-1:0] tb_rddata ;
reg check_err ;
reg [2:0] results_cnt;
wire [DATA_WIDTH-1:0] tb_tmp ;
reg [ADDR_WIDTH-1:0] cnt ;
reg cmp_en ;
assign tb_tmp = tb_rddata + DEPTH + 1;
//************************************************************ CGU ****************************************************************************
//generate clk_tb
initial
begin
clk_tb = 0;
forever #(T_CLK_PERIOD/2) clk_tb = ~clk_tb;
end
//********************************************************* DGU ********************************************************************************
initial begin
tb_addr = 0;
tb_wrdata = 0;
cnt = 0;
tb_rst = 1;
addr = VARIABLE_MAX_DEPTH;
#T_RST_TIME ;
tb_rst = 0;
#10 ;
$display("writing shiftregister");
write_shiftregister;
#10;
$display("shiftregister Simulation done");
if (|results_cnt)
$display("Simulation Failed due to Error Found.") ;
else
$display("Simulation Success.") ;
$finish ;
end
//***************************************************************** DUT INST **************************************************************************************
always@(posedge clk_tb or posedge tb_rst) begin
if(tb_rst)
check_err = 0;
else begin
cnt = cnt + 1;
if(cnt > DEPTH + 2 && tb_wrdata != tb_tmp && cmp_en) begin
check_err = 1;
end
else
check_err = 0;
end
end
always @(posedge clk_tb or posedge tb_rst)
begin
if (tb_rst)
results_cnt <= 3'b000 ;
else if (&results_cnt)
results_cnt <= 3'b100 ;
else if (check_err)
results_cnt <= results_cnt + 3'd1 ;
end
integer result_fid;
initial begin
result_fid = $fopen ("sim_results.log","a");
$fmonitor(result_fid,"err_chk=%b",check_err);
end
GTP_GRS GRS_INST(
.GRS_N(1'b1)
);
ShiftRegister U_ShiftRegister (
.addr (addr ), //input wire [`T_A_ADDR_WIDTH-1 : 0]
.din (tb_wrdata ), //input wire [`T_A_DATA_WIDTH-1 : 0]
.dout (tb_rddata ), //output wire [`T_A_DATA_WIDTH-1 : 0]
.rst (tb_rst ), //input wire
.clk (clk_tb )
);
task write_shiftregister;
integer i;
begin
tb_wrdata = 0;
tb_addr = 0;
cmp_en = 0;
while ( tb_addr < 2**ADDR_WIDTH - 1)
begin
@(posedge clk_tb);
tb_addr = tb_addr + 1'b1;
tb_wrdata = tb_wrdata + 1'b1;
cmp_en = 1'b1;
end
cmp_en = 0;
end
endtask
endmodule

15
ip_backup/20240321095414/ShiftRegister/ShiftRegister_tmpl.v
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// Created by IP Generator (Version 2021.1-SP7 build 86875)
// Instantiation Template
//
// Insert the following codes into your Verilog file.
// * Change the_instance_name to your own instance name.
// * Change the signal names in the port associations
ShiftRegister the_instance_name (
.din(din), // input
.addr(addr), // input [9:0]
.clk(clk), // input
.rst(rst), // input
.dout(dout) // output
);

27
ip_backup/20240321095414/ShiftRegister/ShiftRegister_tmpl.vhdl
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-- Created by IP Generator (Version 2021.1-SP7 build 86875)
-- Instantiation Template
--
-- Insert the following codes into your VHDL file.
-- * Change the_instance_name to your own instance name.
-- * Change the net names in the port map.
COMPONENT ShiftRegister
PORT (
din : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
dout : OUT STD_LOGIC
);
END COMPONENT;
the_instance_name : ShiftRegister
PORT MAP (
din => din,
addr => addr,
clk => clk,
rst => rst,
dout => dout
);

21
ip_backup/20240321095414/ShiftRegister/generate.log
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IP Generator (Version 2021.1-SP7 build 86875)
Check out license ...
Start generating at 2024-03-20 17:08
Instance: ShiftRegister (D:\workspace\p_lusterinc\xsync_fpge\ipcore\ShiftRegister\ShiftRegister.idf)
IP: Distributed Shift Register (1.2)
Part: Logos-PGL22G-MBG324--6
Create directory 'rtl' ...
Copy 'rtl\ipm_distributed_sdpram_v1_2.v.xml' to 'rtl' ...
Copy 'rtl\ipm_distributed_shiftregister_v1_2.v.xml' to 'rtl' ...
Compile file 'rtl\ipm_distributed_sdpram_v1_2.v.xml' to 'rtl\ipm_distributed_sdpram_v1_2_ShiftRegister.v' ...
Compile file 'rtl\ipm_distributed_shiftregister_v1_2.v.xml' to 'rtl\ipm_distributed_shiftregister_v1_2_ShiftRegister.v' ...
Copy 'ipm_distributed_shiftregister_wrapper_v1_2.v.xml' ...
Copy 'ipm_distributed_shiftregister_wrapper_v1_2_tb.v.xml' ...
Compile file 'ipm_distributed_shiftregister_wrapper_v1_2.v.xml' to 'ShiftRegister.v' ...
Found top module 'ShiftRegister' in file 'ShiftRegister.v'.
Compile file 'ipm_distributed_shiftregister_wrapper_v1_2_tb.v.xml' to 'ShiftRegister_tb.v' ...
Create template file 'ShiftRegister_tmpl.v' ...
Create template file 'ShiftRegister_tmpl.vhdl' ...
There are 3 source files to synthesize.
Synthesis is disabled.
Done: 0 error(s), 0 warning(s)

111
ip_backup/20240321095414/ShiftRegister/rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v
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// Created by IP Generator (Version 2021.1-SP7 build 86875)
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2014 PANGO MICROSYSTEMS, INC
// ALL RIGHTS REVERVED.
//
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
//
//////////////////////////////////////////////////////////////////////////////
//
// Library:
// Filename:ipm_distributed_sdpram_v1_2_ShiftRegister.v
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module ipm_distributed_sdpram_v1_2_ShiftRegister
#(
parameter ADDR_WIDTH = 4 , //address width range:4-10
parameter DATA_WIDTH = 4 , //data width range:1-256
parameter RST_TYPE = "ASYNC" , //reset type "ASYNC" "SYNC"
parameter OUT_REG = 0 , //output options :non_register(0) register(1)
parameter INIT_FILE = "NONE" , //legal value:"NONE" or "initial file name"
parameter FILE_FORMAT = "BIN" //initial data format : "BIN" or "HEX"
)
(
input wire [DATA_WIDTH-1:0] wr_data ,
input wire [ADDR_WIDTH-1:0] wr_addr ,
input wire [ADDR_WIDTH-1:0] rd_addr ,
input wire wr_clk ,
input wire rd_clk ,
input wire wr_en ,
input wire rst ,
output wire [DATA_WIDTH-1:0] rd_data
)/* synthesis syn_ramstyle = "select_ram" */;
wire asyn_rst ;
wire syn_rst ;
wire [DATA_WIDTH-1:0] q ;
reg [DATA_WIDTH-1:0] q_reg ;
reg [DATA_WIDTH-1:0] mem [2**ADDR_WIDTH-1:0];
//***********************************************************************reset*******************************************************************
assign asyn_rst = (RST_TYPE == "ASYNC") ? rst : 0 ;
assign syn_rst = (RST_TYPE == "SYNC" ) ? rst : 0 ;
//initialize sdpram
generate
integer i,j;
if (INIT_FILE != "NONE") begin
if (FILE_FORMAT == "BIN") begin
initial begin
$readmemb(INIT_FILE,mem);
end
end
else if (FILE_FORMAT == "HEX") begin
initial begin
$readmemh(INIT_FILE,mem);
end
end
end
else begin
initial begin
for (i=0;i<2**ADDR_WIDTH;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
mem[i][j] = 1'b0;
end
end
end
end
endgenerate
//write & read
generate
always @(posedge wr_clk) begin
if(wr_en)
mem[wr_addr] <= wr_data;
end
assign q = mem[rd_addr];
if (RST_TYPE == "ASYNC") begin
always@(posedge rd_clk or posedge asyn_rst)
begin
if(asyn_rst)
q_reg <= {DATA_WIDTH{1'b0}};
else
q_reg <= q;
end
end
else if (RST_TYPE == "SYNC") begin
always@(posedge rd_clk)
begin
if(syn_rst)
q_reg <= {DATA_WIDTH{1'b0}};
else
q_reg <= q;
end
end
endgenerate
assign rd_data = (OUT_REG == 1) ? q_reg : q;
endmodule

111
ip_backup/20240321095414/ShiftRegister/rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v
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// Created by IP Generator (Version 2021.1-SP7 build 86875)
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2014 PANGO MICROSYSTEMS, INC
// ALL RIGHTS REVERVED.
//
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
//
//////////////////////////////////////////////////////////////////////////////
//
// Library:
// Filename:ipm_distributed_shiftregister_v1_2_ShiftRegister.v
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module ipm_distributed_shiftregister_v1_2_ShiftRegister
#(
parameter FIXED_DEPTH = 16 , //range:1-1024
parameter VARIABLE_MAX_DEPTH = 16 , //range:1-1024
parameter DATA_WIDTH = 16 , //data width range:1-256
parameter SHIFT_REG_TYPE = "fixed_latency" , //default value :"fixed_latency" or "dynamic_latency"
parameter RST_TYPE = "ASYNC" //reset type "ASYNC" "SYNC"
)
(
din ,
addr,
clk ,
rst ,
dout
);
localparam DEPTH = (SHIFT_REG_TYPE=="fixed_latency" ) ? FIXED_DEPTH :
(SHIFT_REG_TYPE=="dynamic_latency") ? VARIABLE_MAX_DEPTH : 0;
localparam ADDR_WIDTH = (DEPTH<=16 ) ? 4 :
(DEPTH<=32 ) ? 5 :
(DEPTH<=64 ) ? 6 :
(DEPTH<=128) ? 7 :
(DEPTH<=256) ? 8 :
(DEPTH<=512) ? 9 : 10;
//***********************************************************IO******************************
input wire [DATA_WIDTH-1:0] din ;
input wire [ADDR_WIDTH-1:0] addr ;
input wire clk ;
input wire rst ;
output wire [DATA_WIDTH-1:0] dout ;
//*******************************************************************************************
reg [ADDR_WIDTH-1:0] wr_addr ;
reg [ADDR_WIDTH-1:0] rd_addr ;
wire asyn_rst ;
wire syn_rst ;
assign asyn_rst = (RST_TYPE == "ASYNC") ? rst : 0;
assign syn_rst = (RST_TYPE == "SYNC" ) ? rst : 0;
generate
if (RST_TYPE == "ASYNC") begin
always @(posedge clk or posedge asyn_rst) begin
if (asyn_rst)
wr_addr <= 0;
else
wr_addr <= wr_addr+1;
end
end
else if (RST_TYPE == "SYNC") begin
always @(posedge clk) begin
if (syn_rst)
wr_addr <= 0;
else
wr_addr <= wr_addr+1;
end
end
endgenerate
always @(*) begin
if (SHIFT_REG_TYPE=="fixed_latency")
rd_addr = wr_addr+2**ADDR_WIDTH-DEPTH;
else if (SHIFT_REG_TYPE=="dynamic_latency")
rd_addr = wr_addr+2**ADDR_WIDTH-addr;
end
//********************************************************* SDP INST **************************************************
ipm_distributed_sdpram_v1_2_ShiftRegister
#(
.ADDR_WIDTH (ADDR_WIDTH ) ,
.DATA_WIDTH (DATA_WIDTH ) ,
.RST_TYPE (RST_TYPE ) ,
.OUT_REG (1'b1 ) ,
.INIT_FILE ("NONE" ) ,
.FILE_FORMAT ("BIN" )
) u_ipm_distributed_sdpram_ShiftRegister
(
.wr_data (din ) ,
.wr_addr (wr_addr ) ,
.rd_addr (rd_addr ) ,
.wr_clk (clk ) ,
.rd_clk (clk ) ,
.wr_en (1'b1 ) ,
.rst (rst ) ,
.rd_data (dout )
);
endmodule

2
ipcore/ShiftRegister/.last_generated
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2024-03-21 09:54
rev_1

92
ipcore/ShiftRegister/ShiftRegister.idf
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<?xml version="1.0" encoding="UTF-8"?>
<ip_inst>
<header>
<vendor>Pango</vendor>
<id>06100103</id>
<display_name>Distributed Shift Register</display_name>
<name>Distributed Shift Register</name>
<version>1.2</version>
<instance>ShiftRegister</instance>
<family>Logos</family>
<device>PGL22G</device>
<package>MBG324</package>
<speedgrade>-6</speedgrade>
<generator version="2021.1-SP7" build="86875">IP Compiler</generator>
</header>
<param_list>
<param>
<name>DATA_WIDTH</name>
<value>1</value>
</param>
<param>
<name>SHIFT_REG_TYPE</name>
<value>dynamic_latency</value>
</param>
<param>
<name>VARIABLE_MAX_DEPTH</name>
<value>1024</value>
</param>
<param>
<name>RST_TYPE</name>
<value>ASYNC</value>
</param>
<param>
<name>FIXED_DEPTH</name>
<value>1024</value>
</param>
<param>
<name>SHIFT_REG_TYPE_BOOL</name>
<value>true</value>
</param>
</param_list>
<pin_list>
<pin>
<name>din</name>
<text>din</text>
<dir>input</dir>
<pos>left</pos>
</pin>
<pin>
<name>addr</name>
<text>addr</text>
<dir>input</dir>
<pos>left</pos>
<msb>9</msb>
<lsb>0</lsb>
</pin>
<pin>
<name>clk</name>
<text>clk</text>
<dir>input</dir>
<pos>left</pos>
</pin>
<pin>
<name>rst</name>
<text>rst</text>
<dir>input</dir>
<pos>left</pos>
</pin>
<pin>
<name>dout</name>
<text>dout</text>
<dir>output</dir>
<pos>right</pos>
</pin>
</pin_list>
<synthesis>
<script><![CDATA[set_option -vlog_std v2001]]></script>
<script><![CDATA[set_option -disable_io_insertion 1]]></script>
</synthesis>
<file_list>
<output>
<file pathname="generate.log" format="log" description="Generate Log"/>
<file pathname="ShiftRegister_tmpl.v" format="verilog" description="Instantiation Template"/>
<file pathname="ShiftRegister_tmpl.vhdl" format="vhdl" description="Instantiation Template"/>
</output>
<source>
<file pathname="rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v"/>
<file pathname="rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v"/>
<file pathname="ShiftRegister.v"/>
</source>
</file_list>
</ip_inst>

83
ipcore/ShiftRegister/ShiftRegister.v
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@ -0,0 +1,83 @@
// Created by IP Generator (Version 2021.1-SP7 build 86875)
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2014 PANGO MICROSYSTEMS, INC
// ALL RIGHTS REVERVED.
//
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
//
//////////////////////////////////////////////////////////////////////////////
//
// Library:
// Filename:ShiftRegister.v
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module ShiftRegister
(
din ,
addr ,
clk ,
rst ,
dout
);
localparam FIXED_DEPTH = 1024 ; // @IPC int 1,1024
localparam VARIABLE_MAX_DEPTH = 1024 ; // @IPC int 1,1024
localparam DATA_WIDTH = 1 ; // @IPC int 1,256
localparam SHIFT_REG_TYPE = "dynamic_latency" ; // @IPC enum fixed_latency,dynamic_latency
localparam SHIFT_REG_TYPE_BOOL = 1 ; // @IPC bool
localparam RST_TYPE = "ASYNC" ; // @IPC enum ASYNC,SYNC
localparam DEPTH = (SHIFT_REG_TYPE=="fixed_latency" ) ? FIXED_DEPTH :
(SHIFT_REG_TYPE=="dynamic_latency") ? VARIABLE_MAX_DEPTH : 0;
localparam ADDR_WIDTH = (DEPTH<=16) ? 4 :
(DEPTH<=32) ? 5 :
(DEPTH<=64) ? 6 :
(DEPTH<=128) ? 7 :
(DEPTH<=256) ? 8 :
(DEPTH<=512) ? 9 : 10 ;
input wire [DATA_WIDTH-1:0] din ;
input wire [ADDR_WIDTH-1:0] addr ;
input wire clk ;
input wire rst ;
output wire [DATA_WIDTH-1:0] dout ;
ipm_distributed_shiftregister_v1_2_ShiftRegister
#(
.FIXED_DEPTH (FIXED_DEPTH ) ,
.VARIABLE_MAX_DEPTH (VARIABLE_MAX_DEPTH ) ,
.DATA_WIDTH (DATA_WIDTH ) ,
.SHIFT_REG_TYPE (SHIFT_REG_TYPE ) ,
.RST_TYPE (RST_TYPE )
)u_ipm_distributed_shiftregister_ShiftRegister
(
.din (din ) ,
.addr (addr ) ,
.clk (clk ) ,
.rst (rst ) ,
.dout (dout )
);
endmodule

168
ipcore/ShiftRegister/ShiftRegister_tb.v
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@ -0,0 +1,168 @@
// Created by IP Generator (Version 2021.1-SP7 build 86875)
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2014 PANGO MICROSYSTEMS, INC
// ALL RIGHTS REVERVED.
//
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
//
//////////////////////////////////////////////////////////////////////////////
//
// Library:
// Filename:TB ShiftRegister_tb.v
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ShiftRegister_tb ();
localparam T_CLK_PERIOD = 10 ; //clock a half perid
localparam T_RST_TIME = 200 ; //reset time
localparam FIXED_DEPTH = 1024 ; // @IPC int 1,1024
localparam VARIABLE_MAX_DEPTH = 1024 ; // @IPC int 1,1024
localparam DATA_WIDTH = 1 ; // @IPC int 1,256
localparam SHIFT_REG_TYPE = "dynamic_latency" ; // @IPC enum fixed_latency,dynamic_latency
localparam SHIFT_REG_TYPE_BOOL = 1 ; // @IPC bool
localparam RST_TYPE = "ASYNC" ; // @IPC enum ASYNC,SYNC
localparam DEPTH = (SHIFT_REG_TYPE=="fixed_latency") ? FIXED_DEPTH :
(SHIFT_REG_TYPE=="dynamic_latency") ? VARIABLE_MAX_DEPTH : 0;
localparam ADDR_WIDTH = (DEPTH<=16) ? 4 :
(DEPTH<=32) ? 5 :
(DEPTH<=64) ? 6 :
(DEPTH<=128) ? 7 :
(DEPTH<=256) ? 8 :
(DEPTH<=512) ? 9 : 10 ;
// variable declaration
reg clk_tb ;
reg tb_rst ;
reg [ADDR_WIDTH-1:0] tb_addr ;
reg [ADDR_WIDTH-1:0] addr ;
reg [DATA_WIDTH-1:0] tb_wrdata ;
wire [DATA_WIDTH-1:0] tb_rddata ;
reg check_err ;
reg [2:0] results_cnt;
wire [DATA_WIDTH-1:0] tb_tmp ;
reg [ADDR_WIDTH-1:0] cnt ;
reg cmp_en ;
assign tb_tmp = tb_rddata + DEPTH + 1;
//************************************************************ CGU ****************************************************************************
//generate clk_tb
initial
begin
clk_tb = 0;
forever #(T_CLK_PERIOD/2) clk_tb = ~clk_tb;
end
//********************************************************* DGU ********************************************************************************
initial begin
tb_addr = 0;
tb_wrdata = 0;
cnt = 0;
tb_rst = 1;
addr = VARIABLE_MAX_DEPTH;
#T_RST_TIME ;
tb_rst = 0;
#10 ;
$display("writing shiftregister");
write_shiftregister;
#10;
$display("shiftregister Simulation done");
if (|results_cnt)
$display("Simulation Failed due to Error Found.") ;
else
$display("Simulation Success.") ;
$finish ;
end
//***************************************************************** DUT INST **************************************************************************************
always@(posedge clk_tb or posedge tb_rst) begin
if(tb_rst)
check_err = 0;
else begin
cnt = cnt + 1;
if(cnt > DEPTH + 2 && tb_wrdata != tb_tmp && cmp_en) begin
check_err = 1;
end
else
check_err = 0;
end
end
always @(posedge clk_tb or posedge tb_rst)
begin
if (tb_rst)
results_cnt <= 3'b000 ;
else if (&results_cnt)
results_cnt <= 3'b100 ;
else if (check_err)
results_cnt <= results_cnt + 3'd1 ;
end
integer result_fid;
initial begin
result_fid = $fopen ("sim_results.log","a");
$fmonitor(result_fid,"err_chk=%b",check_err);
end
GTP_GRS GRS_INST(
.GRS_N(1'b1)
);
ShiftRegister U_ShiftRegister (
.addr (addr ), //input wire [`T_A_ADDR_WIDTH-1 : 0]
.din (tb_wrdata ), //input wire [`T_A_DATA_WIDTH-1 : 0]
.dout (tb_rddata ), //output wire [`T_A_DATA_WIDTH-1 : 0]
.rst (tb_rst ), //input wire
.clk (clk_tb )
);
task write_shiftregister;
integer i;
begin
tb_wrdata = 0;
tb_addr = 0;
cmp_en = 0;
while ( tb_addr < 2**ADDR_WIDTH - 1)
begin
@(posedge clk_tb);
tb_addr = tb_addr + 1'b1;
tb_wrdata = tb_wrdata + 1'b1;
cmp_en = 1'b1;
end
cmp_en = 0;
end
endtask
endmodule

15
ipcore/ShiftRegister/ShiftRegister_tmpl.v
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@ -0,0 +1,15 @@
// Created by IP Generator (Version 2021.1-SP7 build 86875)
// Instantiation Template
//
// Insert the following codes into your Verilog file.
// * Change the_instance_name to your own instance name.
// * Change the signal names in the port associations
ShiftRegister the_instance_name (
.din(din), // input
.addr(addr), // input [9:0]
.clk(clk), // input
.rst(rst), // input
.dout(dout) // output
);

27
ipcore/ShiftRegister/ShiftRegister_tmpl.vhdl
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@ -0,0 +1,27 @@
-- Created by IP Generator (Version 2021.1-SP7 build 86875)
-- Instantiation Template
--
-- Insert the following codes into your VHDL file.
-- * Change the_instance_name to your own instance name.
-- * Change the net names in the port map.
COMPONENT ShiftRegister
PORT (
din : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
dout : OUT STD_LOGIC
);
END COMPONENT;
the_instance_name : ShiftRegister
PORT MAP (
din => din,
addr => addr,
clk => clk,
rst => rst,
dout => dout
);

21
ipcore/ShiftRegister/generate.log
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@ -0,0 +1,21 @@
IP Generator (Version 2021.1-SP7 build 86875)
Check out license ...
Start generating at 2024-03-21 09:54
Instance: ShiftRegister (D:\workspace\p_lusterinc\xsync_fpge\ipcore\ShiftRegister\ShiftRegister.idf)
IP: Distributed Shift Register (1.2)
Part: Logos-PGL22G-MBG324--6
Create directory 'rtl' ...
Copy 'rtl\ipm_distributed_sdpram_v1_2.v.xml' to 'rtl' ...
Copy 'rtl\ipm_distributed_shiftregister_v1_2.v.xml' to 'rtl' ...
Compile file 'rtl\ipm_distributed_sdpram_v1_2.v.xml' to 'rtl\ipm_distributed_sdpram_v1_2_ShiftRegister.v' ...
Compile file 'rtl\ipm_distributed_shiftregister_v1_2.v.xml' to 'rtl\ipm_distributed_shiftregister_v1_2_ShiftRegister.v' ...
Copy 'ipm_distributed_shiftregister_wrapper_v1_2.v.xml' ...
Copy 'ipm_distributed_shiftregister_wrapper_v1_2_tb.v.xml' ...
Compile file 'ipm_distributed_shiftregister_wrapper_v1_2.v.xml' to 'ShiftRegister.v' ...
Found top module 'ShiftRegister' in file 'ShiftRegister.v'.
Compile file 'ipm_distributed_shiftregister_wrapper_v1_2_tb.v.xml' to 'ShiftRegister_tb.v' ...
Create template file 'ShiftRegister_tmpl.v' ...
Create template file 'ShiftRegister_tmpl.vhdl' ...
There are 3 source files to synthesize.
Synthesis is disabled.
Done: 0 error(s), 0 warning(s)

111
ipcore/ShiftRegister/rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v
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@ -0,0 +1,111 @@
// Created by IP Generator (Version 2021.1-SP7 build 86875)
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2014 PANGO MICROSYSTEMS, INC
// ALL RIGHTS REVERVED.
//
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
//
//////////////////////////////////////////////////////////////////////////////
//
// Library:
// Filename:ipm_distributed_sdpram_v1_2_ShiftRegister.v
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module ipm_distributed_sdpram_v1_2_ShiftRegister
#(
parameter ADDR_WIDTH = 4 , //address width range:4-10
parameter DATA_WIDTH = 4 , //data width range:1-256
parameter RST_TYPE = "ASYNC" , //reset type "ASYNC" "SYNC"
parameter OUT_REG = 0 , //output options :non_register(0) register(1)
parameter INIT_FILE = "NONE" , //legal value:"NONE" or "initial file name"
parameter FILE_FORMAT = "BIN" //initial data format : "BIN" or "HEX"
)
(
input wire [DATA_WIDTH-1:0] wr_data ,
input wire [ADDR_WIDTH-1:0] wr_addr ,
input wire [ADDR_WIDTH-1:0] rd_addr ,
input wire wr_clk ,
input wire rd_clk ,
input wire wr_en ,
input wire rst ,
output wire [DATA_WIDTH-1:0] rd_data
)/* synthesis syn_ramstyle = "select_ram" */;
wire asyn_rst ;
wire syn_rst ;
wire [DATA_WIDTH-1:0] q ;
reg [DATA_WIDTH-1:0] q_reg ;
reg [DATA_WIDTH-1:0] mem [2**ADDR_WIDTH-1:0];
//***********************************************************************reset*******************************************************************
assign asyn_rst = (RST_TYPE == "ASYNC") ? rst : 0 ;
assign syn_rst = (RST_TYPE == "SYNC" ) ? rst : 0 ;
//initialize sdpram
generate
integer i,j;
if (INIT_FILE != "NONE") begin
if (FILE_FORMAT == "BIN") begin
initial begin
$readmemb(INIT_FILE,mem);
end
end
else if (FILE_FORMAT == "HEX") begin
initial begin
$readmemh(INIT_FILE,mem);
end
end
end
else begin
initial begin
for (i=0;i<2**ADDR_WIDTH;i=i+1) begin
for (j=0;j<DATA_WIDTH;j=j+1) begin
mem[i][j] = 1'b0;
end
end
end
end
endgenerate
//write & read
generate
always @(posedge wr_clk) begin
if(wr_en)
mem[wr_addr] <= wr_data;
end
assign q = mem[rd_addr];
if (RST_TYPE == "ASYNC") begin
always@(posedge rd_clk or posedge asyn_rst)
begin
if(asyn_rst)
q_reg <= {DATA_WIDTH{1'b0}};
else
q_reg <= q;
end
end
else if (RST_TYPE == "SYNC") begin
always@(posedge rd_clk)
begin
if(syn_rst)
q_reg <= {DATA_WIDTH{1'b0}};
else
q_reg <= q;
end
end
endgenerate
assign rd_data = (OUT_REG == 1) ? q_reg : q;
endmodule

111
ipcore/ShiftRegister/rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v
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@ -0,0 +1,111 @@
// Created by IP Generator (Version 2021.1-SP7 build 86875)
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2014 PANGO MICROSYSTEMS, INC
// ALL RIGHTS REVERVED.
//
// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC.
// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY
// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER.
//
//////////////////////////////////////////////////////////////////////////////
//
// Library:
// Filename:ipm_distributed_shiftregister_v1_2_ShiftRegister.v
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module ipm_distributed_shiftregister_v1_2_ShiftRegister
#(
parameter FIXED_DEPTH = 16 , //range:1-1024
parameter VARIABLE_MAX_DEPTH = 16 , //range:1-1024
parameter DATA_WIDTH = 16 , //data width range:1-256
parameter SHIFT_REG_TYPE = "fixed_latency" , //default value :"fixed_latency" or "dynamic_latency"
parameter RST_TYPE = "ASYNC" //reset type "ASYNC" "SYNC"
)
(
din ,
addr,
clk ,
rst ,
dout
);
localparam DEPTH = (SHIFT_REG_TYPE=="fixed_latency" ) ? FIXED_DEPTH :
(SHIFT_REG_TYPE=="dynamic_latency") ? VARIABLE_MAX_DEPTH : 0;
localparam ADDR_WIDTH = (DEPTH<=16 ) ? 4 :
(DEPTH<=32 ) ? 5 :
(DEPTH<=64 ) ? 6 :
(DEPTH<=128) ? 7 :
(DEPTH<=256) ? 8 :
(DEPTH<=512) ? 9 : 10;
//***********************************************************IO******************************
input wire [DATA_WIDTH-1:0] din ;
input wire [ADDR_WIDTH-1:0] addr ;
input wire clk ;
input wire rst ;
output wire [DATA_WIDTH-1:0] dout ;
//*******************************************************************************************
reg [ADDR_WIDTH-1:0] wr_addr ;
reg [ADDR_WIDTH-1:0] rd_addr ;
wire asyn_rst ;
wire syn_rst ;
assign asyn_rst = (RST_TYPE == "ASYNC") ? rst : 0;
assign syn_rst = (RST_TYPE == "SYNC" ) ? rst : 0;
generate
if (RST_TYPE == "ASYNC") begin
always @(posedge clk or posedge asyn_rst) begin
if (asyn_rst)
wr_addr <= 0;
else
wr_addr <= wr_addr+1;
end
end
else if (RST_TYPE == "SYNC") begin
always @(posedge clk) begin
if (syn_rst)
wr_addr <= 0;
else
wr_addr <= wr_addr+1;
end
end
endgenerate
always @(*) begin
if (SHIFT_REG_TYPE=="fixed_latency")
rd_addr = wr_addr+2**ADDR_WIDTH-DEPTH;
else if (SHIFT_REG_TYPE=="dynamic_latency")
rd_addr = wr_addr+2**ADDR_WIDTH-addr;
end
//********************************************************* SDP INST **************************************************
ipm_distributed_sdpram_v1_2_ShiftRegister
#(
.ADDR_WIDTH (ADDR_WIDTH ) ,
.DATA_WIDTH (DATA_WIDTH ) ,
.RST_TYPE (RST_TYPE ) ,
.OUT_REG (1'b1 ) ,
.INIT_FILE ("NONE" ) ,
.FILE_FORMAT ("BIN" )
) u_ipm_distributed_sdpram_ShiftRegister
(
.wr_data (din ) ,
.wr_addr (wr_addr ) ,
.rd_addr (rd_addr ) ,
.wr_clk (clk ) ,
.rd_clk (clk ) ,
.wr_en (1'b1 ) ,
.rst (rst ) ,
.rd_data (dout )
);
endmodule

94
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Wed Mar 6 00:21:26 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Mar 22 22:10:41 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-05T23:54:38")
(_timespec "2024-03-22T22:10:39")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -143,7 +143,7 @@
)
(_file "source/src/input/ttl_input.v"
(_format verilog)
(_timespec "2024-03-05T10:18:22")
(_timespec "2024-03-22T21:00:04")
)
(_file "source/src/zutils/ztuils_sig_devide.v"
(_format verilog)
@ -175,7 +175,7 @@
)
(_file "source/src/spi_reg_bus.v"
(_format verilog)
(_timespec "2024-03-04T18:25:03")
(_timespec "2024-03-21T15:13:16")
)
(_file "source/src/internal/internal_timecode_generator.v"
(_format verilog)
@ -207,12 +207,28 @@
)
(_file "source/src/output/camera_sync_signal_output.v"
(_format verilog)
(_timespec "2024-03-05T22:17:42")
(_timespec "2024-03-21T15:01:29")
)
(_file "source/src/business/record_sig_generator.v"
(_format verilog)
(_timespec "2024-03-06T00:10:36")
)
(_file "source/src/sys_signal_delayer.v"
(_format verilog)
(_timespec "2024-03-22T21:08:01")
)
(_file "source/src/zutils/zutils_sig_delayer.v"
(_format verilog)
(_timespec "2024-03-21T17:36:08")
)
(_file "source/src/zutils/zutils_sig_delayer_v2.v"
(_format verilog)
(_timespec "2024-03-22T22:10:19")
)
(_file "source/src/zutils/zutils_pluse_delayer.v"
(_format verilog)
(_timespec "2024-03-22T22:01:26")
)
)
)
(_widget wgt_my_ips_src
@ -226,6 +242,18 @@
(_ip "ipcore/genlock_sig_gen_pll/genlock_sig_gen_pll.idf"
(_timespec "2024-02-27T20:28:55")
)
(_ip "ipcore/ShiftRegister/ShiftRegister.idf"
(_timespec "2024-03-21T09:54:18")
(_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v"
(_timespec "2024-03-21T09:54:18")
)
(_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v"
(_timespec "2024-03-21T09:54:18")
)
(_ip_source_item "ipcore/ShiftRegister/ShiftRegister.v"
(_timespec "2024-03-21T09:54:18")
)
)
)
)
(_widget wgt_import_logic_con_file
@ -279,21 +307,21 @@
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 2))
(_gci_state (_integer 3))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-03-06T00:17:50")
(_timespec "2024-03-22T22:04:52")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-03-06T00:17:48")
(_timespec "2024-03-22T22:04:51")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-03-06T00:17:50")
(_timespec "2024-03-22T22:04:52")
)
)
)
@ -303,27 +331,27 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 2))
(_gci_state (_integer 3))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-03-06T00:19:28")
(_timespec "2024-03-22T22:04:57")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-03-06T00:19:37")
(_timespec "2024-03-22T22:04:57")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-03-06T00:19:42")
(_timespec "2024-03-22T22:04:58")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-03-06T00:19:42")
(_timespec "2024-03-22T22:04:58")
)
)
)
@ -340,25 +368,25 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 2))
(_gci_state (_integer 3))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-03-06T00:19:47")
(_timespec "2024-03-22T22:05:00")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-03-06T00:19:45")
(_timespec "2024-03-22T22:05:00")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-03-06T00:19:47")
(_timespec "2024-03-22T22:05:00")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-03-06T00:19:47")
(_timespec "2024-03-22T22:05:01")
)
)
)
@ -367,7 +395,7 @@
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-03-06T00:19:47")
(_timespec "2024-03-22T22:05:00")
)
)
)
@ -377,38 +405,38 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 2))
(_gci_state (_integer 3))
(_option mode (_string "fast"))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-06T00:21:07")
(_timespec "2024-03-22T22:05:08")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-06T00:21:07")
(_timespec "2024-03-22T22:05:08")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-06T00:21:07")
(_timespec "2024-03-22T22:05:08")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-06T00:21:07")
(_timespec "2024-03-22T22:05:08")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-06T00:20:03")
(_timespec "2024-03-22T22:05:05")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-06T00:21:07")
(_timespec "2024-03-22T22:05:08")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-06T00:21:08")
(_timespec "2024-03-22T22:05:09")
)
)
)
@ -439,23 +467,23 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 2))
(_gci_state (_integer 3))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-03-06T00:21:26")
(_timespec "2024-03-22T22:05:15")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-03-06T00:21:26")
(_timespec "2024-03-22T22:05:15")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-03-06T00:21:26")
(_timespec "2024-03-22T22:05:15")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-03-06T00:21:26")
(_timespec "2024-03-22T22:05:15")
)
)
)

1
source/src/config.v
View File

@ -16,6 +16,7 @@
`define REGADDOFF__SYS_GENLOCK 16'h0410
`define REGADDOFF__SYS_CLOCK 16'h0420
`define REGADDOFF__RECORD_SIG_GENERATOR 16'h0500
`define REGADDOFF__DELAYER 16'h0600
`define FREQ_DETECT_BIAS_DEFAULT 32'd10

4
source/src/output/camera_sync_signal_output.v
View File

@ -15,7 +15,7 @@ module camera_sync_signal_output #(
input record_en_sig,
output stm32if_camera_sync_out, //ttl输出信号
output stm32if_record_sync_out //
output stm32if_record_state_change_sig //
);
/*******************************************************************************
@ -78,6 +78,6 @@ module camera_sync_signal_output #(
);
assign stm32if_camera_sync_out = frame_sig_fa_process;
assign stm32if_record_sync_out = record_en_sig;
assign stm32if_record_state_change_sig = record_en_sig;
endmodule

4
source/src/spi_reg_bus.v
View File

@ -30,7 +30,8 @@ module spi_reg_bus (
input [31:0] rd_data_module_sys_timecode,
input [31:0] rd_data_module_sys_genlock,
input [31:0] rd_data_module_sys_clock,
input [31:0] rd_data_module_record_sig_generator
input [31:0] rd_data_module_record_sig_generator,
input [31:0] rd_data_module_sys_signal_delayer
);
reg [31:0] rd_data;
@ -71,6 +72,7 @@ module spi_reg_bus (
`REGADDOFF__SYS_GENLOCK: rd_data <= rd_data_module_sys_genlock;
`REGADDOFF__SYS_CLOCK: rd_data <= rd_data_module_sys_clock;
`REGADDOFF__RECORD_SIG_GENERATOR: rd_data <= rd_data_module_record_sig_generator;
`REGADDOFF__DELAYER: rd_data <= rd_data_module_sys_signal_delayer;
default: rd_data <= 0;
endcase

266
source/src/sys_signal_delayer.v
View File

@ -0,0 +1,266 @@
module sys_signal_delayer #(
parameter REG_START_ADD = 0,
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk, //! 时钟输入
input rst_n, //! 复位输入
input [31:0] addr, //! 寄存器地址
input [31:0] wr_data, //! 写入数据
input wr_en, //! 写使能
output wire [31:0] rd_data, //! 读出数据
/*******************************************************************************
* 输入信号延迟 *
*******************************************************************************/
input sync_ttl_in1,
input sync_ttl_in2,
input sync_ttl_in3,
input sync_ttl_in4,
input timecode_headphone_in,
input timecode_bnc_in,
input genlock_in_hsync,
input genlock_in_vsync,
input genlock_in_fsync,
output af_delay__sync_ttl_in1,
output af_delay__sync_ttl_in2,
output af_delay__sync_ttl_in3,
output af_delay__sync_ttl_in4,
output af_delay__timecode_headphone_in,
output af_delay__timecode_bnc_in,
output af_delay__genlock_in_hsync,
output af_delay__genlock_in_vsync,
output af_delay__genlock_in_fsync,
/*******************************************************************************
* 输出接口延迟 *
*******************************************************************************/
output sync_ttl_out1,
output sync_ttl_out2,
output sync_ttl_out3,
output sync_ttl_out4,
output stm32if_start_signal_out,
output stm32if_camera_sync_out,
output stm32if_timecode_sync_out,
input before_delay__sync_ttl_out1,
input before_delay__sync_ttl_out2,
input before_delay__sync_ttl_out3,
input before_delay__sync_ttl_out4,
input before_delay__stm32if_start_signal_out,
input before_delay__stm32if_camera_sync_out,
input before_delay__stm32if_timecode_sync_out
);
reg [31:0] r1_ctrl;
reg [31:0] r2_input_delay_cnt;
reg [31:0] r3_input_delay_freq_div;
reg [31:0] r4_output_delay_cnt;
reg [31:0] r5_output_delay_freq_div;
wire [31:0] reg_wr_index;
zutils_register_advanced #(
.REG_START_ADD(REG_START_ADD)
) _register (
.clk (clk),
.rst_n (rst_n),
.addr (addr),
.wr_data (wr_data),
.wr_en (wr_en),
.rd_data (rd_data),
.reg1 (r1_ctrl),
.reg2 (r2_input_delay_cnt),
.reg3 (r3_input_delay_freq_div),
.reg4 (r4_output_delay_cnt),
.reg5 (r5_output_delay_freq_div),
.reg_wr_sig(reg_wr_sig),
.reg_index (reg_wr_index)
);
reg delayer_rst_n_ctrl;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
r1_ctrl <= 32'hffff_ffff;
r2_input_delay_cnt <= 32'd100;
r3_input_delay_freq_div <= 1;
r4_output_delay_cnt <= 0;
r5_output_delay_freq_div <= 1;
delayer_rst_n_ctrl <= 1;
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)
1: begin
r1_ctrl <= wr_data;
delayer_rst_n_ctrl <= 0;
end
2: r2_input_delay_cnt <= wr_data;
3: r3_input_delay_freq_div <= wr_data;
4: r4_output_delay_cnt <= wr_data;
5: r5_output_delay_freq_div <= wr_data;
default: begin
end
endcase
end else begin
delayer_rst_n_ctrl <= 1;
end
end
end
assign delayer_rst_n = delayer_rst_n_ctrl & rst_n;
zutils_sig_delayer_v2 sig_delayer_inst (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (sync_ttl_in1),
.out (af_delay__sync_ttl_in1)
);
zutils_sig_delayer_v2 sig_delayer_inst1 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (sync_ttl_in2),
.out (af_delay__sync_ttl_in2)
);
zutils_sig_delayer_v2 sig_delayer_inst2 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (sync_ttl_in3),
.out (af_delay__sync_ttl_in3)
);
zutils_sig_delayer_v2 sig_delayer_inst3 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (sync_ttl_in4),
.out (af_delay__sync_ttl_in4)
);
zutils_sig_delayer_v2 sig_delayer_inst4 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (timecode_headphone_in),
.out (af_delay__timecode_headphone_in)
);
zutils_sig_delayer_v2 sig_delayer_inst5 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (timecode_bnc_in),
.out (af_delay__timecode_bnc_in)
);
zutils_sig_delayer_v2 sig_delayer_inst6 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (genlock_in_hsync),
.out (af_delay__genlock_in_hsync)
);
zutils_sig_delayer_v2 sig_delayer_inst7 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (genlock_in_vsync),
.out (af_delay__genlock_in_vsync)
);
zutils_sig_delayer_v2 sig_delayer_inst8 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (genlock_in_fsync),
.out (af_delay__genlock_in_fsync)
);
zutils_sig_delayer_v2 sig_delayer_inst9 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__sync_ttl_out1),
.out (sync_ttl_out1)
);
zutils_sig_delayer_v2 sig_delayer_inst10 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__sync_ttl_out2),
.out (sync_ttl_out2)
);
zutils_sig_delayer_v2 sig_delayer_inst11 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__sync_ttl_out3),
.out (sync_ttl_out3)
);
zutils_sig_delayer_v2 sig_delayer_inst12 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__sync_ttl_out4),
.out (sync_ttl_out4)
);
zutils_sig_delayer_v2 sig_delayer_inst13 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__stm32if_start_signal_out),
.out (stm32if_start_signal_out)
);
zutils_sig_delayer_v2 sig_delayer_inst14 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__stm32if_camera_sync_out),
.out (stm32if_camera_sync_out)
);
zutils_sig_delayer_v2 sig_delayer_inst15 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__stm32if_timecode_sync_out),
.out (stm32if_timecode_sync_out)
);
endmodule

129
source/src/top.v
View File

@ -109,6 +109,9 @@ module Top (
wire [31:0] rd_data_module_sys_clock; //! 模块寄存器数据总线读数据
wire [31:0] rd_data_module_record_sig_generator; //! 模块寄存器数据总线读数据
wire [31:0] rd_data_module_sys_signal_delayer; //! 模块寄存器数据总线读数据
//内部信号
wire signal_logic0; //! 逻辑0
wire signal_logic1; //! 逻辑1
@ -205,7 +208,8 @@ module Top (
.rd_data_module_sys_timecode (rd_data_module_sys_timecode),
.rd_data_module_sys_genlock (rd_data_module_sys_genlock),
.rd_data_module_sys_clock (rd_data_module_sys_clock),
.rd_data_module_record_sig_generator(rd_data_module_record_sig_generator)
.rd_data_module_record_sig_generator(rd_data_module_record_sig_generator),
.rd_data_module_sys_signal_delayer (rd_data_module_sys_signal_delayer)
);
@ -215,22 +219,22 @@ module Top (
*******************************************************************************/
zutils_register16 #(
.REG_START_ADD(`REGADDOFF__FPGA_INFO),
.REG0_INIT(1),
.REG1_INIT(2),
.REG2_INIT(3),
.REG3_INIT(4),
.REG4_INIT(5),
.REG5_INIT(6),
.REG6_INIT(7),
.REG7_INIT(8),
.REG8_INIT(9),
.REG9_INIT(10),
.REGA_INIT(11),
.REGB_INIT(12),
.REGC_INIT(13),
.REGD_INIT(14),
.REGE_INIT(15),
.REGF_INIT(16)
.REG0_INIT(0),
.REG1_INIT(0),
.REG2_INIT(0),
.REG3_INIT(0),
.REG4_INIT(0),
.REG5_INIT(0),
.REG6_INIT(0),
.REG7_INIT(0),
.REG8_INIT(0),
.REG9_INIT(0),
.REGA_INIT(0),
.REGB_INIT(0),
.REGC_INIT(0),
.REGD_INIT(0),
.REGE_INIT(0),
.REGF_INIT(0)
) test_reg (
.clk (sys_clk),
.rst_n (sys_rst_n),
@ -240,6 +244,61 @@ module Top (
.rd_data(rd_data_module_fpga_info)
);
sys_signal_delayer #(
.REG_START_ADD (`REGADDOFF__DELAYER),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) sys_signal_delayer_ins (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr (RegReaderBus_addr),
.wr_data(RegReaderBus_wr_data),
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_sys_signal_delayer),
.sync_ttl_in1 (sync_ttl_in1),
.sync_ttl_in2 (sync_ttl_in2),
.sync_ttl_in3 (sync_ttl_in3),
.sync_ttl_in4 (sync_ttl_in4),
.timecode_headphone_in(timecode_headphone_in),
.timecode_bnc_in (timecode_bnc_in),
.genlock_in_hsync (genlock_in_hsync),
.genlock_in_vsync (genlock_in_vsync),
.genlock_in_fsync (genlock_in_fsync),
.af_delay__sync_ttl_in1 (af_delay__sync_ttl_in1),
.af_delay__sync_ttl_in2 (af_delay__sync_ttl_in2),
.af_delay__sync_ttl_in3 (af_delay__sync_ttl_in3),
.af_delay__sync_ttl_in4 (af_delay__sync_ttl_in4),
.af_delay__timecode_headphone_in(af_delay__timecode_headphone_in),
.af_delay__timecode_bnc_in (af_delay__timecode_bnc_in),
.af_delay__genlock_in_hsync (af_delay__genlock_in_hsync),
.af_delay__genlock_in_vsync (af_delay__genlock_in_vsync),
.af_delay__genlock_in_fsync (af_delay__genlock_in_fsync),
.sync_ttl_out1(sync_ttl_out1),
.sync_ttl_out2(sync_ttl_out2),
.sync_ttl_out3(sync_ttl_out3),
.sync_ttl_out4(sync_ttl_out4),
.stm32if_start_signal_out (stm32if_start_signal_out),
.stm32if_camera_sync_out (stm32if_camera_sync_out),
.stm32if_timecode_sync_out(stm32if_timecode_sync_out),
.before_delay__sync_ttl_out1(before_delay__sync_ttl_out1),
.before_delay__sync_ttl_out2(before_delay__sync_ttl_out2),
.before_delay__sync_ttl_out3(before_delay__sync_ttl_out3),
.before_delay__sync_ttl_out4(before_delay__sync_ttl_out4),
.before_delay__stm32if_start_signal_out (before_delay__stm32if_start_signal_out),
.before_delay__stm32if_camera_sync_out (before_delay__stm32if_camera_sync_out),
.before_delay__stm32if_timecode_sync_out(before_delay__stm32if_timecode_sync_out)
);
/*******************************************************************************
* TTL输入模块 *
*******************************************************************************/
@ -256,10 +315,10 @@ module Top (
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_ttlin),
.ttlin1_raw(sync_ttl_in1),
.ttlin2_raw(sync_ttl_in2),
.ttlin3_raw(sync_ttl_in3),
.ttlin4_raw(!sync_ttl_in4), //in4电路上进行了反向
.ttlin1_raw(af_delay__sync_ttl_in1),
.ttlin2_raw(af_delay__sync_ttl_in2),
.ttlin3_raw(af_delay__sync_ttl_in3),
.ttlin4_raw(!af_delay__sync_ttl_in4), //in4电路上进行了反向
//指示灯
.ttlin1_state_led(sync_ttl_in1_state_led),
@ -288,8 +347,8 @@ module Top (
.rd_data(rd_data_module_timecode_in),
//input
.timecode_bnc_in (timecode_bnc_in),
.timecode_headphone_in(timecode_headphone_in),
.timecode_bnc_in (af_delay__timecode_bnc_in),
.timecode_headphone_in(af_delay__timecode_headphone_in),
//output
.timecode_tigger_sig (ext_timecode_tigger_sig),
@ -312,9 +371,9 @@ module Top (
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_genlock_in),
.genlock_in_hsync(genlock_in_hsync),
.genlock_in_vsync(genlock_in_vsync),
.genlock_in_fsync(genlock_in_fsync),
.genlock_in_hsync(af_delay__genlock_in_hsync),
.genlock_in_vsync(af_delay__genlock_in_vsync),
.genlock_in_fsync(af_delay__genlock_in_fsync),
.genlock_freq_signal (signal_ext_genlock_freq),
.genlock_in_state_led(genlock_in_state_led)
@ -462,7 +521,7 @@ module Top (
.signal_in(sig_src),
.ttloutput (sync_ttl_out1),
.ttloutput (before_delay__sync_ttl_out1),
.ttloutput_state_led(sync_ttl_out1_state_led)
);
@ -481,7 +540,7 @@ module Top (
.signal_in(sig_src),
.ttloutput (sync_ttl_out2),
.ttloutput (before_delay__sync_ttl_out2),
.ttloutput_state_led(sync_ttl_out2_state_led)
);
ttl_output #(
@ -499,7 +558,7 @@ module Top (
.signal_in(sig_src),
.ttloutput (sync_ttl_out3),
.ttloutput (before_delay__sync_ttl_out3),
.ttloutput_state_led(sync_ttl_out3_state_led)
);
@ -518,7 +577,7 @@ module Top (
.signal_in(sig_src),
.ttloutput (sync_ttl_out4),
.ttloutput (before_delay__sync_ttl_out4),
.ttloutput_state_led(sync_ttl_out4_state_led)
);
@ -535,7 +594,7 @@ module Top (
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_timecode_out),
.stm32if_timecode_tigger_sig(stm32if_timecode_sync_out),
.stm32if_timecode_tigger_sig(before_delay__stm32if_timecode_sync_out),
.in_timecode_tigger_sig (sys_timecode_tigger_sig),
.in_timecode_format (sys_timecode_format),
@ -592,14 +651,14 @@ module Top (
.frame_sig (signal_business_record_exposure_sig),
.record_en_sig(signal_business_record_en_sig),
.stm32if_camera_sync_out(stm32if_camera_sync_out),
.stm32if_record_sync_out(stm32if_start_signal_out)
.stm32if_camera_sync_out (before_delay__stm32if_camera_sync_out),
.stm32if_record_state_change_sig(before_delay__stm32if_start_signal_out)
);
assign debug_signal_output[0] = sys_clk;
assign debug_signal_output[1] = sync_ttl_in1;
assign debug_signal_output[2] = sync_ttl_in2;
assign debug_signal_output[2] = af_delay__sync_ttl_in1;
assign debug_signal_output[3] = sync_ttl_in3;
assign debug_signal_output[4] = sync_ttl_in4;
assign debug_signal_output[5] = sync_ttl_out1;

77
source/src/zutils/zutils_pluse_delayer.v
View File

@ -0,0 +1,77 @@
module zutils_pluse_delayer (
input clk, //clock input
input rst_n, //asynchronous reset input, low active
input [31:0] delay_cnt,
input wire in_sig,
output wire out_sig,
output reg gen_pulse
);
reg [31:0] cnt;
reg state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 0;
state <= 0;
gen_pulse <= 0;
end else begin
if (!state) begin
if (in_sig) begin
state <= 1;
cnt <= delay_cnt;
end
gen_pulse <= 0;
end else begin
if (cnt == 0) begin
gen_pulse <= 1;
state <= 0;
end else begin
cnt <= cnt - 1;
end
end
end
end
assign out_sig = in_sig & state & rst_n;
// always @(posedge clk or negedge rst_n) begin
// if (!rst_n) begin
// cnt <= 0;
// busy <= 0;
// out <= 0;
// state <= 0;
// end else begin
// if (handle_reset) begin
// cnt <= 0;
// busy <= 0;
// out <= 0;
// state <= 0;
// end else begin
// if (!state) begin
// if (in) begin
// state <= 1;
// cnt <= delay_cnt;
// busy <= 1;
// end
// out <= 0;
// end else begin
// if (cnt == 0) begin
// out <= 1;
// state <= 0;
// busy <= 0;
// end else begin
// cnt <= cnt - 1;
// end
// end
// end
// end
// end
endmodule

104
source/src/zutils/zutils_sig_delayer.v
View File

@ -0,0 +1,104 @@
module zutils_sig_delayer (
input clk,
input rst_n,
input [31:0] delay_cnt,
input [31:0] freq_division,
input in,
output reg out,
output reg ready
);
reg [31:0] freq_division_cache; //! freq_division 配置缓存
reg [ 1:0] state; //! 状态机状态
reg [31:0] cnt; //! 采样预分频cnt
reg shift_register_clk; //! 移位寄存器时钟
reg [ 9:0] shift_register_add; //! 移位寄存器偏移地址
reg [31:0] shift_register_freq_div_clk_cnt; //! 移位寄存器分频时钟计数
wire dout;
ShiftRegister shift1 (
.din (in),
.addr(shift_register_add),
.clk (clk),
.rst (!rst_n),
.dout(dout)
);
// assign out = dout;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
freq_division_cache <= 0;
cnt <= 0;
shift_register_clk <= 0;
shift_register_add <= 0;
out <= 0;
ready <= 0;
state <= 0;
end else begin
case (state)
0: begin
if (delay_cnt == 0) begin
shift_register_add <= 1;
end else if (delay_cnt >= 1000) begin
shift_register_add <= 1000;
end else begin
shift_register_add <= delay_cnt;
end
if (freq_division == 0) begin
freq_division_cache <= 1;
end else begin
freq_division_cache <= freq_division;
end
state <= 1;
out <= in;
end
1: begin
state <= 2;
shift_register_clk <= 1;
cnt <= 0;
end
2: begin
if (cnt == 0) begin
shift_register_clk <= 1;
cnt <= freq_division_cache;
shift_register_freq_div_clk_cnt <= shift_register_freq_div_clk_cnt + 1;
if (shift_register_freq_div_clk_cnt > shift_register_add + 1) begin
state <= 3;
end
end else begin
cnt <= cnt - 1;
shift_register_clk <= 0;
end
end
3: begin
ready <= 1;
out <= dout;
if (cnt == 0) begin
shift_register_clk <= 1;
cnt <= freq_division_cache;
end else begin
shift_register_clk <= 0;
cnt <= cnt - 1;
end
end
default: begin
state <= 0;
end
endcase
end
end
endmodule

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source/src/zutils/zutils_sig_delayer_v2.v
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//
// 波形延时器
// 特点:
// 1. 如果要延后的时间小于原始信号的周期,延时时间可随意设置。
// 2. 相比使用FIFO的方式缓存信号的方式，这个延时模块使用的资源更少。
// 3. 无法延迟非周期短时高频信号。最多缓存3个短时脉冲（缓存脉冲数量与zutils_edge_detecter的实力数量有关）
//
module zutils_sig_delayer_v2 (
input clk,
input rst_n,
input [31:0] delay_cnt,
input [31:0] freq_division,
input in,
output reg out,
output reg ready
);
reg [31:0] delay_cache;
reg internal_reset_sig;
zutils_edge_detecter _signal_in (
.clk (clk),
.rst_n (internal_reset_sig),
.in_signal (in),
.in_signal_rising_edge (in_signal_rising_edge),
.in_signal_falling_edge(in_signal_falling_edge)
);
zutils_pluse_delayer _pluse_delayer11 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (in_signal_rising_edge),
.out_sig (out_sig11),
.gen_pulse(gen_pluse11)
);
zutils_pluse_delayer _pluse_delayer12 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (out_sig11),
.out_sig (out_sig12),
.gen_pulse(gen_pluse12)
);
zutils_pluse_delayer _pluse_delayer13 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (out_sig12),
.out_sig (final_out_sig1),
.gen_pulse(gen_pluse13)
);
zutils_pluse_delayer _pluse_delayer21 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (in_signal_falling_edge),
.out_sig (out_sig21),
.gen_pulse(gen_pluse21)
);
zutils_pluse_delayer _pluse_delayer22 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (out_sig21),
.out_sig (out_sig22),
.gen_pulse(gen_pluse22)
);
zutils_pluse_delayer _pluse_delayer23 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (out_sig22),
.out_sig (final_out_sig2),
.gen_pulse(gen_pluse23)
);
assign final_gen_pluse1 = gen_pluse11 | gen_pluse12 | gen_pluse13;
assign final_gen_pluse2 = gen_pluse21 | gen_pluse22 | gen_pluse23;
reg state;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= 0;
ready <= 0;
out <= 0;
internal_reset_sig <= 0;
end else begin
case (state)
0: begin
state <= 1;
out <= in;
internal_reset_sig <= 0;
ready <= 0;
delay_cache <= delay_cnt;
end
1: begin
if (final_out_sig2 | final_out_sig1) begin
state <= 0;
ready <= 0;
out <= in;
internal_reset_sig <= 0;
end else begin
ready <= 1;
internal_reset_sig <= 1;
if (final_gen_pluse1) begin
out <= 1;
end else if (final_gen_pluse2) begin
out <= 0;
end
end
end
endcase
end
end
endmodule