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xsync_fpge
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TTLOUTPUT_OK

master
zhaohe 2 years ago
parent
9d143fb497
commit
580f4cf371
9 changed files with 432 additions and 232 deletions
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  1. 59
      README.md
  2. 120
      led_test.pds
  3. 16
      source/src/output/ttl_output.v
  4. 247
      source/src/top.v
  5. 17
      source/src/zutils/zutils_multiplexer_2t1.v
  6. 114
      source/src/zutils/zutils_multiplexer_32t1.v
  7. 1
      source/src/zutils/zutils_multiplexer_4t1.v
  8. 36
      source/src/zutils/zutils_muti_debug_signal_gen.v
  9. 54
      source/src/zutils/zutils_pluse_generator.v

59
README.md
View File

@ -18,5 +18,62 @@ define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33}
```
TTL OUTPUT
1,3,4 丝印正确，正常输出
1,2,3,4 丝印正确，正常输出
```
```
SIGNAL_GENERATOR
启动方式:
1.寄存器控制启动
2.外部触发启动
3.TIMECODE触发启动
帧格式:
TIMECODE:
25/30/...
GENLOCK:
....
产生:
1.start_state_sig (高电平表示拍照进行中)
2.timecode_sig[64]
3.timecode_tirgger_sig[1]
4.genlock_sig[1] 帧信号,场信号
5.秒信号
TTL_INPUT
TIMECODE_INPUT
TIMECODE_OUTPUT
GENLOCK_INPUT
```
```
1. 修改启动方式
2. 修改TIMECODE启动时间戳
```
```
TTL模块信号源输入
0:0
1:1
2:ttl_input1_raw
3:ttl_input1_division
4:ttl_input2_raw
5:ttl_input2_division
6:ttl_input3_raw
7:ttl_input3_division
8:genlock_frame_freq
9:timecode_trigger
10:work_state_signal
11:internal_frame_freq (genlock)
12:internal_sec_freq
```

120
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Jan 8 22:23:17 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Jan 9 15:13:07 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-01-08T22:21:53")
(_timespec "2024-01-09T14:06:30")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -27,7 +27,7 @@
)
(_file "source/src/zutils/zutils_pluse_generator.v"
(_format verilog)
(_timespec "2024-01-08T17:43:24")
(_timespec "2024-01-09T14:45:57")
)
(_file "source/src/zutils/zutils_edge_detecter.v"
(_format verilog)
@ -39,7 +39,7 @@
)
(_file "source/src/zutils/zutils_multiplexer_4t1.v"
(_format verilog)
(_timespec "2024-01-08T17:42:11")
(_timespec "2024-01-09T10:15:13")
)
(_file "source/src/zutils/zutils_debug_led.v"
(_format verilog)
@ -55,11 +55,11 @@
)
(_file "source/src/zutils/zutils_multiplexer_16t1.v"
(_format verilog)
(_timespec "2024-01-08T22:15:04")
(_timespec "2024-01-09T10:30:12")
)
(_file "source/src/output/ttl_output.v"
(_format verilog)
(_timespec "2024-01-08T22:10:21")
(_timespec "2024-01-09T11:35:46")
)
(_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog)
@ -73,6 +73,18 @@
(_format verilog)
(_timespec "2024-01-08T22:22:50")
)
(_file "source/src/zutils/zutils_multiplexer_2t1.v"
(_format verilog)
(_timespec "2024-01-09T10:38:01")
)
(_file "source/src/zutils/zutils_multiplexer_32t1.v"
(_format verilog)
(_timespec "2024-01-09T10:30:11")
)
(_file "source/src/zutils/zutils_muti_debug_signal_gen.v"
(_format verilog)
(_timespec "2024-01-09T10:38:50")
)
)
)
(_widget wgt_my_ips_src
@ -132,17 +144,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-01-08T22:22:53")
(_timespec "2024-01-09T15:12:23")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-01-08T22:22:53")
(_timespec "2024-01-09T15:12:22")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-01-08T22:22:53")
(_timespec "2024-01-09T15:12:23")
)
)
)
@ -158,21 +170,21 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-01-08T22:22:56")
(_timespec "2024-01-09T15:12:54")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-01-08T22:22:57")
(_timespec "2024-01-09T15:12:58")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-01-08T22:22:57")
(_timespec "2024-01-09T15:13:01")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-01-08T22:22:57")
(_timespec "2024-01-09T15:13:01")
)
)
)
@ -193,21 +205,21 @@
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-01-08T22:22:59")
(_timespec "2024-01-09T15:13:07")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-01-08T22:22:59")
(_timespec "2024-01-09T15:13:06")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-01-08T22:22:59")
(_timespec "2024-01-09T15:13:07")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-01-08T22:22:59")
(_timespec "2024-01-09T15:13:07")
)
)
)
@ -216,7 +228,7 @@
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-01-08T22:22:59")
(_timespec "2024-01-09T15:13:07")
)
)
)
@ -226,39 +238,7 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 2))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-01-08T22:23:07")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-01-08T22:23:07")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-01-08T22:23:07")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-01-08T22:23:07")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-01-08T22:23:05")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-01-08T22:23:07")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-01-08T22:23:08")
)
)
(_gci_state (_integer 0))
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -267,24 +247,8 @@
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 2))
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2024-01-08T22:23:11")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2024-01-08T22:23:11")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2024-01-08T22:23:11")
)
)
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
@ -302,25 +266,7 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 2))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-01-08T22:23:16")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-01-08T22:23:16")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-01-08T22:23:16")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-01-08T22:23:17")
)
)
(_gci_state (_integer 0))
)
)
)

16
source/src/output/ttl_output.v
View File

@ -19,7 +19,7 @@ module ttl_output #(
input wr_en,
output wire [31:0] rd_data,
input [7:0] signal_in,
input [31:0] signal_in,
output ttloutput, //ttl输出信号
output ttloutput_state_led //ttl输出状态信号
@ -61,6 +61,11 @@ module ttl_output #(
// 0~0xffffffff
//
wire [31:0] reg_pulse_mode_valid_len; // 脉冲模式-有效电平长度: 0~0xffffffff
//
// 脉冲模式-触发延时:
// 0~0xffffffff
//
wire [31:0] reg_pulse_mode_trigger_delay; // 脉冲模式-触发延时: 0~0xffffffff
zutils_register16 #(
@ -76,7 +81,8 @@ module ttl_output #(
.reg0(reg_input_signal_select),
.reg1(reg_output_signal_select),
.reg2(reg_config),
.reg3(reg_pulse_mode_valid_len)
.reg3(reg_pulse_mode_valid_len),
.reg4(reg_pulse_mode_trigger_delay)
);
/*******************************************************************************
@ -97,9 +103,9 @@ module ttl_output #(
assign signal_src_trigger = (pluse_input_trigger_signal==0) ? (in_signal_rising_edge) : (in_signal_falling_edge);
wire signal_in_choose;
zutils_multiplexer_16t1 _signal_select (
zutils_multiplexer_32t1 _signal_select (
.chooseindex(reg_input_signal_select),
.signal({8'b0, signal_in}),
.signal(signal_in),
.signalout(signal_in_choose)
);
@ -119,6 +125,7 @@ module ttl_output #(
.clk(clk),
.rst_n(rst_n),
.pluse_width(reg_pulse_mode_valid_len),
.pluse_delay(reg_pulse_mode_trigger_delay),
.trigger(signal_src_trigger),
.output_signal(ttl_after_process_output)
);
@ -148,6 +155,7 @@ module ttl_output #(
zutils_multiplexer_16t1 _signal_output_select (
.chooseindex(reg_output_signal_select),
.signal(signal_output_select_in),
.signalout(ttloutput)
);
// assign ttloutput_state_led = !ttloutput;

247
source/src/top.v
View File

@ -124,35 +124,6 @@ module Top (
/*******************************************************************************
* 调试器 *
*******************************************************************************/
// wire [6:0] trig0_i;
// JtagHubIst jtag_hub_ist (
// .resetn_i(sys_rst_n), // input
// .drck_o (drck_o), // output
// .hub_tdi (hub_tdi), // output
// .capt_o (capt_o), // output
// .shift_o (shift_o), // output
// .conf_sel(conf_sel), // output [14:0]
// .id_o (id_o), // output [4:0]
// .hub_tdo (hub_tdo) // input [14:0]
// );
// DebugCoreIst debug_core_ist (
// .hub_tdi (hub_tdi), // input
// .hub_tdo (hub_tdo[0]), // output
// .id_i (id_o), // input [4:0]
// .capt_i (capt_o), // input
// .shift_i (shift_o), // input
// .conf_sel(conf_sel[0]), // input
// .drck_in (drck_o), // input
// .clk (sys_clk), // input
// .resetn_i(sys_rst_n), // input
// .trig0_i (trig0_i)
// );
/*******************************************************************************
* DEBUG_LED *
*******************************************************************************/
// zutils_debug_led #(
@ -211,22 +182,22 @@ module Top (
*******************************************************************************/
zutils_register16 #(
.REG_START_ADD(`REG_ADD_OFF_FPGA_TEST),
.REG0_INIT(31'h0000_0000),
.REG1_INIT(31'h1111_1111),
.REG2_INIT(31'h2222_2222),
.REG3_INIT(31'h3333_3333),
.REG4_INIT(31'h4444_4444),
.REG5_INIT(31'h5555_5555),
.REG6_INIT(31'h6666_6666),
.REG7_INIT(31'h7777_7777),
.REG8_INIT(31'h8888_8888),
.REG9_INIT(31'h9999_9999),
.REGA_INIT(31'haaaa_aaaa),
.REGB_INIT(31'hbbbb_bbbb),
.REGC_INIT(31'hcccc_cccc),
.REGD_INIT(31'hdddd_dddd),
.REGE_INIT(31'heeee_eeee),
.REGF_INIT(31'hffff_ffff)
.REG0_INIT(31'h0000_0000_0000_0001),
.REG1_INIT(31'h0000_0000_0000_0010),
.REG2_INIT(31'h0000_0000_0000_0100),
.REG3_INIT(31'h0000_0000_0000_1000),
.REG4_INIT(31'h0000_0000_0001_0000),
.REG5_INIT(31'h0000_0000_0010_0000),
.REG6_INIT(31'h0000_0000_0100_0000),
.REG7_INIT(31'h0000_0000_1000_0000),
.REG8_INIT(31'h0000_0001_0000_0000),
.REG9_INIT(31'h0000_0010_0000_0000),
.REGA_INIT(31'h0000_0100_0000_0000),
.REGB_INIT(31'h0000_1000_0000_0000),
.REGC_INIT(31'h0001_0000_0000_0000),
.REGD_INIT(31'h0010_0000_0000_0000),
.REGE_INIT(31'h0100_0000_0000_0000),
.REGF_INIT(31'h1000_0000_0000_0000)
) test_reg (
.clk(sys_clk),
.rst_n(sys_rst_n),
@ -241,118 +212,132 @@ module Top (
* 输出组件 *
*******************************************************************************/
wire [7:0] ttl_output_signal_in;
wire [31:0] ttl_output_module_source_sig;
wire [31:0] ttl_output_module_source_sig_af;
// ttl_output #(
// .REG_START_ADD(`REG_ADD_OFF_TTLIN1),
// .TEST(HARDWARE_TEST_MODE),
// .ID(1)
// ) ttl_output_1 (
// .clk (sys_clk),
// .rst_n(sys_rst_n),
zutils_muti_debug_signal_gen ttl_sig_source (
.clk(sys_clk),
.rst_n(sys_rst_n),
// .addr(reg_reader_bus_addr),
// .wr_data(reg_reader_bus_wr_data),
// .wr_en(reg_reader_bus_wr_en),
// .rd_data(ttlout1_rd_data),
.testflag(HARDWARE_TEST_MODE),
// .signal_in(ttl_output_signal_in),
.rawsig(ttl_output_module_source_sig),
.output_signal(ttl_output_module_source_sig_af)
);
// .ttloutput(sync_ttl_out1),
// .ttloutput_state_led(sync_ttl_out1_state_led)
// );
ttl_output #(
.REG_START_ADD(`REG_ADD_OFF_TTLOUT1),
.TEST(HARDWARE_TEST_MODE),
.ID(1)
) ttl_output_1 (
.clk (sys_clk),
.rst_n(sys_rst_n),
// ttl_output #(
// .REG_START_ADD(`REG_ADD_OFF_TTLIN2),
// .TEST(HARDWARE_TEST_MODE),
// .ID(2)
// ) ttl_output_2 (
// .clk (sys_clk),
// .rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(ttlout1_rd_data),
// .addr(reg_reader_bus_addr),
// .wr_data(reg_reader_bus_wr_data),
// .wr_en(reg_reader_bus_wr_en),
// .rd_data(ttlout2_rd_data),
.signal_in(ttl_output_module_source_sig_af),
// .signal_in(ttl_output_signal_in),
.ttloutput(sync_ttl_out1),
.ttloutput_state_led(sync_ttl_out1_state_led)
);
// .ttloutput(sync_ttl_out2),
// .ttloutput_state_led(sync_ttl_out2_state_led)
// );
ttl_output #(
.REG_START_ADD(`REG_ADD_OFF_TTLOUT2),
.TEST(HARDWARE_TEST_MODE),
.ID(2)
) ttl_output_2 (
.clk (sys_clk),
.rst_n(sys_rst_n),
// ttl_output #(
// .REG_START_ADD(`REG_ADD_OFF_TTLIN3),
// .TEST(HARDWARE_TEST_MODE),
// .ID(3)
// ) ttl_output_3 (
// .clk (sys_clk),
// .rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(ttlout2_rd_data),
// .addr(reg_reader_bus_addr),
// .wr_data(reg_reader_bus_wr_data),
// .wr_en(reg_reader_bus_wr_en),
// .rd_data(ttlout3_rd_data),
.signal_in(ttl_output_module_source_sig_af),
// .signal_in(ttl_output_signal_in),
.ttloutput(sync_ttl_out2),
.ttloutput_state_led(sync_ttl_out2_state_led)
);
// .ttloutput(sync_ttl_out3),
// .ttloutput_state_led(sync_ttl_out3_state_led)
// );
ttl_output #(
.REG_START_ADD(`REG_ADD_OFF_TTLOUT3),
.TEST(HARDWARE_TEST_MODE),
.ID(3)
) ttl_output_3 (
.clk (sys_clk),
.rst_n(sys_rst_n),
// ttl_output #(
// .REG_START_ADD(`REG_ADD_OFF_TTLIN4),
// .TEST(HARDWARE_TEST_MODE),
// .ID(4)
// ) ttl_output_4 (
// .clk (sys_clk),
// .rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(ttlout3_rd_data),
// .addr(reg_reader_bus_addr),
// .wr_data(reg_reader_bus_wr_data),
// .wr_en(reg_reader_bus_wr_en),
// .rd_data(ttlout4_rd_data),
.signal_in(ttl_output_module_source_sig_af),
// .signal_in(ttl_output_signal_in),
.ttloutput(sync_ttl_out3),
.ttloutput_state_led(sync_ttl_out3_state_led)
);
// .ttloutput(sync_ttl_out4),
// .ttloutput_state_led(sync_ttl_out4_state_led)
// );
ttl_output #(
.REG_START_ADD(`REG_ADD_OFF_TTLOUT4),
.TEST(HARDWARE_TEST_MODE),
.ID(4)
) ttl_output_4 (
.clk (sys_clk),
.rst_n(sys_rst_n),
.addr(reg_reader_bus_addr),
.wr_data(reg_reader_bus_wr_data),
.wr_en(reg_reader_bus_wr_en),
.rd_data(ttlout4_rd_data),
// rd_data_router rd_data_router_inst (
// .addr(reg_reader_bus_addr),
.signal_in(ttl_output_module_source_sig_af),
// .stm32_rd_data(stm32_rd_data),
// .fpga_test_rd_data(fpga_test_rd_data),
// .control_sensor_rd_data(control_sensor_rd_data),
// .ttlin1_rd_data(ttlin1_rd_data),
// .ttlin2_rd_data(ttlin2_rd_data),
// .ttlin3_rd_data(ttlin3_rd_data),
// .ttlin4_rd_data(ttlin4_rd_data),
// .timecode_in_rd_data(timecode_in_rd_data),
// .genlock_in_rd_data(genlock_in_rd_data),
.ttloutput(sync_ttl_out4),
.ttloutput_state_led(sync_ttl_out4_state_led)
);
// .ttlout1_rd_data(ttlout1_rd_data), // ok
// .ttlout2_rd_data(ttlout2_rd_data), // ok
// .ttlout3_rd_data(ttlout3_rd_data), // ok
// .ttlout4_rd_data(ttlout4_rd_data), // ok
// .timecode_out_rd_data(timecode_out_rd_data),
// .genlock_out_rd_data(genlock_out_rd_data),
// .stm32_if_rd_data(stm32_if_rd_data),
// .debuger_rd_data(debuger_rd_data),
rd_data_router rd_data_router_inst (
.addr(reg_reader_bus_addr),
// .rd_data_out(reg_reader_bus_rd_data)
// );
assign reg_reader_bus_rd_data[31:0] = fpga_test_rd_data[31:0];
.stm32_rd_data(stm32_rd_data),
.fpga_test_rd_data(fpga_test_rd_data),
.control_sensor_rd_data(control_sensor_rd_data),
.ttlin1_rd_data(ttlin1_rd_data),
.ttlin2_rd_data(ttlin2_rd_data),
.ttlin3_rd_data(ttlin3_rd_data),
.ttlin4_rd_data(ttlin4_rd_data),
.timecode_in_rd_data(timecode_in_rd_data),
.genlock_in_rd_data(genlock_in_rd_data),
.ttlout1_rd_data(ttlout1_rd_data), // ok
.ttlout2_rd_data(ttlout2_rd_data), // ok
.ttlout3_rd_data(ttlout3_rd_data), // ok
.ttlout4_rd_data(ttlout4_rd_data), // ok
.timecode_out_rd_data(timecode_out_rd_data),
.genlock_out_rd_data(genlock_out_rd_data),
.stm32_if_rd_data(stm32_if_rd_data),
.debuger_rd_data(debuger_rd_data),
.rd_data_out(reg_reader_bus_rd_data)
);
// assign reg_reader_bus_rd_data[31:0] = fpga_test_rd_data[31:0];
assign debug_signal_output[0] = spi2_cs_pin;
assign debug_signal_output[1] = spi2_clk_pin;
assign debug_signal_output[2] = spi2_rx_pin;
assign debug_signal_output[3] = spi2_tx_pin;
assign core_board_debug_led = 1;
assign debug_signal_output[4] = sync_ttl_out1;
assign debug_signal_output[5] = sync_ttl_out2;
assign debug_signal_output[6] = sync_ttl_out3;
assign debug_signal_output[7] = sync_ttl_out4;
assign core_board_debug_led = 1;
endmodule

17
source/src/zutils/zutils_multiplexer_2t1.v
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@ -0,0 +1,17 @@
module zutils_multiplexer_2t1 (
input choose,
input wire signal0,
input wire signal1,
output reg signalout
);
always @(*) begin
case (choose)
0: begin
signalout = signal0;
end
1: begin
signalout = signal1;
end
endcase
end
endmodule

114
source/src/zutils/zutils_multiplexer_32t1.v
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@ -0,0 +1,114 @@
module zutils_multiplexer_32t1 (
input [31:0] chooseindex,
input wire [31:0] signal,
output reg signalout
);
always @(*) begin
case (chooseindex)
0: begin
signalout = signal[0];
end
1: begin
signalout = signal[1];
end
2: begin
signalout = signal[2];
end
3: begin
signalout = signal[3];
end
4: begin
signalout = signal[4];
end
5: begin
signalout = signal[5];
end
6: begin
signalout = signal[6];
end
7: begin
signalout = signal[7];
end
8: begin
signalout = signal[8];
end
9: begin
signalout = signal[9];
end
10: begin
signalout = signal[10];
end
11: begin
signalout = signal[11];
end
12: begin
signalout = signal[12];
end
13: begin
signalout = signal[13];
end
14: begin
signalout = signal[14];
end
15: begin
signalout = signal[15];
end
16: begin
signalout = signal[16];
end
17: begin
signalout = signal[17];
end
18: begin
signalout = signal[18];
end
19: begin
signalout = signal[19];
end
20: begin
signalout = signal[20];
end
21: begin
signalout = signal[21];
end
22: begin
signalout = signal[22];
end
23: begin
signalout = signal[23];
end
24: begin
signalout = signal[24];
end
25: begin
signalout = signal[25];
end
26: begin
signalout = signal[26];
end
27: begin
signalout = signal[27];
end
28: begin
signalout = signal[28];
end
29: begin
signalout = signal[29];
end
30: begin
signalout = signal[30];
end
31: begin
signalout = signal[31];
end
default: begin
signalout = 0;
end
endcase
end
endmodule

1
source/src/zutils/zutils_multiplexer_4t1.v
View File

@ -7,7 +7,6 @@ module zutils_multiplexer_4t1 (
output reg signalout
);
initial signalout = 0;
always @(*) begin
case (chooseindex)

36
source/src/zutils/zutils_muti_debug_signal_gen.v
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@ -0,0 +1,36 @@
module zutils_muti_debug_signal_gen #(
parameter SYS_CLOCK_FREQ = 50000000
) (
input clk,
input rst_n,
input testflag,
input [31:0] rawsig,
output wire [31:0] output_signal
);
wire [31:0] output_debug_signal;
genvar gv_i;
generate
for (gv_i = 0; gv_i < 32; gv_i = gv_i + 1) begin
zutils_pwm_generator #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ((gv_i + 1) * 100)
) pwm_gen (
.clk(clk),
.rst_n(rst_n),
.output_signal(output_debug_signal[gv_i])
);
zutils_multiplexer_2t1 mux (
.choose(testflag),
.signal0(rawsig[gv_i]),
.signal1(output_debug_signal[gv_i]),
.signalout(output_signal[gv_i])
);
end
endgenerate
endmodule

54
source/src/zutils/zutils_pluse_generator.v
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@ -1,15 +1,41 @@
module zutils_pluse_generator (
module zutils_pluse_generator #(
parameter SYS_CLOCK_FREQ = 50000000
) (
input clk, //clock input
input rst_n, //asynchronous reset input, low active
input wire [31:0] pluse_width,
input wire [31:0] pluse_delay,
input wire trigger,
output reg output_signal
);
initial output_signal = 0;
localparam INTER_CLK_COUNT_MAX = SYS_CLOCK_FREQ / 1000000; //1MHZ
reg [31:0] inter_clk_count;
assign clk_1mhz = (inter_clk_count == INTER_CLK_COUNT_MAX);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
inter_clk_count <= 0;
end else begin
if (inter_clk_count < INTER_CLK_COUNT_MAX) begin
inter_clk_count <= inter_clk_count + 1;
end else begin
inter_clk_count <= 0;
end
end
end
reg [31:0] counter = 0;
reg [31:0] tohigh_count = 0;
reg [31:0] counter_init_count = 0;
always @(*) begin
tohigh_count <= pluse_width;
counter_init_count <= pluse_width + pluse_delay;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
@ -17,15 +43,27 @@ module zutils_pluse_generator (
output_signal <= 0;
end else begin
if (trigger) begin
counter <= pluse_width;
output_signal <= 1;
counter <= counter_init_count;
output_signal <= 0;
end else begin
if (counter == 0) begin
output_signal <= 0;
if (counter != 0) begin
if (clk_1mhz) begin
counter <= counter - 1;
if (counter == tohigh_count) begin
output_signal <= 1;
end
end else begin
output_signal <= output_signal;
counter <= counter;
end
end else begin
counter <= counter - 1;
output_signal <= 0;
counter <= 0;
end
end
end
end
endmodule