diff --git a/led_test.fdc b/led_test.fdc
index 6dd4b39..f805e77 100644
--- a/led_test.fdc
+++ b/led_test.fdc
@@ -550,6 +550,6 @@ define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_STANDARD} {LVCMOS33}
 define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_DRIVE} {4}
 define_attribute {p:timecode_bnc_in_state_led} {PAP_IO_SLEW} {SLOW}
 define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT}
-define_attribute {p:rst_n} {PAP_IO_LOC} {G13}
+define_attribute {p:rst_n} {PAP_IO_LOC} {M16}
 define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3}
 define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33}
diff --git a/led_test.pds b/led_test.pds
index d71ee44..1de081d 100644
--- a/led_test.pds
+++ b/led_test.pds
@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Jan  8 16:51:44 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Jan  8 17:03:12 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -17,77 +17,45 @@
         )
         (_widget wgt_my_design_src
             (_input
-                (_file "source/src/transmitter.v"
-                    (_format verilog)
-                    (_timespec "2023-12-14T15:23:21")
-                )
-                (_file "source/src/baud_rate_gen.v"
-                    (_format verilog)
-                    (_timespec "2023-12-13T15:21:23")
-                )
                 (_file "source/src/top.v" + "Top:"
                     (_format verilog)
                     (_timespec "2024-01-08T16:08:57")
                 )
-                (_file "source/src/uart_tx.v"
-                    (_format verilog)
-                    (_timespec "2017-08-01T15:37:24")
-                )
-                (_file "source/src/uart_rx.v"
-                    (_format verilog)
-                    (_timespec "2023-12-13T10:31:56")
-                )
-                (_file "source/src/uart_reg_reader.v"
-                    (_format verilog)
-                    (_timespec "2023-12-15T09:32:26")
-                )
-                (_file "source/src/monitor_line.v"
-                    (_format verilog)
-                    (_timespec "2023-12-14T21:44:03")
-                )
                 (_file "source/src/spi_reg_reader.v"
                     (_format verilog)
-                    (_timespec "2024-01-08T15:19:56")
-                )
-                (_file "source/src/src_ttl_parser.v"
-                    (_format verilog)
-                    (_timespec "2024-01-08T14:55:25")
-                )
-                (_file "source/src/src_timecode.v"
-                    (_format verilog)
-                    (_timespec "2024-01-08T14:55:20")
+                    (_timespec "2024-01-08T17:03:05")
                 )
                 (_file "source/src/zutils/zutils_pluse_generator.v"
                     (_format verilog)
-                    (_timespec "2023-12-31T16:28:46")
+                    (_timespec "2024-01-08T16:56:59")
                 )
                 (_file "source/src/zutils/zutils_edge_detecter.v"
                     (_format verilog)
-                    (_timespec "2023-12-31T16:39:25")
+                    (_timespec "2024-01-08T16:56:16")
                 )
                 (_file "source/src/zutils/zutils_register.v"
                     (_format verilog)
-                    (_timespec "2024-01-08T14:54:46")
+                    (_timespec "2024-01-08T16:58:13")
                 )
                 (_file "source/src/zutils/zutils_multiplexer_4t1.v"
                     (_format verilog)
-                    (_timespec "2024-01-08T12:37:43")
+                    (_timespec "2024-01-08T16:56:29")
                 )
                 (_file "source/src/zutils/zutils_debug_led.v"
                     (_format verilog)
-                    (_timespec "2024-01-06T19:12:28")
+                    (_timespec "2024-01-08T16:55:37")
                 )
                 (_file "source/src/zutils/zutils_signal_filter.v"
                     (_format verilog)
-                    (_timespec "2024-01-07T18:57:38")
+                    (_timespec "2024-01-08T16:58:37")
                 )
                 (_file "source/src/zutils/zutils_clk_parser.v"
                     (_format verilog)
-                    (_timespec "2024-01-07T18:36:41")
+                    (_timespec "2024-01-08T16:55:21")
                 )
                 (_file "source/src/zutils/zutils_multiplexer_16t1.v"
                     (_format verilog)
-                    (_timespec "2024-01-08T12:43:05")
+                    (_timespec "2024-01-08T16:56:42")
                 )
                 (_file "source/src/output/ttl_output.v"
                     (_format verilog)
@@ -95,11 +63,11 @@
                 )
                 (_file "source/src/zutils/zutils_pwm_generator.v"
                     (_format verilog)
-                    (_timespec "2024-01-08T10:07:08")
+                    (_timespec "2024-01-08T16:57:17")
                 )
                 (_file "source/src/rd_data_router.v"
                     (_format verilog)
-                    (_timespec "2024-01-08T15:00:24")
+                    (_timespec "2024-01-08T17:01:42")
                 )
             )
         )
@@ -117,7 +85,7 @@
             (_input
                 (_file "led_test.fdc"
                     (_format fdc)
-                    (_timespec "2024-01-08T16:41:31")
+                    (_timespec "2024-01-08T16:54:45")
                 )
             )
         )
@@ -160,17 +128,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-01-08T16:51:24")
+                    (_timespec "2024-01-08T17:03:12")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-01-08T16:51:23")
+                    (_timespec "2024-01-08T17:03:11")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-01-08T16:51:24")
+                    (_timespec "2024-01-08T17:03:12")
                 )
             )
         )
@@ -180,29 +148,9 @@
     )
     (_task tsk_synthesis
         (_command cmd_synthesize
-            (_gci_state (_integer 2))
+            (_gci_state (_integer 0))
             (_option ads (_switch ON))
             (_option selected_syn_tool_opt (_integer 2))
-            (_db_output
-                (_file "synthesize/Top_syn.adf"
-                    (_format adif)
-                    (_timespec "2024-01-08T16:51:27")
-                )
-            )
-            (_output
-                (_file "synthesize/Top_syn.vm"
-                    (_format structural_verilog)
-                    (_timespec "2024-01-08T16:51:27")
-                )
-                (_file "synthesize/Top.snr"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:27")
-                )
-                (_file "synthesize/snr.db"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:27")
-                )
-            )
         )
         (_widget wgt_tech_view
             (_attribute _click_to_run (_switch ON))
@@ -217,27 +165,7 @@
     )
     (_task tsk_devmap
         (_command cmd_devmap
-            (_gci_state (_integer 2))
-            (_db_output
-                (_file "device_map/Top_map.adf"
-                    (_format adif)
-                    (_timespec "2024-01-08T16:51:29")
-                )
-            )
-            (_output
-                (_file "device_map/Top_dmr.prt"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:29")
-                )
-                (_file "device_map/Top.dmr"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:29")
-                )
-                (_file "device_map/dmr.db"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:29")
-                )
-            )
+            (_gci_state (_integer 0))
         )
         (_widget wgt_edit_placement_cons
             (_attribute _click_to_run (_switch ON))
@@ -254,39 +182,7 @@
     )
     (_task tsk_pnr
         (_command cmd_pnr
-            (_gci_state (_integer 2))
-            (_db_output
-                (_file "place_route/Top_pnr.adf"
-                    (_format adif)
-                    (_timespec "2024-01-08T16:51:35")
-                )
-            )
-            (_output
-                (_file "place_route/Top.prr"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:35")
-                )
-                (_file "place_route/Top_prr.prt"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:35")
-                )
-                (_file "place_route/clock_utilization.txt"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:35")
-                )
-                (_file "place_route/Top_plc.adf"
-                    (_format adif)
-                    (_timespec "2024-01-08T16:51:34")
-                )
-                (_file "place_route/Top_pnr.netlist"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:35")
-                )
-                (_file "place_route/prr.db"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:35")
-                )
-            )
+            (_gci_state (_integer 0))
         )
         (_widget wgt_power_calculator
             (_attribute _click_to_run (_switch ON))
@@ -295,24 +191,8 @@
             (_attribute _click_to_run (_switch ON))
         )
         (_command cmd_report_post_pnr_timing
-            (_gci_state (_integer 2))
+            (_gci_state (_integer 0))
             (_attribute _auto_exe_lock (_switch OFF))
-            (_db_output
-                (_file "report_timing/Top_rtp.adf"
-                    (_format adif)
-                    (_timespec "2024-01-08T16:51:38")
-                )
-            )
-            (_output
-                (_file "report_timing/Top.rtr"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:38")
-                )
-                (_file "report_timing/rtr.db"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:38")
-                )
-            )
         )
         (_widget wgt_arch_browser
             (_attribute _click_to_run (_switch ON))
@@ -330,25 +210,7 @@
     )
     (_task tsk_gen_bitstream
         (_command cmd_gen_bitstream
-            (_gci_state (_integer 2))
-            (_output
-                (_file "generate_bitstream/Top.sbit"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:43")
-                )
-                (_file "generate_bitstream/Top.smsk"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:43")
-                )
-                (_file "generate_bitstream/Top.bgr"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:43")
-                )
-                (_file "generate_bitstream/bgr.db"
-                    (_format text)
-                    (_timespec "2024-01-08T16:51:44")
-                )
-            )
+            (_gci_state (_integer 0))
         )
     )
 )
diff --git a/source/src/src_genlock.v b/source/src/input/src_genlock.v
similarity index 100%
rename from source/src/src_genlock.v
rename to source/src/input/src_genlock.v
diff --git a/source/src/src_timecode.v b/source/src/input/src_timecode.v
similarity index 100%
rename from source/src/src_timecode.v
rename to source/src/input/src_timecode.v
diff --git a/source/src/src_ttl_parser.v b/source/src/input/src_ttl_parser.v
similarity index 100%
rename from source/src/src_ttl_parser.v
rename to source/src/input/src_ttl_parser.v
diff --git a/source/src/monitor_line.v b/source/src/monitor_line.v
deleted file mode 100644
index c71536d..0000000
--- a/source/src/monitor_line.v
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud
- * rx/tx pair where the rx clcken oversamples by 16x.
- */
-module monitor_line (
-    input  wire clk_50m,
-    input  wire rst_n,
-    input  wire in,
-    output reg out
-);
-
-
-  always @(posedge clk_50m or negedge rst_n) begin
-    if (!rst_n) out <= 1'b0;
-    else out <= in;
-  end
-
-endmodule
diff --git a/source/src/rd_data_router.v b/source/src/rd_data_router.v
index 2151ba3..87c8367 100644
--- a/source/src/rd_data_router.v
+++ b/source/src/rd_data_router.v
@@ -24,10 +24,10 @@ module rd_data_router (
     input [31:0] stm32_if_rd_data,
     input [31:0] debuger_rd_data,
 
-    output reg [31:0] rd_data_out
+    output [31:0] rd_data_out
 );
 
-
+  reg [31:0] rd_data_out = 0;
 
   always @(*) begin
     case (addr >> 8)
diff --git a/source/src/spi_reg_reader.v b/source/src/spi_reg_reader.v
index cd31ceb..13ce26f 100644
--- a/source/src/spi_reg_reader.v
+++ b/source/src/spi_reg_reader.v
@@ -3,15 +3,15 @@ module spi_reg_reader (
     input rst_n, //asynchronous reset input, low active
 
     //regbus interface
-    output reg  [31:0] addr,
-    output reg  [31:0] wr_data,
-    output reg         wr_en,
+    output      [31:0] addr,
+    output      [31:0] wr_data,
+    output             wr_en,
     input  wire [31:0] rd_data,      //received serial data 
     //
     input  wire        spi_cs_pin,   //
     input  wire        spi_clk_pin,  //
     input  wire        spi_rx_pin,   //
-    output reg         spi_tx_pin
+    output             spi_tx_pin
 );
 
   parameter STATE_IDLE = 0;
@@ -22,6 +22,12 @@ module spi_reg_reader (
   parameter STATE_WRITE_REG = 5;
   parameter ADDRESS_WIDTH_BYTE_NUM = 2;
 
+  reg [31:0] addr = 0;
+  reg [31:0] wr_data = 0;
+  reg        wr_en = 0;
+  reg        spi_tx_pin = 0;
+
+
   zutils_signal_filter #(
       .FILTER_COUNT(5)
   ) cs_filter (
@@ -144,7 +150,7 @@ module spi_reg_reader (
   /*******************************************************************************
  *                              缓存接收到的数据                               *
  *******************************************************************************/
-  reg [7:0] spi_rx_data_cache[0:7];
+  reg [7:0] spi_rx_data_cache[0:7] = 0;
   genvar i;
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n || spi_cs_pin_after_filter) begin
diff --git a/source/src/transmitter.v b/source/src/transmitter.v
deleted file mode 100644
index bb87654..0000000
--- a/source/src/transmitter.v
+++ /dev/null
@@ -1,76 +0,0 @@
-module transmitter (
-    input wire [7:0] din,
-    input wire wr_en,
-    input wire clk_50m,
-    input wire clken,
-    input wire rest_n,
-    output reg tx,
-    output wire tx_busy,
-    output wire [1:0] t_state,
-    output wire [2:0] t_bitpos,
-    output wire t_worksignal
-);
-  parameter STATE_IDLE = 2'b00;
-  parameter STATE_START = 2'b01;
-  parameter STATE_DATA = 2'b10;
-  parameter STATE_STOP = 2'b11;
-  initial begin
-    tx = 1'b1;
-  end
-
-
-  reg [7:0] data = 8'h00;
-  reg [2:0] bitpos = 3'h0;
-  reg [1:0] state = STATE_IDLE;
-  reg worksignal = 0;
-
-  assign workflag = (state != STATE_IDLE);
-
-  always @(posedge clken, posedge wr_en) begin
-    if (wr_en) begin
-      worksignal <= 1'b1;
-      data <= din;
-    end else begin
-      if (!workflag) worksignal <= 1'b0;
-    end
-  end
-
-
-  always @(posedge clken or negedge rest_n) begin
-    if (!rest_n) begin
-      state <= STATE_IDLE;
-    end else begin
-      case (state)
-        STATE_IDLE: begin
-          tx <= 1'b1;
-          if (worksignal) begin
-            state  <= STATE_START;
-            bitpos <= 0;
-          end
-        end
-        STATE_START: begin
-          tx <= 1'b0;
-          state <= STATE_DATA;
-        end
-        STATE_DATA: begin
-          if (bitpos == 3'h7) state <= STATE_STOP;
-          else bitpos <= bitpos + 3'h1;
-          tx <= data[bitpos];
-        end
-        STATE_STOP: begin
-          tx <= 1'b1;
-          state <= STATE_IDLE;
-        end
-        default begin
-          tx <= 1'b1;
-          state <= STATE_IDLE;
-        end
-      endcase
-    end
-  end
-
-  assign tx_busy = (state != STATE_IDLE);
-  assign t_state = state;
-  assign t_bitpos = bitpos;
-  assign t_worksignal = worksignal;
-endmodule
diff --git a/source/src/uart_reg_reader.v b/source/src/uart_reg_reader.v
deleted file mode 100644
index 56ede04..0000000
--- a/source/src/uart_reg_reader.v
+++ /dev/null
@@ -1,157 +0,0 @@
-module uart_reg_reader #(
-    parameter CLK_FRE   = 50,     //clock frequency(Mhz)
-    parameter BAUD_RATE = 115200  //serial baud rate
-) (
-    input              clk,            //clock input
-    input              rst_n,          //asynchronous reset input, low active
-    input  wire [31:0] reg_data,       //received serial data 
-    output reg  [31:0] reg_add,
-    output reg         reg_add_valid,
-    input  wire        uart_rx_pin,
-    output wire        uart_tx_pin
-);
-  //
-  //           overtime
-  //   |----------------------^
-  //   v                      | 
-  //  IDLE ---------------> READ REG ADD  --------------->  READ_REG ---------------> SEND_REG_DATA
-  //  ^                                                                                    |
-  //  |------------------------------------------------------------------------------------v
-  //
-  //    
-  //
-  //
-  parameter STATE_IDLE = 0;
-  parameter STATE_READ_REG_ADD = 1;
-  parameter STATE_READ_REG = 2;
-  parameter STATE_SEND_REG_DATA = 3;
-  parameter STATE_WAIT_SEND_END = 4;
-
-  wire [7:0] rx_data;
-  wire       rx_data_valid;
-  wire       rx_data_ready;
-
-  wire       tx_data_ready;
-  reg  [7:0] tx_data = 0;
-  reg        tx_data_valid = 0;
-
-  reg  [7:0] state = 0;
-  reg  [7:0] rxpacket_num = 0;
-  reg  [7:0] txpacket_num = 0;
-  reg  [7:0] rxdatacache = 0;  //接收数据buffer
-
-  uart_rx #(
-      .CLK_FRE  (CLK_FRE),
-      .BAUD_RATE(BAUD_RATE)
-  ) uart_rx_impl (
-      .clk          (clk),            // input
-      .rst_n        (rst_n),          // input
-      .rx_data      (rx_data),        // output
-      .rx_data_valid(rx_data_valid),  // output
-      .rx_data_ready(rx_data_ready),  // input
-      .rx_pin       (uart_rx_pin)     // input
-  );
-
-  uart_tx #(
-      .CLK_FRE  (CLK_FRE),
-      .BAUD_RATE(BAUD_RATE)
-  ) uart_tx_impl (
-      .clk          (clk),            // input
-      .rst_n        (rst_n),          // input
-      .tx_data      (tx_data),        // input
-      .tx_data_valid(tx_data_valid),  // input
-      .tx_data_ready(tx_data_ready),  // output
-      .tx_pin       (uart_tx_pin)     // output
-  );
-
-
-  assign rx_data_ready = 1'b1;
-  reg [ 7:0] substep = 0;
-  reg [31:0] reg_data_cache = 0;
-
-
-  always @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      state <= STATE_IDLE;
-      rxpacket_num <= 0;
-      txpacket_num <= 0;
-      substep <= 0;
-      reg_add <= 0;
-      reg_add_valid <= 0;
-    end else begin
-      case (state)
-        STATE_IDLE: begin
-          rxpacket_num <= 0;
-          txpacket_num <= 0;
-          substep <= 0;
-          state <= STATE_READ_REG_ADD;
-        end
-        STATE_READ_REG_ADD: begin
-          if (rxpacket_num == 1) begin
-            state <= STATE_READ_REG;
-          end else if (rx_data_valid) begin
-            rxdatacache  <= rx_data;
-            rxpacket_num <= rxpacket_num + 1;
-          end
-        end
-        STATE_READ_REG: begin
-          case (substep)
-            0: begin
-              reg_add_valid <= 1;
-              reg_add[7:0] <= rxdatacache;
-              substep <= 1;
-            end
-            1: begin
-              tx_data_valid <= 0;
-              substep <= 0;
-              state <= STATE_SEND_REG_DATA;
-            end
-          endcase
-        end
-        STATE_SEND_REG_DATA: begin
-          case (substep)
-            0: begin
-              case (txpacket_num)
-                0: begin
-                  tx_data[7:0] <= reg_data_cache[7:0];
-                end
-                1: begin
-                  tx_data[7:0] <= reg_data_cache[15:8];
-                end
-                2: begin
-                  tx_data[7:0] <= reg_data_cache[23:16];
-                end
-                3: begin
-                  tx_data[7:0] <= reg_data_cache[31:24];
-                end
-                default: begin
-                  tx_data[7:0] <= 0;
-                end
-              endcase
-              tx_data_valid <= 1;
-              txpacket_num <= txpacket_num + 1;
-              substep <= 1;
-            end
-            1: begin
-              tx_data_valid <= 0;
-              substep <= 2;
-            end
-            2: begin
-              if (tx_data_ready) begin
-                if (txpacket_num != 4) begin
-                  substep <= 0;
-                end else begin
-                  substep <= 0;
-                  state   <= STATE_IDLE;
-                end
-              end
-            end
-          endcase
-        end
-        default begin
-          state <= STATE_IDLE;
-        end
-      endcase
-    end
-  end
-endmodule
diff --git a/source/src/uart_rx.v b/source/src/uart_rx.v
deleted file mode 100644
index 46abd40..0000000
--- a/source/src/uart_rx.v
+++ /dev/null
@@ -1,172 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////////
-//                                                                              //
-//                                                                              //
-//  Author: meisq                                                               //
-//          msq@qq.com                                                          //
-//          ALINX(shanghai) Technology Co.,Ltd                                  //
-//          heijin                                                              //
-//     WEB: http://www.alinx.cn/                                                //
-//     BBS: http://www.heijin.org/                                              //
-//                                                                              //
-//////////////////////////////////////////////////////////////////////////////////
-//                                                                              //
-// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd                        //
-//                    All rights reserved                                       //
-//                                                                              //
-// This source file may be used and distributed without restriction provided    //
-// that this copyright statement is not removed from the file and that any      //
-// derivative work contains the original copyright notice and the associated    //
-// disclaimer.                                                                  //
-//                                                                              //
-//////////////////////////////////////////////////////////////////////////////////
-
-//================================================================================
-//  Revision History:
-//  Date          By            Revision    Change Description
-//--------------------------------------------------------------------------------
-//2017/8/1                    1.0          Original
-//*******************************************************************************/
-module uart_rx
-       #(
-         parameter CLK_FRE = 50,      //clock frequency(Mhz)
-         parameter BAUD_RATE = 115200 //serial baud rate
-       )
-       (
-         input                        clk,              //clock input
-         input                        rst_n,            //asynchronous reset input, low active
-         output reg[7:0]              rx_data,          //received serial data
-         output reg                   rx_data_valid,    //received serial data is valid
-         input                        rx_data_ready,    //data receiver module ready
-         input                        rx_pin            //serial data input
-       );
-//calculates the clock cycle for baud rate
-localparam                       CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
-//state machine code
-localparam                       S_IDLE      = 1;
-localparam                       S_START     = 2; //start bit
-localparam                       S_REC_BYTE  = 3; //data bits
-localparam                       S_STOP      = 4; //stop bit
-localparam                       S_DATA      = 5;
-
-reg[2:0]                         state;
-reg[2:0]                         next_state;
-reg                              rx_d0;            //delay 1 clock for rx_pin
-reg                              rx_d1;            //delay 1 clock for rx_d0
-wire rx_negedge;       //negedge of rx_pin
-reg[7:0]                         rx_bits;          //temporary storage of received data
-reg[15:0]                        cycle_cnt;        //baud counter
-reg[2:0]                         bit_cnt;          //bit counter
-
-assign
-  rx_negedge = rx_d1 && ~rx_d0;
-
-always@(posedge clk or negedge rst_n)
-  begin
-    if(rst_n == 1'b0)
-      begin
-        rx_d0 <= 1'b0;
-        rx_d1 <= 1'b0;
-      end
-    else
-      begin
-        rx_d0 <= rx_pin;
-        rx_d1 <= rx_d0;
-      end
-  end
-
-
-always@(posedge clk or negedge rst_n)
-  begin
-    if(rst_n == 1'b0)
-      state <= S_IDLE;
-    else
-      state <= next_state;
-  end
-
-always@(*)
-  begin
-    case(state)
-      S_IDLE:
-        if(rx_negedge)
-          next_state <= S_START;
-        else
-          next_state <= S_IDLE;
-      S_START:
-        if(cycle_cnt == CYCLE - 1)//one data cycle
-          next_state <= S_REC_BYTE;
-        else
-          next_state <= S_START;
-      S_REC_BYTE:
-        if(cycle_cnt == CYCLE - 1  && bit_cnt == 3'd7)  //receive 8bit data
-          next_state <= S_STOP;
-        else
-          next_state <= S_REC_BYTE;
-      S_STOP:
-        if(cycle_cnt == CYCLE/2 - 1)//half bit cycle,to avoid missing the next byte receiver
-          next_state <= S_DATA;
-        else
-          next_state <= S_STOP;
-      S_DATA:
-        if(rx_data_ready)    //data receive complete
-          next_state <= S_IDLE;
-        else
-          next_state <= S_DATA;
-      default:
-        next_state <= S_IDLE;
-    endcase
-  end
-
-always@(posedge clk or negedge rst_n)
-  begin
-    if(rst_n == 1'b0)
-      rx_data_valid <= 1'b0;
-    else if(state == S_STOP && next_state != state)
-      rx_data_valid <= 1'b1;
-    else if(state == S_DATA && rx_data_ready)
-      rx_data_valid <= 1'b0;
-  end
-
-always@(posedge clk or negedge rst_n)
-  begin
-    if(rst_n == 1'b0)
-      rx_data <= 8'd0;
-    else if(state == S_STOP && next_state != state)
-      rx_data <= rx_bits;//latch received data
-  end
-
-always@(posedge clk or negedge rst_n)
-  begin
-    if(rst_n == 1'b0)
-      begin
-        bit_cnt <= 3'd0;
-      end
-    else if(state == S_REC_BYTE)
-      if(cycle_cnt == CYCLE - 1)
-        bit_cnt <= bit_cnt + 3'd1;
-      else
-        bit_cnt <= bit_cnt;
-    else
-      bit_cnt <= 3'd0;
-  end
-
-
-always@(posedge clk or negedge rst_n)
-  begin
-    if(rst_n == 1'b0)
-      cycle_cnt <= 16'd0;
-    else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
-      cycle_cnt <= 16'd0;
-    else
-      cycle_cnt <= cycle_cnt + 16'd1;
-  end
-//receive serial data bit data
-always@(posedge clk or negedge rst_n)
-  begin
-    if(rst_n == 1'b0)
-      rx_bits <= 8'd0;
-    else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1)
-      rx_bits[bit_cnt] <= rx_pin;
-    else
-      rx_bits <= rx_bits;
-  end
-endmodule
diff --git a/source/src/uart_tx.v b/source/src/uart_tx.v
deleted file mode 100644
index 08cff05..0000000
--- a/source/src/uart_tx.v
+++ /dev/null
@@ -1,161 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////////
-//                                                                              //
-//                                                                              //
-//  Author: meisq                                                               //
-//          msq@qq.com                                                          //
-//          ALINX(shanghai) Technology Co.,Ltd                                  //
-//          heijin                                                              //
-//     WEB: http://www.alinx.cn/                                                //
-//     BBS: http://www.heijin.org/                                              //
-//                                                                              //
-//////////////////////////////////////////////////////////////////////////////////
-//                                                                              //
-// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd                        //
-//                    All rights reserved                                       //
-//                                                                              //
-// This source file may be used and distributed without restriction provided    //
-// that this copyright statement is not removed from the file and that any      //
-// derivative work contains the original copyright notice and the associated    //
-// disclaimer.                                                                  //
-//                                                                              //
-//////////////////////////////////////////////////////////////////////////////////
-
-//================================================================================
-//  Revision History:
-//  Date          By            Revision    Change Description
-//--------------------------------------------------------------------------------
-//2017/8/1                    1.0          Original
-//*******************************************************************************/
-module uart_tx
-#(
-	parameter CLK_FRE = 50,      //clock frequency(Mhz)
-	parameter BAUD_RATE = 115200 //serial baud rate
-)
-(
-	input                        clk,              //clock input
-	input                        rst_n,            //asynchronous reset input, low active 
-	input[7:0]                   tx_data,          //data to send
-	input                        tx_data_valid,    //data to be sent is valid
-	output reg                   tx_data_ready,    //send ready
-	output                       tx_pin            //serial data output
-);
-//calculates the clock cycle for baud rate 
-localparam                       CYCLE = CLK_FRE * 1000000 / BAUD_RATE;
-//state machine code
-localparam                       S_IDLE       = 1;
-localparam                       S_START      = 2;//start bit
-localparam                       S_SEND_BYTE  = 3;//data bits
-localparam                       S_STOP       = 4;//stop bit
-reg[2:0]                         state;
-reg[2:0]                         next_state;
-reg[15:0]                        cycle_cnt; //baud counter
-reg[2:0]                         bit_cnt;//bit counter
-reg[7:0]                         tx_data_latch; //latch data to send
-reg                              tx_reg; //serial data output
-assign tx_pin = tx_reg;
-always@(posedge clk or negedge rst_n)
-begin
-	if(rst_n == 1'b0)
-		state <= S_IDLE;
-	else
-		state <= next_state;
-end
-
-always@(*)
-begin
-	case(state)
-		S_IDLE:
-			if(tx_data_valid == 1'b1)
-				next_state <= S_START;
-			else
-				next_state <= S_IDLE;
-		S_START:
-			if(cycle_cnt == CYCLE - 1)
-				next_state <= S_SEND_BYTE;
-			else
-				next_state <= S_START;
-		S_SEND_BYTE:
-			if(cycle_cnt == CYCLE - 1  && bit_cnt == 3'd7)
-				next_state <= S_STOP;
-			else
-				next_state <= S_SEND_BYTE;
-		S_STOP:
-			if(cycle_cnt == CYCLE - 1)
-				next_state <= S_IDLE;
-			else
-				next_state <= S_STOP;
-		default:
-			next_state <= S_IDLE;
-	endcase
-end
-always@(posedge clk or negedge rst_n)
-begin
-	if(rst_n == 1'b0)
-		begin
-			tx_data_ready <= 1'b0;
-		end
-	else if(state == S_IDLE)
-		if(tx_data_valid == 1'b1)
-			tx_data_ready <= 1'b0;
-		else
-			tx_data_ready <= 1'b1;
-	else if(state == S_STOP && cycle_cnt == CYCLE - 1)
-			tx_data_ready <= 1'b1;
-end
-
-
-always@(posedge clk or negedge rst_n)
-begin
-	if(rst_n == 1'b0)
-		begin
-			tx_data_latch <= 8'd0;
-		end
-	else if(state == S_IDLE && tx_data_valid == 1'b1)
-			tx_data_latch <= tx_data;
-		
-end
-
-always@(posedge clk or negedge rst_n)
-begin
-	if(rst_n == 1'b0)
-		begin
-			bit_cnt <= 3'd0;
-		end
-	else if(state == S_SEND_BYTE)
-		if(cycle_cnt == CYCLE - 1)
-			bit_cnt <= bit_cnt + 3'd1;
-		else
-			bit_cnt <= bit_cnt;
-	else
-		bit_cnt <= 3'd0;
-end
-
-
-always@(posedge clk or negedge rst_n)
-begin
-	if(rst_n == 1'b0)
-		cycle_cnt <= 16'd0;
-	else if((state == S_SEND_BYTE && cycle_cnt == CYCLE - 1) || next_state != state)
-		cycle_cnt <= 16'd0;
-	else
-		cycle_cnt <= cycle_cnt + 16'd1;	
-end
-
-always@(posedge clk or negedge rst_n)
-begin
-	if(rst_n == 1'b0)
-		tx_reg <= 1'b1;
-	else
-		case(state)
-			S_IDLE,S_STOP:
-				tx_reg <= 1'b1; 
-			S_START:
-				tx_reg <= 1'b0; 
-			S_SEND_BYTE:
-				tx_reg <= tx_data_latch[bit_cnt];
-			default:
-				tx_reg <= 1'b1; 
-		endcase
-end
-
-endmodule 
\ No newline at end of file
diff --git a/source/src/baud_rate_gen.v b/source/src/zutils/baud_rate_gen.v
similarity index 100%
rename from source/src/baud_rate_gen.v
rename to source/src/zutils/baud_rate_gen.v
diff --git a/source/src/zutils/zutils_clk_parser.v b/source/src/zutils/zutils_clk_parser.v
index 506c966..5ac753f 100644
--- a/source/src/zutils/zutils_clk_parser.v
+++ b/source/src/zutils/zutils_clk_parser.v
@@ -45,7 +45,7 @@ module zutils_clk_parser (
   /*******************************************************************************
    *                               first_clk_start                               *
    *******************************************************************************/
-  reg first_clk_start;
+  reg first_clk_start = 1;
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n || cs_signal_in) begin
       first_clk_start <= 1;
@@ -123,7 +123,7 @@ module zutils_clk_parser (
    *                                   clk_cnt                                   *
    *******************************************************************************/
 
-  reg [31:0] clk_cnt_reg;
+  reg [31:0] clk_cnt_reg = 0;
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n || cs_signal_in) begin
       clk_cnt_reg <= 0;
@@ -138,7 +138,7 @@ module zutils_clk_parser (
   /*******************************************************************************
    *                                 clk_bit_cnt                                 *
    *******************************************************************************/
-  reg [7:0] clk_bit_cnt_reg;
+  reg [7:0] clk_bit_cnt_reg = 0;
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n || cs_signal_in) begin
       clk_bit_cnt_reg <= 0;
@@ -160,7 +160,7 @@ module zutils_clk_parser (
    *                                 byte_cnt                                    *
    *******************************************************************************/
 
-  reg [31:0] byte_cnt_reg;
+  reg [31:0] byte_cnt_reg = 0;
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n || cs_signal_in) begin
       byte_cnt_reg <= 0;
diff --git a/source/src/zutils/zutils_debug_led.v b/source/src/zutils/zutils_debug_led.v
index 0d7eecd..26d6a3d 100644
--- a/source/src/zutils/zutils_debug_led.v
+++ b/source/src/zutils/zutils_debug_led.v
@@ -6,7 +6,7 @@ module zutils_debug_led #(
     output reg debug_led
 );
 
-    reg [31:0] counter;
+    reg [31:0] counter = 0;
 
     always @(posedge clk or negedge rst_n) begin
         if (!rst_n) begin
diff --git a/source/src/zutils/zutils_edge_detecter.v b/source/src/zutils/zutils_edge_detecter.v
index fb26fa9..14c8d9a 100644
--- a/source/src/zutils/zutils_edge_detecter.v
+++ b/source/src/zutils/zutils_edge_detecter.v
@@ -2,16 +2,18 @@ module zutils_edge_detecter (
     input clk,  //clock input
     input rst_n,  //asynchronous reset input, low active
     input wire in_signal,
-    output reg in_signal_last,
-    output reg in_signal_rising_edge,
-    output reg in_signal_falling_edge,
-    output reg in_signal_edge
+    output in_signal_last,
+    output in_signal_rising_edge,
+    output in_signal_falling_edge,
+    output in_signal_edge
 );
 
+  reg in_signal_last = 0;
+  reg in_signal_rising_edge = 0;
+  reg in_signal_falling_edge = 0;
+  reg in_signal_edge = 0;
+
 
-  // reg in_signal_rising_edge;
-  // reg in_signal_falling_edge;
-  // reg in_signal_edge;
 
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
@@ -23,20 +25,20 @@ module zutils_edge_detecter (
 
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
-      in_signal_rising_edge   <= 0;
+      in_signal_rising_edge  <= 0;
       in_signal_falling_edge <= 0;
       in_signal_edge         <= 0;
     end else begin
       if (in_signal_last == 0 && in_signal == 1) begin
-        in_signal_rising_edge   <= 1;
+        in_signal_rising_edge  <= 1;
         in_signal_falling_edge <= 0;
         in_signal_edge         <= 1;
       end else if (in_signal_last == 1 && in_signal == 0) begin
-        in_signal_rising_edge   <= 0;
+        in_signal_rising_edge  <= 0;
         in_signal_falling_edge <= 1;
         in_signal_edge         <= 1;
       end else begin
-        in_signal_rising_edge   <= 0;
+        in_signal_rising_edge  <= 0;
         in_signal_falling_edge <= 0;
         in_signal_edge         <= 0;
       end
diff --git a/source/src/zutils/zutils_multiplexer_16t1.v b/source/src/zutils/zutils_multiplexer_16t1.v
index 9c03531..4613fc3 100644
--- a/source/src/zutils/zutils_multiplexer_16t1.v
+++ b/source/src/zutils/zutils_multiplexer_16t1.v
@@ -1,9 +1,11 @@
 module zutils_multiplexer_16t1 (
     input [31:0] chooseindex,
     input wire [15:0] signal,
-    output reg signalout
+    output signalout
 );
 
+  reg signalout = 0;
+
   always @(*) begin
     case (chooseindex)
       0: begin
diff --git a/source/src/zutils/zutils_multiplexer_4t1.v b/source/src/zutils/zutils_multiplexer_4t1.v
index 2b784bb..836dcf0 100644
--- a/source/src/zutils/zutils_multiplexer_4t1.v
+++ b/source/src/zutils/zutils_multiplexer_4t1.v
@@ -4,9 +4,11 @@ module zutils_multiplexer_4t1 (
     input wire signal1,
     input wire signal2,
     input wire signal3,
-    output reg signalout
+    output signalout
 );
 
+  reg signalout = 0;
+
   always @(*) begin
     case (chooseindex)
       0: begin
diff --git a/source/src/zutils/zutils_pluse_generator.v b/source/src/zutils/zutils_pluse_generator.v
index 6d15866..0d2f81d 100644
--- a/source/src/zutils/zutils_pluse_generator.v
+++ b/source/src/zutils/zutils_pluse_generator.v
@@ -4,11 +4,11 @@ module zutils_pluse_generator (
 
     input  wire [31:0] pluse_width,
     input  wire        trigger,
-    output reg         output_signal
+    output             output_signal
 
-    
-);
 
+);
+  reg output_signal = 0;
   reg [31:0] counter = 0;
 
   always @(posedge clk or negedge rst_n) begin
diff --git a/source/src/zutils/zutils_pwm_generator.v b/source/src/zutils/zutils_pwm_generator.v
index 86c00ff..cc6efae 100644
--- a/source/src/zutils/zutils_pwm_generator.v
+++ b/source/src/zutils/zutils_pwm_generator.v
@@ -2,14 +2,16 @@ module zutils_pwm_generator #(
     parameter SYS_CLOCK_FREQ = 50000000,
     parameter OUTPUT_FREQ = 1000
 ) (
-    input      clk,
-    input      rst_n,
-    output reg output_signal
+    input  clk,
+    input  rst_n,
+    output output_signal
 
 );
 
   localparam COUNT = SYS_CLOCK_FREQ / OUTPUT_FREQ;
   reg [31:0] counter = 0;
+  reg output_signal = 0;
+
 
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
diff --git a/source/src/zutils/zutils_register.v b/source/src/zutils/zutils_register.v
index 28bc564..57f56d6 100644
--- a/source/src/zutils/zutils_register.v
+++ b/source/src/zutils/zutils_register.v
@@ -26,7 +26,7 @@ module zutils_register16 #(
     input [31:0] wr_data,
     input        wr_en,
 
-   output [31:0] rd_data,  //received serial data 
+    output [31:0] rd_data,  //received serial data 
 
     output [31:0] reg0,
     output [31:0] reg1,
@@ -46,9 +46,8 @@ module zutils_register16 #(
     output [31:0] regF
 );
 
-  localparam ADD_NUM = 16;  //寄存器数量
-  parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1;  //寄存器结束地址
-  reg [31:0] data[0:ADD_NUM];
+  parameter REG_END_ADD = REG_START_ADD + 16 - 1;  //寄存器结束地址
+  reg [31:0] data[0:15] = 0;
 
   assign reg0 = data[0];
   assign reg1 = data[1];
diff --git a/source/src/zutils/zutils_signal_filter.v b/source/src/zutils/zutils_signal_filter.v
index 8ed46ef..4fa4771 100644
--- a/source/src/zutils/zutils_signal_filter.v
+++ b/source/src/zutils/zutils_signal_filter.v
@@ -4,9 +4,10 @@ module zutils_signal_filter #(
     input       clk,    //clock input
     input       rst_n,  //asynchronous reset input, low active
     input  wire in,
-    output reg  out
+    output      out
 );
-  reg [31:0] counter;
+  reg out = 0;
+  reg [31:0] counter = 0;
   always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
       counter <= 0;