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xsync_fpge
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V3.0

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zhaohe 1 year ago
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3ebac6a5d9
commit
d39251373a
11 changed files with 499 additions and 523 deletions
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  1. 104
      led_test.pds
  2. 7
      source/src/config.v
  3. 74
      source/src/output/camera_sync_signal_output.v
  4. 19
      source/src/output/timecode_output.v
  5. 159
      source/src/output/ttl_output.v
  6. 252
      source/src/sys_signal_delayer.v
  7. 6
      source/src/timecode/timecode_generator.v
  8. 78
      source/src/timecode/timecode_serialization.v
  9. 90
      source/src/top.v
  10. 142
      source/src/zutils/zsimple_pll.v
  11. 91
      source/src/zutils/zutils_sig_delayer_v2.v

104
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sat Mar 23 20:35:10 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Mon Mar 25 20:08:45 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-23T17:11:42")
(_timespec "2024-03-25T17:56:09")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -59,7 +59,7 @@
)
(_file "source/src/output/ttl_output.v"
(_format verilog)
(_timespec "2024-03-05T10:18:24")
(_timespec "2024-03-25T14:05:59")
)
(_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog)
@ -91,7 +91,7 @@
)
(_file "source/src/zutils/zutils_register_advanced.v"
(_format verilog)
(_timespec "2024-03-04T18:48:11")
(_timespec "2024-03-25T09:14:45")
)
(_file "source/src/zutils/zutils_genlock_clk_generator.v"
(_format verilog)
@ -119,15 +119,15 @@
)
(_file "source/src/timecode/timecode_serialization.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
(_timespec "2024-03-25T16:05:09")
)
(_file "source/src/timecode/timecode_generator.v"
(_format verilog)
(_timespec "2024-03-23T19:26:35")
(_timespec "2024-03-25T17:29:22")
)
(_file "source/src/output/timecode_output.v"
(_format verilog)
(_timespec "2024-03-04T18:50:44")
(_timespec "2024-03-25T17:21:13")
)
(_file "source/src/input/timecode_input.v"
(_format verilog)
@ -139,7 +139,7 @@
)
(_file "source/src/timecode/timecode_sample_sig_generator.v"
(_format verilog)
(_timespec "2024-02-27T20:28:55")
(_timespec "2024-03-25T09:20:42")
)
(_file "source/src/input/ttl_input.v"
(_format verilog)
@ -163,7 +163,7 @@
)
(_file "source/src/zutils/zsimple_pll.v"
(_format verilog)
(_timespec "2024-03-04T09:54:54")
(_timespec "2024-03-23T20:42:57")
)
(_file "source/src/zutils/zutils_freq_detector_v2.v"
(_format verilog)
@ -207,7 +207,7 @@
)
(_file "source/src/output/camera_sync_signal_output.v"
(_format verilog)
(_timespec "2024-03-21T15:01:29")
(_timespec "2024-03-25T17:49:01")
)
(_file "source/src/business/record_sig_generator.v"
(_format verilog)
@ -215,7 +215,7 @@
)
(_file "source/src/sys_signal_delayer.v"
(_format verilog)
(_timespec "2024-03-22T21:08:01")
(_timespec "2024-03-25T11:41:59")
)
(_file "source/src/zutils/zutils_sig_delayer.v"
(_format verilog)
@ -223,7 +223,7 @@
)
(_file "source/src/zutils/zutils_sig_delayer_v2.v"
(_format verilog)
(_timespec "2024-03-22T22:10:19")
(_timespec "2024-03-25T17:37:50")
)
(_file "source/src/zutils/zutils_pluse_delayer.v"
(_format verilog)
@ -315,17 +315,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-03-23T20:34:02")
(_timespec "2024-03-25T19:55:01")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-03-23T20:33:59")
(_timespec "2024-03-25T19:54:58")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-03-23T20:34:02")
(_timespec "2024-03-25T19:55:01")
)
)
)
@ -341,21 +341,21 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-03-23T20:34:48")
(_timespec "2024-03-25T19:55:33")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-03-23T20:35:00")
(_timespec "2024-03-25T19:55:35")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-03-23T20:35:09")
(_timespec "2024-03-25T19:55:37")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-03-23T20:35:10")
(_timespec "2024-03-25T19:55:37")
)
)
)
@ -372,14 +372,34 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-03-25T19:55:42")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-03-25T19:55:39")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-03-25T19:55:42")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-03-25T19:55:42")
)
)
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-03-22T22:05:00")
(_timespec "2024-03-25T19:55:42")
)
)
)
@ -389,8 +409,47 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
(_option parallel (_integer 4))
(_option share_router_control_signal (_boolean FALSE))
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option mode (_string "fast"))
(_option fix_hold_violation_in_route (_boolean FALSE))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-25T20:08:43")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-25T20:08:44")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-25T20:08:41")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-25T20:08:41")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-25T19:56:00")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-25T20:08:44")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-25T20:08:45")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -401,7 +460,6 @@
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))

7
source/src/config.v
View File

@ -19,9 +19,6 @@
`define REGADDOFF__RECORD_SIG_GENERATOR 16'h0500
`define REGADDOFF__DELAYER 16'h0600
`define FREQ_DETECT_BIAS_DEFAULT 32'd10
`define SIGNAL_LOGIC0 32'd0
`define SIGNAL_LOGIC1 32'd1
`define SIGNAL_TTLIN1 32'd2
@ -38,3 +35,7 @@
`define SIGNAL_SYS_TIMECODE_FREQ_OUTPUT 32'd13
`define SIGNAL_BUSINESS_RECORD_SIG 32'd14
`define SIGNAL_BUSINESS_RECORD_EXPOSURE_SIG 32'd15
`define TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH 32'd1000
`define FREQ_DETECT_BIAS_DEFAULT 32'd10
`define VERSION 32'd3

74
source/src/output/camera_sync_signal_output.v
View File

@ -11,17 +11,27 @@ module camera_sync_signal_output #(
input wr_en,
output wire [31:0] rd_data,
input in_timecode_tigger_sig,
input [31:0] in_timecode_format,
input [63:0] in_timecode_data,
input in_timecode_serial_data,
input frame_sig,
input record_en_sig,
output stm32if_camera_sync_out, //ttl输出信号
output stm32if_record_state_change_sig //
output stm32if_camera_sync_out, //ttl输出信号
output stm32if_record_state_change_sig, //
output stm32if_timecode_tigger_sig
);
/*******************************************************************************
* 寄存器列表 *
*******************************************************************************/
reg [31:0] reg1_pulse_mode_valid_len;
reg [31:0] reg2_timecode_snapshot0; //!
reg [31:0] reg3_timecode_snapshot1; //!
reg [31:0] reg4_sub_frame_cnt; //!
wire [31:0] reg_wr_index;
zutils_register_advanced #(
@ -34,6 +44,8 @@ module camera_sync_signal_output #(
.wr_en (wr_en),
.rd_data (rd_data),
.reg1 (reg1_pulse_mode_valid_len),
.reg2 (reg2_timecode_snapshot0),
.reg3 (reg3_timecode_snapshot1),
.reg_wr_sig(reg_wr_sig),
.reg_index (reg_wr_index)
);
@ -52,6 +64,8 @@ module camera_sync_signal_output #(
end
end
/*******************************************************************************
* 内部信号 *
*******************************************************************************/
@ -67,7 +81,58 @@ module camera_sync_signal_output #(
.in_signal_rising_edge(frame_sig_rising_edge)
);
// 短脉冲，触发生成，长脉冲
//! 锁存系统时钟触发时的时码
//! 清空
reg [31:0] timecode_data_cache0; //!
reg [31:0] timecode_data_cache1; //!
wire [ 1:0] trigger_sig;
assign trigger_sig[0] = frame_sig_rising_edge;
assign trigger_sig[1] = in_timecode_tigger_sig;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg2_timecode_snapshot0 <= 0;
reg3_timecode_snapshot1 <= 0;
reg4_sub_frame_cnt <= 0;
timecode_data_cache0 <= 0;
timecode_data_cache1 <= 0;
end else begin
case (trigger_sig)
2'b01: begin
//帧触发信号
reg2_timecode_snapshot0 <= timecode_data_cache0;
reg3_timecode_snapshot1 <= timecode_data_cache1;
reg4_sub_frame_cnt <= reg4_sub_frame_cnt + 1;
end
2'b10: begin
//时码变更触发信号
timecode_data_cache0 <= in_timecode_data[31:0];
timecode_data_cache1 <= in_timecode_data[63:32];
reg4_sub_frame_cnt <= 0;
end
2'b11: begin
//帧触发信号&时码变更信号
timecode_data_cache0 <= in_timecode_data[31:0];
timecode_data_cache1 <= in_timecode_data[63:32];
reg2_timecode_snapshot0 <= in_timecode_data[31:0];
reg3_timecode_snapshot1 <= in_timecode_data[63:32];
reg4_sub_frame_cnt <= 1;
end
default: begin
end
endcase
end
end
//! 短脉冲，触发生成，长脉冲
zutils_pluse_generator _pluse_generator (
.clk (clk),
.rst_n (rst_n),
@ -77,7 +142,8 @@ module camera_sync_signal_output #(
.output_signal(frame_sig_fa_process)
);
assign stm32if_camera_sync_out = frame_sig_fa_process;
assign stm32if_camera_sync_out = frame_sig_fa_process;
assign stm32if_record_state_change_sig = record_en_sig;
assign stm32if_timecode_tigger_sig = 0;
endmodule

19
source/src/output/timecode_output.v
View File

@ -22,7 +22,6 @@ module timecode_output #(
/*******************************************************************************
* 输出接口 *
*******************************************************************************/
output stm32if_timecode_tigger_sig,
output reg timecode_out_bnc,
output reg timecode_out_bnc_select, // 电平选择 0line,1:mic
@ -83,32 +82,18 @@ module timecode_output #(
assign r1_timecode0 = in_timecode_data[31:0];
assign r2_timecode1 = in_timecode_data[63:32];
assign r3_timecode_format = in_timecode_format;
assign out_timecode_serial_data = in_timecode_serial_data;
assign timecode_tigger_sig = in_timecode_tigger_sig;
zutils_pluse_generator _pluse_generator (
.clk (clk),
.rst_n (rst_n),
.pluse_width (1000), //1ms
.pluse_delay (32'd0),
.trigger (timecode_tigger_sig),
.output_signal(stm32if_timecode_tigger_sig)
);
always @(*) begin
timecode_out_bnc <= out_timecode_serial_data;
timecode_out_bnc <= in_timecode_serial_data;
timecode_out_bnc_select <= r4_bnc_outut_level_select[0];
timecode_out_bnc_state_led <= 1;
timecode_out_headphone <= out_timecode_serial_data;
timecode_out_headphone <= in_timecode_serial_data;
timecode_out_headphone_select <= r5_headphone_outut_level_select[0];
timecode_out_headphone_state_led <= 1;
end
endmodule

159
source/src/output/ttl_output.v
View File

@ -22,29 +22,32 @@ module ttl_output #(
/*******************************************************************************
* 寄存器列表 *
*******************************************************************************/
//!信号处理模式 0:固定输出低电平，1:固定输出高电平，2:分频倍频模式，3:转发模式，4:测试模式
reg [31:0] reg_signal_process_mode;
//!信号处理模式 0:固定输出低电平，1:固定输出高电平，2:触发模式，3:转发模式，4:测试模式
reg [31:0] reg1_signal_process_mode;
//!TTLOUT_信号选择器
reg [31:0] reg_input_signal_select;
reg [31:0] reg2_input_signal_select;
//!TTLOUT_分频器
reg [31:0] reg_pllout_freq_division_ctrl;
reg [31:0] reg3_pllout_freq_division_ctrl;
//!TTLOUT_频率倍增器
reg [31:0] reg_pllout_freq_multiplication_ctrl;
reg [31:0] reg4_pllout_freq_multiplication_ctrl;
//!TTLOUT_极性控制寄存器
reg [31:0] reg_pllout_polarity_ctrl;
reg [31:0] reg5_pllout_polarity_ctrl;
//!TTLOUT_触发信号边沿类型
reg [31:0] reg_pllout_trigger_edge_select;
reg [31:0] reg6_pllout_trigger_edge_select;
//!转发模式下的极性控制
reg [31:0] reg_forward_mode_polarity_ctrl;
reg [31:0] reg7_forward_mode_polarity_ctrl;
//!占位
reg [31:0] reg_placeholder0;
// !频率探测偏差
reg [31:0] reg_freq_detect_bias;
reg [31:0] reg8_placeholder0;
//!频率探测偏差
reg [31:0] reg9_freq_detect_bias;
//!分频倍频后的信号脉宽
reg [31:0] regA_pluse_width_ctrl;
//!分频后信号延迟
reg [31:0] regB_pluse_delay_ctrl;
//!输入信号频率探测 read only
wire [31:0] reg_sig_in_freq_detect;
wire [31:0] regE_sig_in_freq_detect;
//!输出信号频率探测 read only
wire [31:0] reg_sig_out_freq_detect;
wire [31:0] regF_sig_out_freq_detect;
wire [31:0] reg_wr_index; //!寄存器写入时相对地址
wire signal_in_choose; //!原始信号
@ -57,11 +60,11 @@ module ttl_output #(
//信号流转图
//
// signal_in[](原始信号)
// ---> reg_input_signal_select -->signal_in_choose(信号选择器)
// ---> reg2_input_signal_select -->signal_in_choose(信号选择器)
// -->
// reg_pllout_trigger_edge_select
// reg_pllout_freq_division_ctrl ---> signal_in_af_pll(经分频倍频后的信号)
// reg_pllout_freq_multiplication_ctrl
// reg6_pllout_trigger_edge_select
// reg3_pllout_freq_division_ctrl ---> signal_in_af_pll(经分频倍频后的信号)
// reg4_pllout_freq_multiplication_ctrl
// ---> signal_af_pll_af_polarity_ctrl
//
//
@ -82,17 +85,19 @@ module ttl_output #(
.wr_data (wr_data),
.wr_en (wr_en),
.rd_data (rd_data),
.reg1 (reg_signal_process_mode),
.reg2 (reg_input_signal_select),
.reg3 (reg_pllout_freq_division_ctrl),
.reg4 (reg_pllout_freq_multiplication_ctrl),
.reg5 (reg_pllout_polarity_ctrl),
.reg6 (reg_pllout_trigger_edge_select),
.reg7 (reg_forward_mode_polarity_ctrl),
.reg8 (reg_placeholder0),
.reg9 (reg_freq_detect_bias),
.regE (reg_sig_in_freq_detect),
.regF (reg_sig_out_freq_detect),
.reg1 (reg1_signal_process_mode),
.reg2 (reg2_input_signal_select),
.reg3 (reg3_pllout_freq_division_ctrl),
.reg4 (reg4_pllout_freq_multiplication_ctrl),
.reg5 (reg5_pllout_polarity_ctrl),
.reg6 (reg6_pllout_trigger_edge_select),
.reg7 (reg7_forward_mode_polarity_ctrl),
.reg8 (reg8_placeholder0),
.reg9 (reg9_freq_detect_bias),
.regA (regA_pluse_width_ctrl),
.regB (regB_pluse_delay_ctrl),
.regE (regE_sig_in_freq_detect),
.regF (regF_sig_out_freq_detect),
.reg_wr_sig(reg_wr_sig),
.reg_index (reg_wr_index)
);
@ -100,27 +105,31 @@ module ttl_output #(
//!寄存器写入逻辑
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
reg_signal_process_mode <= 0;
reg_input_signal_select <= 0;
reg_pllout_freq_division_ctrl <= 0;
reg_pllout_freq_multiplication_ctrl <= 0;
reg_pllout_polarity_ctrl <= 0;
reg_pllout_trigger_edge_select <= 1;
reg_forward_mode_polarity_ctrl <= 0;
reg_placeholder0 <= 0;
reg_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT;
reg1_signal_process_mode <= 0;
reg2_input_signal_select <= 0;
reg3_pllout_freq_division_ctrl <= 0;
reg4_pllout_freq_multiplication_ctrl <= 0;
reg5_pllout_polarity_ctrl <= 0;
reg6_pllout_trigger_edge_select <= 1;
reg7_forward_mode_polarity_ctrl <= 0;
reg8_placeholder0 <= 0;
reg9_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT;
regA_pluse_width_ctrl <= `TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH;
regB_pluse_delay_ctrl <= 0;
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)
1: reg_signal_process_mode <= wr_data;
2: reg_input_signal_select <= wr_data;
3: reg_pllout_freq_division_ctrl <= wr_data;
4: reg_pllout_freq_multiplication_ctrl <= wr_data;
5: reg_pllout_polarity_ctrl <= wr_data;
6: reg_pllout_trigger_edge_select <= wr_data;
7: reg_forward_mode_polarity_ctrl <= wr_data;
8: reg_placeholder0 <= wr_data;
9: reg_freq_detect_bias <= wr_data;
1: reg1_signal_process_mode <= wr_data;
2: reg2_input_signal_select <= wr_data;
3: reg3_pllout_freq_division_ctrl <= wr_data;
4: reg4_pllout_freq_multiplication_ctrl <= wr_data;
5: reg5_pllout_polarity_ctrl <= wr_data;
6: reg6_pllout_trigger_edge_select <= wr_data;
7: reg7_forward_mode_polarity_ctrl <= wr_data;
8: reg8_placeholder0 <= wr_data;
9: reg9_freq_detect_bias <= wr_data;
10: regA_pluse_width_ctrl <= wr_data;
32'hB: regB_pluse_delay_ctrl <= wr_data;
default: begin
end
endcase
@ -130,7 +139,7 @@ module ttl_output #(
//!信号选择器
zutils_multiplexer_32t1 signal_in_multiplexer (
.chooseindex(reg_input_signal_select),
.chooseindex(reg2_input_signal_select),
.signal (signal_in),
.signalout (signal_in_choose)
);
@ -140,38 +149,49 @@ module ttl_output #(
.clk (clk),
.rst_n (rst_n),
.insignal (signal_in_choose),
.trigger_eage_type (reg_pllout_trigger_edge_select[0]),
.freq_detect_bias (reg_freq_detect_bias),
.freq_division (reg_pllout_freq_division_ctrl),
.freq_multiplication(reg_pllout_freq_multiplication_ctrl),
.polarity_ctrl (reg_pllout_polarity_ctrl[0]),
.trigger_eage_type (reg6_pllout_trigger_edge_select[0]),
.freq_detect_bias (reg9_freq_detect_bias),
.freq_division (reg3_pllout_freq_division_ctrl),
.freq_multiplication(reg4_pllout_freq_multiplication_ctrl),
.polarity_ctrl (1'd0),
.cfg_change (reg_wr_sig),
.outsignal (signal_in_af_pll)
// .outsignal (signal_in_af_pll),
.output_trigger_sig (signal_in_af_pll_trigger_sig)
);
//!100HZ测试信号发生器
zutils_pwm_generator #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(100)
) pwm100hz_gen (
//!脉冲生成
zutils_pluse_generator _pluse_generator (
.clk (clk),
.rst_n (rst_n),
.output_signal(signal_test)
.pluse_width (regA_pluse_width_ctrl),
.pluse_delay (regB_pluse_delay_ctrl),
.trigger (signal_in_af_pll_trigger_sig),
.output_signal(signal_in_af_pll_raw)
);
assign signal_in_af_pll = signal_in_af_pll_raw ^ reg5_pllout_polarity_ctrl[0];
//!100HZ测试信号发生器
// zutils_pwm_generator #(
// .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
// .OUTPUT_FREQ(100)
// ) pwm100hz_gen (
// .clk (clk),
// .rst_n (rst_n),
// .output_signal(signal_test)
// );
assign signal_in_af_forward_mode_polarity_ctrl = signal_in_choose ^ reg_forward_mode_polarity_ctrl[0];
assign signal_in_af_forward_mode_polarity_ctrl = signal_in_choose ^ reg7_forward_mode_polarity_ctrl[0];
//!信号输出选择器
zutils_multiplexer_8t1 signal_output_multiplexer (
.chooseindex(reg_signal_process_mode),
.chooseindex(reg1_signal_process_mode),
.signal0 (1'b0),
.signal1 (1'b1),
.signal2 (signal_in_af_pll),
.signal3 (signal_in_af_forward_mode_polarity_ctrl),
.signal4 (signal_test),
.signal4 (1'b0),
.signal5 (1'b0),
.signal6 (1'b0),
.signal7 (1'b0),
@ -179,21 +199,20 @@ module ttl_output #(
);
//
//
zutils_freq_detector_v2 in_freq_detector (
.clk (clk),
.rst_n (rst_n),
.freq_detect_bias(reg_freq_detect_bias),
.freq_detect_bias(reg9_freq_detect_bias),
.pluse_input (signal_in_choose),
.pluse_width_cnt (reg_sig_in_freq_detect)
.pluse_width_cnt (regE_sig_in_freq_detect)
);
zutils_freq_detector_v2 output_freq_detector (
.clk (clk),
.rst_n (rst_n),
.freq_detect_bias(reg_freq_detect_bias),
.freq_detect_bias(reg9_freq_detect_bias),
.pluse_input (ttloutput),
.pluse_width_cnt (reg_sig_out_freq_detect)
.pluse_width_cnt (regF_sig_out_freq_detect)
);
assign ttloutput_state_led = 1;

252
source/src/sys_signal_delayer.v
View File

@ -1,6 +1,7 @@
module sys_signal_delayer #(
parameter REG_START_ADD = 0,
parameter SYS_CLOCK_FREQ = 10000000
parameter SYS_CLOCK_FREQ = 10000000,
parameter SIG_BUS_WIDTH = 15
) (
input clk, //! 时钟输入
@ -14,58 +15,13 @@ module sys_signal_delayer #(
/*******************************************************************************
* 输入信号延迟 *
*******************************************************************************/
input sync_ttl_in1,
input sync_ttl_in2,
input sync_ttl_in3,
input sync_ttl_in4,
input timecode_headphone_in,
input timecode_bnc_in,
input genlock_in_hsync,
input genlock_in_vsync,
input genlock_in_fsync,
output af_delay__sync_ttl_in1,
output af_delay__sync_ttl_in2,
output af_delay__sync_ttl_in3,
output af_delay__sync_ttl_in4,
output af_delay__timecode_headphone_in,
output af_delay__timecode_bnc_in,
output af_delay__genlock_in_hsync,
output af_delay__genlock_in_vsync,
output af_delay__genlock_in_fsync,
/*******************************************************************************
* 输出接口延迟 *
*******************************************************************************/
output sync_ttl_out1,
output sync_ttl_out2,
output sync_ttl_out3,
output sync_ttl_out4,
output stm32if_start_signal_out,
output stm32if_camera_sync_out,
output stm32if_timecode_sync_out,
input before_delay__sync_ttl_out1,
input before_delay__sync_ttl_out2,
input before_delay__sync_ttl_out3,
input before_delay__sync_ttl_out4,
input before_delay__stm32if_start_signal_out,
input before_delay__stm32if_camera_sync_out,
input before_delay__stm32if_timecode_sync_out
input [SIG_BUS_WIDTH:0] sig_in,
output [SIG_BUS_WIDTH:0] sig_out
);
reg [31:0] r1_ctrl;
reg [31:0] r2_input_delay_cnt;
reg [31:0] r3_input_delay_freq_div;
reg [31:0] r4_output_delay_cnt;
reg [31:0] r5_output_delay_freq_div;
reg [31:0] r1_ctrl_reg_index;
reg [31:0] r2_delay_cnt_ctrl;
reg [31:0] delay_ctrl [SIG_BUS_WIDTH:0];
wire [31:0] reg_wr_index;
zutils_register_advanced #(
@ -77,190 +33,56 @@ module sys_signal_delayer #(
.wr_data (wr_data),
.wr_en (wr_en),
.rd_data (rd_data),
.reg1 (r1_ctrl),
.reg2 (r2_input_delay_cnt),
.reg3 (r3_input_delay_freq_div),
.reg4 (r4_output_delay_cnt),
.reg5 (r5_output_delay_freq_div),
.reg1 (r1_ctrl_reg_index),
.reg2 (r2_delay_cnt_ctrl),
.reg_wr_sig(reg_wr_sig),
.reg_index (reg_wr_index)
);
reg delayer_rst_n_ctrl;
reg delayer_rst_n_ctrl;
integer m;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
r1_ctrl <= 32'hffff_ffff;
r2_input_delay_cnt <= 32'd100;
r3_input_delay_freq_div <= 1;
r4_output_delay_cnt <= 0;
r5_output_delay_freq_div <= 1;
delayer_rst_n_ctrl <= 1;
r1_ctrl_reg_index <= 32'hffff_ffff;
r2_delay_cnt_ctrl <= 0;
for (m = 0; m <= SIG_BUS_WIDTH; m = m + 1) begin
delay_ctrl[m] <= 0;
end
delayer_rst_n_ctrl <= 1;
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)
1: begin
r1_ctrl <= wr_data;
delayer_rst_n_ctrl <= 0;
1: r1_ctrl_reg_index <= wr_data;
2: begin
if (r1_ctrl_reg_index <= SIG_BUS_WIDTH) begin
r2_delay_cnt_ctrl[r1_ctrl_reg_index] <= wr_data;
end
end
2: r2_input_delay_cnt <= wr_data;
3: r3_input_delay_freq_div <= wr_data;
4: r4_output_delay_cnt <= wr_data;
5: r5_output_delay_freq_div <= wr_data;
default: begin
end
endcase
delayer_rst_n_ctrl <= 0;
end else begin
delayer_rst_n_ctrl <= 1;
end
end
end
assign delayer_rst_n = delayer_rst_n_ctrl & rst_n;
zutils_sig_delayer_v2 sig_delayer_inst (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (sync_ttl_in1),
.out (af_delay__sync_ttl_in1)
);
zutils_sig_delayer_v2 sig_delayer_inst1 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (sync_ttl_in2),
.out (af_delay__sync_ttl_in2)
);
zutils_sig_delayer_v2 sig_delayer_inst2 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (sync_ttl_in3),
.out (af_delay__sync_ttl_in3)
);
zutils_sig_delayer_v2 sig_delayer_inst3 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (sync_ttl_in4),
.out (af_delay__sync_ttl_in4)
);
zutils_sig_delayer_v2 sig_delayer_inst4 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (timecode_headphone_in),
.out (af_delay__timecode_headphone_in)
);
zutils_sig_delayer_v2 sig_delayer_inst5 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (timecode_bnc_in),
.out (af_delay__timecode_bnc_in)
);
zutils_sig_delayer_v2 sig_delayer_inst6 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (genlock_in_hsync),
.out (af_delay__genlock_in_hsync)
);
zutils_sig_delayer_v2 sig_delayer_inst7 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (genlock_in_vsync),
.out (af_delay__genlock_in_vsync)
);
zutils_sig_delayer_v2 sig_delayer_inst8 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r2_input_delay_cnt),
.freq_division(r3_input_delay_freq_div),
.in (genlock_in_fsync),
.out (af_delay__genlock_in_fsync)
);
zutils_sig_delayer_v2 sig_delayer_inst9 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__sync_ttl_out1),
.out (sync_ttl_out1)
);
zutils_sig_delayer_v2 sig_delayer_inst10 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__sync_ttl_out2),
.out (sync_ttl_out2)
);
zutils_sig_delayer_v2 sig_delayer_inst11 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__sync_ttl_out3),
.out (sync_ttl_out3)
);
zutils_sig_delayer_v2 sig_delayer_inst12 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__sync_ttl_out4),
.out (sync_ttl_out4)
);
zutils_sig_delayer_v2 sig_delayer_inst13 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__stm32if_start_signal_out),
.out (stm32if_start_signal_out)
);
zutils_sig_delayer_v2 sig_delayer_inst14 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__stm32if_camera_sync_out),
.out (stm32if_camera_sync_out)
);
zutils_sig_delayer_v2 sig_delayer_inst15 (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt (r4_output_delay_cnt),
.freq_division(r5_output_delay_freq_div),
.in (before_delay__stm32if_timecode_sync_out),
.out (stm32if_timecode_sync_out)
);
genvar i;
generate
for (i = 0; i <= SIG_BUS_WIDTH; i = i + 1) begin
zutils_sig_delayer_v2 sig_delayer_inst (
.clk (clk),
.rst_n (delayer_rst_n),
.delay_cnt(delay_ctrl[i]),
.in (sig_in[i]),
.out (sig_out[i])
);
end
endgenerate
endmodule

6
source/src/timecode/timecode_generator.v
View File

@ -14,7 +14,7 @@ module timecode_generator #(
input [31:0] timecode1, //!timecode[32:63]写数据
output [31:0] timecode1_export, //!timecode[32:63]输出
input en, //!使能信号,只有在失能的情况才能修改timecode
input en, //!使能信号,只有在失能的情况才能修改timecode
output wire out_timecode_serial_data,
output wire out_trigger_sig,
@ -22,10 +22,6 @@ module timecode_generator #(
output wire [31:0] out_timecode1
);
//
wire [7:0] out_frame_num;
wire out_drop_frame;

78
source/src/timecode/timecode_serialization.v
View File

@ -11,8 +11,8 @@ module timecode_serialization #(
input [63:0] timecode,
output reg out_timecode_serial_data,
output reg out_trigger_sig,
output reg out_timecode_serial_data,
output reg out_trigger_sig,
output reg [63:0] out_timecode
);
@ -40,29 +40,39 @@ module timecode_serialization #(
reg [31:0] timecode_onehalf_bit_count;
always @(*) begin
case (timecode_format)
FPS2398Format: timecode_onehalf_bit_count = FPS2398FormatOneHalfFe;
FPS2400Format: timecode_onehalf_bit_count = FPS2400FormatOneHalfFe;
FPS2500Format: timecode_onehalf_bit_count = FPS2500FormatOneHalfFe;
FPS2997Format: timecode_onehalf_bit_count = FPS2997FormatOneHalfFe;
FPS2398Format: timecode_onehalf_bit_count = FPS2398FormatOneHalfFe;
FPS2400Format: timecode_onehalf_bit_count = FPS2400FormatOneHalfFe;
FPS2500Format: timecode_onehalf_bit_count = FPS2500FormatOneHalfFe;
FPS2997Format: timecode_onehalf_bit_count = FPS2997FormatOneHalfFe;
FPS2997DropFormat: timecode_onehalf_bit_count = FPS2997DropFormatOneHalfFe;
FPS3000Format: timecode_onehalf_bit_count = FPS3000FormatOneHalfFe;
default: timecode_onehalf_bit_count = FPS2398FormatOneHalfFe;
FPS3000Format: timecode_onehalf_bit_count = FPS3000FormatOneHalfFe;
default: timecode_onehalf_bit_count = FPS2398FormatOneHalfFe;
endcase
end
reg [31:0] oneframe_timeout_count;
always @(*) begin
case (timecode_format)
FPS2398Format: oneframe_timeout_count = FPS2398FormatOneHalfFe * 2 * 80;
FPS2400Format: oneframe_timeout_count = FPS2400FormatOneHalfFe * 2 * 80;
FPS2500Format: oneframe_timeout_count = FPS2500FormatOneHalfFe * 2 * 80;
FPS2997Format: oneframe_timeout_count = FPS2997FormatOneHalfFe * 2 * 80;
FPS2398Format: oneframe_timeout_count = FPS2398FormatOneHalfFe * 2 * 80;
FPS2400Format: oneframe_timeout_count = FPS2400FormatOneHalfFe * 2 * 80;
FPS2500Format: oneframe_timeout_count = FPS2500FormatOneHalfFe * 2 * 80;
FPS2997Format: oneframe_timeout_count = FPS2997FormatOneHalfFe * 2 * 80;
FPS2997DropFormat: oneframe_timeout_count = FPS2997DropFormatOneHalfFe * 2 * 80;
FPS3000Format: oneframe_timeout_count = FPS3000FormatOneHalfFe * 2 * 80;
default: oneframe_timeout_count = FPS2398FormatOneHalfFe * 2 * 80;
FPS3000Format: oneframe_timeout_count = FPS3000FormatOneHalfFe * 2 * 80;
default: oneframe_timeout_count = FPS2398FormatOneHalfFe * 2 * 80;
endcase
end
reg dropflag;
always @(*) begin
case (timecode_format)
FPS2997DropFormat: dropflag = 1;
default: dropflag = 0;
endcase
end
/*******************************************************************************
* workflag *
*******************************************************************************/
@ -73,26 +83,26 @@ module timecode_serialization #(
localparam NULL_CTRL_SIG = 0;
reg [31:0] oneframe_timeout_counter;
reg [1:0] internal_ctrl_sig;
reg startflag;
reg [ 1:0] internal_ctrl_sig;
reg startflag;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
oneframe_timeout_counter <= 0;
startflag <= 0;
internal_ctrl_sig <= NULL_CTRL_SIG;
startflag <= 0;
internal_ctrl_sig <= NULL_CTRL_SIG;
end else begin
if (trigger_sig && startflag) begin // 重启
oneframe_timeout_counter <= oneframe_timeout_count;
internal_ctrl_sig <= RESTART_CTRL_SIG;
startflag <= 1;
internal_ctrl_sig <= RESTART_CTRL_SIG;
startflag <= 1;
end else if (trigger_sig && !startflag) begin //启动
oneframe_timeout_counter <= oneframe_timeout_count;
internal_ctrl_sig <= START_CTRL_SIG;
startflag <= 1;
internal_ctrl_sig <= START_CTRL_SIG;
startflag <= 1;
end else if (!trigger_sig && startflag && oneframe_timeout_counter == 0) begin //停止
internal_ctrl_sig <= STOP_CTRL_SIG;
startflag <= 0;
startflag <= 0;
end else begin
if (oneframe_timeout_counter != 0) begin
oneframe_timeout_counter <= oneframe_timeout_counter - 1;
@ -103,6 +113,8 @@ module timecode_serialization #(
end
reg [79:0] in_timecode_cache;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
@ -110,7 +122,13 @@ module timecode_serialization #(
end else begin
case (internal_ctrl_sig)
START_CTRL_SIG, RESTART_CTRL_SIG: begin
in_timecode_cache[63:0] <= timecode;
in_timecode_cache[9:0] <= timecode[9:0];
if (dropflag) begin
in_timecode_cache[10] <= 1;
end else begin
in_timecode_cache[10] <= 0;
end
in_timecode_cache[63:11] <= timecode[63:11];
in_timecode_cache[79:64] <= 16'b1011_1111_1111_1100;
end
STOP_CTRL_SIG: begin
@ -131,7 +149,7 @@ module timecode_serialization #(
// bit trigger sig gen
reg [31:0] halfbitcount;
reg bit_tigger_sig;
reg bit_tigger_sig;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
halfbitcount <= 0;
@ -166,16 +184,16 @@ module timecode_serialization #(
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
onebitoff <= 0;
bitoff <= 0;
bitoff <= 0;
end else begin
case (internal_ctrl_sig)
START_CTRL_SIG, RESTART_CTRL_SIG: begin
onebitoff <= 0;
bitoff <= 0;
bitoff <= 0;
end
STOP_CTRL_SIG: begin
onebitoff <= 0;
bitoff <= 0;
bitoff <= 0;
end
default: begin
if (bit_tigger_sig) begin
@ -244,11 +262,11 @@ module timecode_serialization #(
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
out_trigger_sig <= 0;
out_timecode <= 0;
out_timecode <= 0;
end else begin
case (internal_ctrl_sig)
RESTART_CTRL_SIG, STOP_CTRL_SIG: begin
out_timecode <= in_timecode_cache[63:0];
out_timecode <= in_timecode_cache[63:0];
out_trigger_sig <= 1;
end
default: begin

90
source/src/top.v
View File

@ -221,7 +221,7 @@ module Top (
*******************************************************************************/
zutils_register16 #(
.REG_START_ADD(`REGADDOFF__FPGA_INFO),
.REG0_INIT(0),
.REG0_INIT(`VERSION),
.REG1_INIT(0),
.REG2_INIT(0),
.REG3_INIT(0),
@ -258,46 +258,43 @@ module Top (
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_sys_signal_delayer),
.sync_ttl_in1 (sync_ttl_in1),
.sync_ttl_in2 (sync_ttl_in2),
.sync_ttl_in3 (sync_ttl_in3),
.sync_ttl_in4 (sync_ttl_in4),
.timecode_headphone_in(timecode_headphone_in),
.timecode_bnc_in (timecode_bnc_in),
.genlock_in_hsync (genlock_in_hsync),
.genlock_in_vsync (genlock_in_vsync),
.genlock_in_fsync (genlock_in_fsync),
.af_delay__sync_ttl_in1 (af_delay__sync_ttl_in1),
.af_delay__sync_ttl_in2 (af_delay__sync_ttl_in2),
.af_delay__sync_ttl_in3 (af_delay__sync_ttl_in3),
.af_delay__sync_ttl_in4 (af_delay__sync_ttl_in4),
.af_delay__timecode_headphone_in(af_delay__timecode_headphone_in),
.af_delay__timecode_bnc_in (af_delay__timecode_bnc_in),
.af_delay__genlock_in_hsync (af_delay__genlock_in_hsync),
.af_delay__genlock_in_vsync (af_delay__genlock_in_vsync),
.af_delay__genlock_in_fsync (af_delay__genlock_in_fsync),
.sync_ttl_out1(sync_ttl_out1),
.sync_ttl_out2(sync_ttl_out2),
.sync_ttl_out3(sync_ttl_out3),
.sync_ttl_out4(sync_ttl_out4),
.stm32if_start_signal_out (stm32if_start_signal_out),
.stm32if_camera_sync_out (stm32if_camera_sync_out),
.stm32if_timecode_sync_out(stm32if_timecode_sync_out),
.before_delay__sync_ttl_out1(before_delay__sync_ttl_out1),
.before_delay__sync_ttl_out2(before_delay__sync_ttl_out2),
.before_delay__sync_ttl_out3(before_delay__sync_ttl_out3),
.before_delay__sync_ttl_out4(before_delay__sync_ttl_out4),
.before_delay__stm32if_start_signal_out (before_delay__stm32if_start_signal_out),
.before_delay__stm32if_camera_sync_out (before_delay__stm32if_camera_sync_out),
.before_delay__stm32if_timecode_sync_out(before_delay__stm32if_timecode_sync_out)
.sig_in({
sync_ttl_in1, //0
sync_ttl_in2, //1
sync_ttl_in3, //2
sync_ttl_in4, //3
timecode_headphone_in, //4
timecode_bnc_in, //5
genlock_in_hsync, //6
genlock_in_vsync, //7
genlock_in_fsync, //8
before_delay__sync_ttl_out1, //9
before_delay__sync_ttl_out2, //10
before_delay__sync_ttl_out3, //11
before_delay__sync_ttl_out4, //12
before_delay__stm32if_start_signal_out, //13
before_delay__stm32if_camera_sync_out, //14
before_delay__stm32if_timecode_sync_out //15
}),
.sig_out({
af_delay__sync_ttl_in1, //0
af_delay__sync_ttl_in2, //1
af_delay__sync_ttl_in3, //2
af_delay__sync_ttl_in4, //3
af_delay__timecode_headphone_in, //4
af_delay__timecode_bnc_in, //5
af_delay__genlock_in_hsync, //6
af_delay__genlock_in_vsync, //7
af_delay__genlock_in_fsync, //8
sync_ttl_out1, //9
sync_ttl_out2, //10
sync_ttl_out3, //11
sync_ttl_out4, //12
stm32if_start_signal_out, //13
stm32if_camera_sync_out, //14
stm32if_timecode_sync_out //15
})
);
@ -388,7 +385,7 @@ module Top (
*******************************************************************************/
internal_sig_generator_en_contrler #(
.REG_START_ADD(`REGADDOFF__INTERNAL_SIG_EN_CONTRLER),
.REG_START_ADD (`REGADDOFF__INTERNAL_SIG_EN_CONTRLER),
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) internal_sig_generator_en_contrler0 (
.clk (sys_clk),
@ -416,7 +413,7 @@ module Top (
.wr_data(RegReaderBus_wr_data),
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_internal_timecode),
.en(en0),
.timecode_tigger_sig (internal_timecode_tigger_sig),
@ -618,8 +615,6 @@ module Top (
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_timecode_out),
.stm32if_timecode_tigger_sig(before_delay__stm32if_timecode_sync_out),
.in_timecode_tigger_sig (sys_timecode_tigger_sig),
.in_timecode_format (sys_timecode_format),
.in_timecode_data (sys_timecode_data),
@ -673,11 +668,12 @@ module Top (
.wr_en (RegReaderBus_wr_en),
.rd_data(rd_data_module_camera_sync_out),
.frame_sig (signal_business_record_exposure_sig),
.frame_sig (signal_sys_clk_output),
.record_en_sig(signal_business_record_en_sig),
.stm32if_camera_sync_out (before_delay__stm32if_camera_sync_out),
.stm32if_record_state_change_sig(before_delay__stm32if_start_signal_out)
.stm32if_record_state_change_sig(before_delay__stm32if_start_signal_out),
.stm32if_timecode_tigger_sig(before_delay__stm32if_timecode_sync_out)
);
assign debug_signal_output[0] = sys_clk;

142
source/src/zutils/zsimple_pll.v
View File

@ -2,15 +2,16 @@ module zsimple_pll (
input clk, //!clock input
input rst_n, //!asynchronous reset input, low active
input insignal, //!输入信号
input trigger_eage_type,
input wire [31:0] freq_detect_bias, //! 频率偏差计数
input wire [31:0] freq_division,
input wire [31:0] freq_multiplication,
input wire polarity_ctrl,
input wire cfg_change,
output wire outsignal
);
input insignal, //!输入信号
input trigger_eage_type,
input wire [31:0] freq_detect_bias, //! 频率偏差计数
input wire [31:0] freq_division,
input wire [31:0] freq_multiplication,
input wire polarity_ctrl,
input wire cfg_change,
output wire outsignal,
output reg output_trigger_sig
);
//
//
@ -24,46 +25,43 @@ module zsimple_pll (
wire insignal_rising_edge; //! 输入信号上升沿
wire insignal_falling_edge; //! 输入信号下降沿
wire insignal_trigger_sig; //! 触发信号
wire module_reset; //! 模块内部复位信号
wire insignal_rising_edge; //! 输入信号上升沿
wire insignal_falling_edge; //! 输入信号下降沿
wire insignal_trigger_sig; //! 触发信号
wire module_reset; //! 模块内部复位信号
reg insignal_division; //! 输入信号分频后的信号
reg insignal_multiplication;//! 输入信号倍频后的信号
reg insignal_pluse_width_modulation;//! 输入信号脉宽调制后的信号
reg insignal_division; //! 输入信号分频后的信号
reg insignal_multiplication; //! 输入信号倍频后的信号
reg insignal_pluse_width_modulation; //! 输入信号脉宽调制后的信号
zutils_edge_detecter edge_detecter (
.clk(clk),
.rst_n(rst_n),
.in_signal(insignal),
.in_signal_rising_edge(insignal_rising_edge),
.in_signal_falling_edge(insignal_falling_edge)
);
.clk (clk),
.rst_n (rst_n),
.in_signal (insignal),
.in_signal_rising_edge (insignal_rising_edge),
.in_signal_falling_edge(insignal_falling_edge)
);
assign insignal_trigger_sig = trigger_eage_type ? insignal_rising_edge : insignal_falling_edge;
assign module_reset = !rst_n || cfg_change;
assign module_reset = !rst_n || cfg_change;
// 分频
reg [31:0] insignal_division_cnt;
always @(posedge clk or posedge module_reset) begin
if (module_reset) begin
insignal_division_cnt <= 0;
insignal_division <= 0;
end
else begin
if(insignal_trigger_sig) begin
if(insignal_division_cnt >= freq_division) begin
insignal_division <= 0;
end else begin
if (insignal_trigger_sig) begin
if (insignal_division_cnt >= freq_division) begin
insignal_division_cnt <= 0;
insignal_division <= 1;
end
else begin
insignal_division <= 1;
end else begin
insignal_division_cnt <= insignal_division_cnt + 1;
end
end
else begin
end else begin
insignal_division <= 0;
end
end
@ -71,17 +69,16 @@ module zsimple_pll (
wire [31:0] insignal_multiplication_freq_cnt;
wire pluse_width_cnt_lock;
zutils_freq_detector_v2
freq_detector (
.clk(clk),
.rst_n(rst_n),
.freq_detect_bias(freq_detect_bias),
.pluse_input(insignal_division),
.pluse_width_cnt(insignal_multiplication_freq_cnt),
wire pluse_width_cnt_lock;
zutils_freq_detector_v2 freq_detector (
.clk (clk),
.rst_n (rst_n),
.freq_detect_bias (freq_detect_bias),
.pluse_input (insignal_division),
.pluse_width_cnt (insignal_multiplication_freq_cnt),
.pluse_width_cnt_lock(pluse_width_cnt_lock)
);
);
reg [31:0] multiplication_cnt;
@ -90,49 +87,50 @@ module zsimple_pll (
always @(posedge clk or posedge module_reset) begin
if (module_reset || !pluse_width_cnt_lock) begin
multiplication_cnt <= 0;
multiplication_state <= 0;
gen_pluse_cnt <= 0;
multiplication_cnt <= 0;
multiplication_state <= 0;
gen_pluse_cnt <= 0;
insignal_multiplication <= 0;
end
else begin
output_trigger_sig <= 0;
end else begin
case (multiplication_state)
0 : begin
gen_pluse_cnt <= 0;
multiplication_cnt <= 0;
0: begin
gen_pluse_cnt <= 0;
multiplication_cnt <= 0;
insignal_multiplication <= 0;
if(pluse_width_cnt_lock) begin
if (pluse_width_cnt_lock) begin
multiplication_state <= 1;
end
end
1 : begin
if(insignal_division) begin
multiplication_state <= 2;
gen_pluse_cnt <= 0;
1: begin
if (insignal_division) begin
multiplication_state <= 2;
gen_pluse_cnt <= 0;
insignal_multiplication <= 1;
multiplication_cnt <= 0;
output_trigger_sig <= 1;
multiplication_cnt <= 0;
end
end
2: begin
if(multiplication_cnt < insignal_multiplication_freq_cnt>>1) begin
multiplication_cnt <= multiplication_cnt + freq_multiplication + 1;
if (multiplication_cnt < insignal_multiplication_freq_cnt >> 1) begin
multiplication_cnt <= multiplication_cnt + freq_multiplication + 1;
insignal_multiplication <= 1;
end
else if((multiplication_cnt+freq_multiplication+2) >= insignal_multiplication_freq_cnt) begin
gen_pluse_cnt <= gen_pluse_cnt + 1;
multiplication_cnt <= 0;
output_trigger_sig <= 0;
end else if ((multiplication_cnt + freq_multiplication + 2) >= insignal_multiplication_freq_cnt) begin
gen_pluse_cnt <= gen_pluse_cnt + 1;
multiplication_cnt <= 0;
insignal_multiplication <= 1;
gen_pluse_cnt <= gen_pluse_cnt + 1;
end
else begin
if(gen_pluse_cnt >= freq_multiplication ) begin
multiplication_state <= 1;
output_trigger_sig <= 1;
gen_pluse_cnt <= gen_pluse_cnt + 1;
end else begin
output_trigger_sig <= 0;
if (gen_pluse_cnt >= freq_multiplication) begin
multiplication_state <= 1;
insignal_multiplication <= 0;
multiplication_cnt <= 0;
end
else begin
multiplication_cnt <= multiplication_cnt + freq_multiplication + 1;
multiplication_cnt <= 0;
end else begin
multiplication_cnt <= multiplication_cnt + freq_multiplication + 1;
insignal_multiplication <= 0;
end
end

91
source/src/zutils/zutils_sig_delayer_v2.v
View File

@ -5,17 +5,18 @@
// 2. 相比使用FIFO的方式缓存信号的方式，这个延时模块使用的资源更少。
// 3. 无法延迟非周期短时高频信号。最多缓存3个短时脉冲（缓存脉冲数量与zutils_edge_detecter的实力数量有关）
//
/*
module zutils_sig_delayer_v2 (
input clk,
input rst_n,
input [31:0] delay_cnt,
input [31:0] freq_division,
input in,
output reg out,
output reg ready
);
reg [31:0] delay_cache;
reg internal_reset_sig;
zutils_edge_detecter _signal_in (
@ -31,58 +32,58 @@ module zutils_sig_delayer_v2 (
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (in_signal_rising_edge),
.out_sig (out_sig11),
.out_sig (final_out_sig1),
.gen_pulse(gen_pluse11)
);
zutils_pluse_delayer _pluse_delayer12 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (out_sig11),
.out_sig (out_sig12),
.gen_pulse(gen_pluse12)
);
// zutils_pluse_delayer _pluse_delayer12 (
// .clk (clk),
// .rst_n (internal_reset_sig),
// .delay_cnt(delay_cache),
// .in_sig (out_sig11),
// .out_sig (final_out_sig1),
// .gen_pulse(gen_pluse12)
// );
zutils_pluse_delayer _pluse_delayer13 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (out_sig12),
.out_sig (final_out_sig1),
.gen_pulse(gen_pluse13)
);
// zutils_pluse_delayer _pluse_delayer13 (
// .clk (clk),
// .rst_n (internal_reset_sig),
// .delay_cnt(delay_cache),
// .in_sig (out_sig12),
// .out_sig (final_out_sig1),
// .gen_pulse(gen_pluse13)
// );
zutils_pluse_delayer _pluse_delayer21 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (in_signal_falling_edge),
.out_sig (out_sig21),
.out_sig (final_out_sig2),
.gen_pulse(gen_pluse21)
);
zutils_pluse_delayer _pluse_delayer22 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (out_sig21),
.out_sig (out_sig22),
.gen_pulse(gen_pluse22)
);
// zutils_pluse_delayer _pluse_delayer22 (
// .clk (clk),
// .rst_n (internal_reset_sig),
// .delay_cnt(delay_cache),
// .in_sig (out_sig21),
// .out_sig (final_out_sig2),
// .gen_pulse(gen_pluse22)
// );
zutils_pluse_delayer _pluse_delayer23 (
.clk (clk),
.rst_n (internal_reset_sig),
.delay_cnt(delay_cache),
.in_sig (out_sig22),
.out_sig (final_out_sig2),
.gen_pulse(gen_pluse23)
);
// zutils_pluse_delayer _pluse_delayer23 (
// .clk (clk),
// .rst_n (internal_reset_sig),
// .delay_cnt(delay_cache),
// .in_sig (out_sig22),
// .out_sig (final_out_sig2),
// .gen_pulse(gen_pluse23)
// );
assign final_gen_pluse1 = gen_pluse11 | gen_pluse12 | gen_pluse13;
assign final_gen_pluse2 = gen_pluse21 | gen_pluse22 | gen_pluse23;
assign final_gen_pluse1 = gen_pluse11;
assign final_gen_pluse2 = gen_pluse21;
reg state;
always @(posedge clk or negedge rst_n) begin
@ -122,3 +123,19 @@ module zutils_sig_delayer_v2 (
endmodule
*/
module zutils_sig_delayer_v2 (
input clk,
input rst_n,
input [31:0] delay_cnt,
input in,
output out,
output ready
);
assign ready = 1;
assign out = in;
endmodule