15 changed files with 950 additions and 398 deletions
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108led_test.fdc
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169led_test.pds
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202source/async.v
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44source/led_test.v
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31source/src/baud_rate_gen.v
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24source/src/top.v
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76source/src/transmitter.v
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129source/src/uart_reg_reader.v
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172source/src/uart_rx.v
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161source/src/uart_tx.v
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35source/test.v
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30source/test/test_baud_rate_gen.v
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50source/test/test_top.v
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51source/test/test_transmitter.v
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66source/test/test_uart_reg_reader.v
@ -1,202 +0,0 @@ |
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//////////////////////////////////////////////////////// |
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// RS-232 RX and TX module |
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// (c) fpga4fun.com & KNJN LLC - 2003 to 2016 |
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// The RS-232 settings are fixed |
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// TX: 8-bit data, 2 stop, no-parity |
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// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course) |
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//`define SIMULATION // in this mode, TX outputs one bit per clock cycle |
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// and RX receives one bit per clock cycle (for fast simulations) |
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//////////////////////////////////////////////////////// |
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module async_transmitter( |
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input clk, |
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input TxD_start, |
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input [7:0] TxD_data, |
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output TxD, |
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output TxD_busy |
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); |
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// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data |
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// TxD_data is latched so that it doesn't have to stay valid while it is being sent |
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parameter ClkFrequency = 50000000; // 50MHz |
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parameter Baud = 115200; |
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generate |
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if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate"); |
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endgenerate |
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//////////////////////////////// |
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`ifdef SIMULATION |
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wire BitTick = 1'b1; // output one bit per clock cycle |
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`else |
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wire BitTick; |
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BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick)); |
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`endif |
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reg [3:0] TxD_state = 0; |
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wire TxD_ready = (TxD_state==0); |
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assign TxD_busy = ~TxD_ready; |
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reg [7:0] TxD_shift = 0; |
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always @(posedge clk) |
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begin |
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if(TxD_ready & TxD_start) |
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TxD_shift <= TxD_data; |
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else |
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if(TxD_state[3] & BitTick) |
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TxD_shift <= (TxD_shift >> 1); |
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case(TxD_state) |
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4'b0000: if(TxD_start) TxD_state <= 4'b0100; |
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4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit |
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4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0 |
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4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1 |
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4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2 |
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4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3 |
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4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4 |
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4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5 |
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4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6 |
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4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7 |
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4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1 |
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4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2 |
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default: if(BitTick) TxD_state <= 4'b0000; |
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endcase |
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end |
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assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits |
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endmodule |
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//////////////////////////////////////////////////////// |
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module async_receiver( |
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input clk, |
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input RxD, |
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output reg RxD_data_ready = 0, |
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output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted |
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// We also detect if a gap occurs in the received stream of characters |
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// That can be useful if multiple characters are sent in burst |
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// so that multiple characters can be treated as a "packet" |
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output RxD_idle, // asserted when no data has been received for a while |
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output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high) |
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); |
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parameter ClkFrequency = 25000000; // 25MHz |
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parameter Baud = 115200; |
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parameter Oversampling = 8; // needs to be a power of 2 |
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// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time |
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// 8 times oversampling by default, use 16 for higher quality reception |
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generate |
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if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling"); |
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if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value"); |
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endgenerate |
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//////////////////////////////// |
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reg [3:0] RxD_state = 0; |
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`ifdef SIMULATION |
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wire RxD_bit = RxD; |
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wire sampleNow = 1'b1; // receive one bit per clock cycle |
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`else |
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wire OversamplingTick; |
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BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick)); |
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// synchronize RxD to our clk domain |
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reg [1:0] RxD_sync = 2'b11; |
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always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD}; |
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// and filter it |
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reg [1:0] Filter_cnt = 2'b11; |
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reg RxD_bit = 1'b1; |
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always @(posedge clk) |
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if(OversamplingTick) |
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begin |
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if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1; |
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else |
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if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1; |
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if(Filter_cnt==2'b11) RxD_bit <= 1'b1; |
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else |
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if(Filter_cnt==2'b00) RxD_bit <= 1'b0; |
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end |
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// and decide when is the good time to sample the RxD line |
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function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction |
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localparam l2o = log2(Oversampling); |
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reg [l2o-2:0] OversamplingCnt = 0; |
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always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1; |
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wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1); |
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`endif |
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// now we can accumulate the RxD bits in a shift-register |
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always @(posedge clk) |
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case(RxD_state) |
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4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found? |
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4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow |
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4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0 |
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4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1 |
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4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2 |
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4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3 |
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4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4 |
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4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5 |
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4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6 |
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4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7 |
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4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit |
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default: RxD_state <= 4'b0000; |
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endcase |
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always @(posedge clk) |
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if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]}; |
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//reg RxD_data_error = 0; |
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always @(posedge clk) |
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begin |
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RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received |
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//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received |
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end |
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`ifdef SIMULATION |
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assign RxD_idle = 0; |
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`else |
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reg [l2o+1:0] GapCnt = 0; |
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always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1; |
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assign RxD_idle = GapCnt[l2o+1]; |
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always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0]; |
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`endif |
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endmodule |
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//////////////////////////////////////////////////////// |
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// dummy module used to be able to raise an assertion in Verilog |
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module ASSERTION_ERROR(); |
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endmodule |
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//////////////////////////////////////////////////////// |
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module BaudTickGen( |
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input clk, enable, |
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output tick // generate a tick at the specified baud rate * oversampling |
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); |
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parameter ClkFrequency = 25000000; |
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parameter Baud = 115200; |
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parameter Oversampling = 1; |
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function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction |
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localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte |
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reg [AccWidth:0] Acc = 0; |
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localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow |
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localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter); |
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always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0]; |
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assign tick = Acc[AccWidth]; |
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endmodule |
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//////////////////////////////////////////////////////// |
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@ -1,44 +0,0 @@ |
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`timescale 1ns/1ns |
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module led_test |
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( |
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sys_clk, // system clock 50Mhz on board |
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rst_n, // reset ,low active |
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led // LED,use for control the LED signal on board |
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); |
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input sys_clk; |
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input rst_n; |
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output [3:0] led; |
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//define the time counter |
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reg [31:0] timer; |
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reg [3:0] led; |
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always @(posedge sys_clk or negedge rst_n) |
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begin |
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if (~rst_n) |
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timer <= 32'd0; // when the reset signal valid,time counter clearing |
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else if (timer == 32'd199_9999_9) //4 seconds count(50M*4-1=199999999) |
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timer <= 32'd0; //count done,clearing the time counter |
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else |
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timer <= timer + 1'b1; //timer counter = timer counter + 1 |
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end |
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always @(posedge sys_clk or negedge rst_n) |
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begin |
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if (~rst_n) |
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led <= 4'b0000; //when the reset signal active |
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else if (timer == 32'd49_999_9) //time counter count to 1st sec,LED1 Extinguish |
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led <= 4'b0001; |
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else if (timer == 32'd99_999_9) //time counter count to 2nd sec,LED2 Extinguish |
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begin |
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led <= 4'b0010; |
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end |
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else if (timer == 32'd149_999_9) //time counter count to 3nd sec,LED3 Extinguish |
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led <= 4'b0100; |
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else if (timer == 32'd199_999_9) //time counter count to 4nd sec,LED4 Extinguish |
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led <= 4'b1000; |
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end |
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endmodule |
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@ -0,0 +1,31 @@ |
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/* |
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* Hacky baud rate generator to divide a 50MHz clock into a 115200 baud |
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* rx/tx pair where the rx clcken oversamples by 16x. |
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*/ |
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module baud_rate_gen ( |
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input wire clk_50m, |
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output wire rxclk_en, |
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output wire txclk_en |
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); |
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parameter RX_ACC_MAX = 50000000 / (115200 * 16); |
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parameter TX_ACC_MAX = 50000000 / 115200; |
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parameter RX_ACC_WIDTH = $clog2(RX_ACC_MAX); |
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parameter TX_ACC_WIDTH = $clog2(TX_ACC_MAX); |
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reg [RX_ACC_WIDTH - 1:0] rx_acc = 0; |
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reg [TX_ACC_WIDTH - 1:0] tx_acc = 0; |
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assign rxclk_en = (rx_acc == 5'd0); |
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assign txclk_en = (tx_acc == 9'd0); |
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always @(posedge clk_50m) begin |
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if (rx_acc == RX_ACC_MAX[RX_ACC_WIDTH-1:0]) rx_acc <= 0; |
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else rx_acc <= rx_acc + 5'b1; |
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end |
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always @(posedge clk_50m) begin |
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if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH-1:0]) tx_acc <= 0; |
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else tx_acc <= tx_acc + 9'b1; |
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end |
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endmodule |
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@ -0,0 +1,24 @@ |
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`timescale 1ns / 1ns |
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module Top ( |
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input sys_clk, |
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input rst_n, |
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output reg [3:0] led, |
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output wire test_io3, |
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output wire test_io4, |
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output wire test_io5, |
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output wire test_io6, |
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output wire test_io7, |
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output wire test_io8, |
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output wire test_io9, |
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output wire test_io10, |
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output wire test_io11, |
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output wire test_io12, |
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output wire test_io13, |
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output wire test_io14, |
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output wire test_io15, |
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output wire test_io16 |
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); |
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endmodule |
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@ -0,0 +1,76 @@ |
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module transmitter ( |
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input wire [7:0] din, |
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input wire wr_en, |
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input wire clk_50m, |
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input wire clken, |
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input wire rest_n, |
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output reg tx, |
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output wire tx_busy, |
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output wire [1:0] t_state, |
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output wire [2:0] t_bitpos, |
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output wire t_worksignal |
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); |
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parameter STATE_IDLE = 2'b00; |
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parameter STATE_START = 2'b01; |
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parameter STATE_DATA = 2'b10; |
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parameter STATE_STOP = 2'b11; |
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initial begin |
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tx = 1'b1; |
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end |
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reg [7:0] data = 8'h00; |
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reg [2:0] bitpos = 3'h0; |
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reg [1:0] state = STATE_IDLE; |
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reg worksignal = 0; |
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assign workflag = (state != STATE_IDLE); |
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always @(posedge clken, posedge wr_en) begin |
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if (wr_en) begin |
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worksignal <= 1'b1; |
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data <= din; |
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end else begin |
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if (!workflag) worksignal <= 1'b0; |
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end |
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end |
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always @(posedge clken or negedge rest_n) begin |
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if (!rest_n) begin |
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state <= STATE_IDLE; |
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end else begin |
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case (state) |
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STATE_IDLE: begin |
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tx <= 1'b1; |
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if (worksignal) begin |
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state <= STATE_START; |
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bitpos <= 0; |
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end |
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end |
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STATE_START: begin |
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tx <= 1'b0; |
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state <= STATE_DATA; |
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end |
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STATE_DATA: begin |
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if (bitpos == 3'h7) state <= STATE_STOP; |
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else bitpos <= bitpos + 3'h1; |
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tx <= data[bitpos]; |
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end |
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STATE_STOP: begin |
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tx <= 1'b1; |
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state <= STATE_IDLE; |
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end |
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default begin |
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tx <= 1'b1; |
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state <= STATE_IDLE; |
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end |
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endcase |
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end |
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end |
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assign tx_busy = (state != STATE_IDLE); |
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assign t_state = state; |
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assign t_bitpos = bitpos; |
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assign t_worksignal = worksignal; |
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endmodule |
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@ -0,0 +1,129 @@ |
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module uart_reg_reader #( |
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parameter CLK_FRE = 50, //clock frequency(Mhz) |
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parameter BAUD_RATE = 115200 //serial baud rate |
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) ( |
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input clk, //clock input |
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input rst_n, //asynchronous reset input, low active |
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input wire [31:0] reg_data, //received serial data |
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output reg [ 7:0] reg_add, |
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output reg reg_add_valid, |
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input wire uart_rx_pin, |
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output wire uart_tx_pin |
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); |
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// |
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// overtime |
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// |----------------------^ |
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// v | |
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// IDLE ---------------> READ REG ADD ---------------> READ_REG ---------------> SEND_REG_DATA |
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// ^ | |
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// |------------------------------------------------------------------------------------v |
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// |
||||
|
// |
||||
|
// |
||||
|
// |
||||
|
|
||||
|
parameter STATE_IDLE = 0; |
||||
|
parameter STATE_READ_REG_ADD = 1; |
||||
|
parameter STATE_READ_REG = 2; |
||||
|
parameter STATE_SEND_REG_DATA = 3; |
||||
|
parameter STATE_WAIT_SEND_END = 4; |
||||
|
|
||||
|
|
||||
|
|
||||
|
wire [7:0] rx_data; |
||||
|
wire rx_data_valid; |
||||
|
wire rx_data_ready; |
||||
|
|
||||
|
wire tx_data_ready; |
||||
|
reg [7:0] tx_data; |
||||
|
reg tx_data_valid; |
||||
|
|
||||
|
reg [7:0] state; |
||||
|
reg [7:0] rxpacket_num; |
||||
|
reg [7:0] txpacket_num; |
||||
|
reg [7:0] rxdatacache; //接收数据buffer |
||||
|
|
||||
|
uart_rx #( |
||||
|
.CLK_FRE (CLK_FRE), |
||||
|
.BAUD_RATE(BAUD_RATE) |
||||
|
) uart_rx_impl ( |
||||
|
.clk (clk), // input |
||||
|
.rst_n (rst_n), // input |
||||
|
.rx_data (rx_data), // output |
||||
|
.rx_data_valid(rx_data_valid), // output |
||||
|
.rx_data_ready(rx_data_ready), // input |
||||
|
.rx_pin (uart_rx_pin) // input |
||||
|
); |
||||
|
|
||||
|
uart_tx #( |
||||
|
.CLK_FRE (CLK_FRE), |
||||
|
.BAUD_RATE(BAUD_RATE) |
||||
|
) uart_tx_impl ( |
||||
|
.clk (clk), // input |
||||
|
.rst_n (rst_n), // input |
||||
|
.tx_data (tx_data), // input |
||||
|
.tx_data_valid(tx_data_valid), // input |
||||
|
.tx_data_ready(tx_data_ready), // output |
||||
|
.tx_pin (uart_tx_pin) // output |
||||
|
); |
||||
|
|
||||
|
|
||||
|
assign rx_data_ready = 1'b1; |
||||
|
|
||||
|
reg [3:0] txdatastep = 0; |
||||
|
always @(posedge clk or negedge rst_n) begin |
||||
|
if (!rst_n) begin |
||||
|
state <= STATE_IDLE; |
||||
|
rxpacket_num <= 0; |
||||
|
txpacket_num <= 0; |
||||
|
txdatastep <= 0; |
||||
|
end else begin |
||||
|
case (state) |
||||
|
STATE_IDLE: begin |
||||
|
rxpacket_num <= 0; |
||||
|
txpacket_num <= 0; |
||||
|
txdatastep <= 0; |
||||
|
state <= STATE_READ_REG_ADD; |
||||
|
end |
||||
|
STATE_READ_REG_ADD: begin |
||||
|
if (rxpacket_num == 1) begin |
||||
|
state <= STATE_READ_REG; |
||||
|
end else if (rx_data_valid) begin |
||||
|
rxdatacache <= rx_data; |
||||
|
rxpacket_num <= rxpacket_num + 1; |
||||
|
end |
||||
|
end |
||||
|
STATE_READ_REG: begin |
||||
|
state <= STATE_SEND_REG_DATA; |
||||
|
end |
||||
|
STATE_SEND_REG_DATA: begin |
||||
|
case (txdatastep) |
||||
|
0: begin |
||||
|
tx_data <= rxdatacache; |
||||
|
tx_data_valid <= 1; |
||||
|
txpacket_num <= txpacket_num + 1; |
||||
|
txdatastep <= 1; |
||||
|
end |
||||
|
1: begin |
||||
|
tx_data_valid <= 0; |
||||
|
txdatastep <= 2; |
||||
|
end |
||||
|
2: begin |
||||
|
if (tx_data_ready) begin |
||||
|
if (txpacket_num != 4) begin |
||||
|
txdatastep <= 0; |
||||
|
end else begin |
||||
|
txdatastep <= 0; |
||||
|
state <= STATE_IDLE; |
||||
|
end |
||||
|
end |
||||
|
end |
||||
|
endcase |
||||
|
end |
||||
|
default begin |
||||
|
state <= STATE_IDLE; |
||||
|
end |
||||
|
endcase |
||||
|
end |
||||
|
end |
||||
|
endmodule |
||||
@ -0,0 +1,172 @@ |
|||||
|
////////////////////////////////////////////////////////////////////////////////// |
||||
|
// // |
||||
|
// // |
||||
|
// Author: meisq // |
||||
|
// msq@qq.com // |
||||
|
// ALINX(shanghai) Technology Co.,Ltd // |
||||
|
// heijin // |
||||
|
// WEB: http://www.alinx.cn/ // |
||||
|
// BBS: http://www.heijin.org/ // |
||||
|
// // |
||||
|
////////////////////////////////////////////////////////////////////////////////// |
||||
|
// // |
||||
|
// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd // |
||||
|
// All rights reserved // |
||||
|
// // |
||||
|
// This source file may be used and distributed without restriction provided // |
||||
|
// that this copyright statement is not removed from the file and that any // |
||||
|
// derivative work contains the original copyright notice and the associated // |
||||
|
// disclaimer. // |
||||
|
// // |
||||
|
////////////////////////////////////////////////////////////////////////////////// |
||||
|
|
||||
|
//================================================================================ |
||||
|
// Revision History: |
||||
|
// Date By Revision Change Description |
||||
|
//-------------------------------------------------------------------------------- |
||||
|
//2017/8/1 1.0 Original |
||||
|
//*******************************************************************************/ |
||||
|
module uart_rx |
||||
|
#( |
||||
|
parameter CLK_FRE = 50, //clock frequency(Mhz) |
||||
|
parameter BAUD_RATE = 115200 //serial baud rate |
||||
|
) |
||||
|
( |
||||
|
input clk, //clock input |
||||
|
input rst_n, //asynchronous reset input, low active |
||||
|
output reg[7:0] rx_data, //received serial data |
||||
|
output reg rx_data_valid, //received serial data is valid |
||||
|
input rx_data_ready, //data receiver module ready |
||||
|
input rx_pin //serial data input |
||||
|
); |
||||
|
//calculates the clock cycle for baud rate |
||||
|
localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE; |
||||
|
//state machine code |
||||
|
localparam S_IDLE = 1; |
||||
|
localparam S_START = 2; //start bit |
||||
|
localparam S_REC_BYTE = 3; //data bits |
||||
|
localparam S_STOP = 4; //stop bit |
||||
|
localparam S_DATA = 5; |
||||
|
|
||||
|
reg[2:0] state; |
||||
|
reg[2:0] next_state; |
||||
|
reg rx_d0; //delay 1 clock for rx_pin |
||||
|
reg rx_d1; //delay 1 clock for rx_d0 |
||||
|
wire rx_negedge; //negedge of rx_pin |
||||
|
reg[7:0] rx_bits; //temporary storage of received data |
||||
|
reg[15:0] cycle_cnt; //baud counter |
||||
|
reg[2:0] bit_cnt; //bit counter |
||||
|
|
||||
|
assign |
||||
|
rx_negedge = rx_d1 && ~rx_d0; |
||||
|
|
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
begin |
||||
|
rx_d0 <= 1'b0; |
||||
|
rx_d1 <= 1'b0; |
||||
|
end |
||||
|
else |
||||
|
begin |
||||
|
rx_d0 <= rx_pin; |
||||
|
rx_d1 <= rx_d0; |
||||
|
end |
||||
|
end |
||||
|
|
||||
|
|
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
state <= S_IDLE; |
||||
|
else |
||||
|
state <= next_state; |
||||
|
end |
||||
|
|
||||
|
always@(*) |
||||
|
begin |
||||
|
case(state) |
||||
|
S_IDLE: |
||||
|
if(rx_negedge) |
||||
|
next_state <= S_START; |
||||
|
else |
||||
|
next_state <= S_IDLE; |
||||
|
S_START: |
||||
|
if(cycle_cnt == CYCLE - 1)//one data cycle |
||||
|
next_state <= S_REC_BYTE; |
||||
|
else |
||||
|
next_state <= S_START; |
||||
|
S_REC_BYTE: |
||||
|
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) //receive 8bit data |
||||
|
next_state <= S_STOP; |
||||
|
else |
||||
|
next_state <= S_REC_BYTE; |
||||
|
S_STOP: |
||||
|
if(cycle_cnt == CYCLE/2 - 1)//half bit cycle,to avoid missing the next byte receiver |
||||
|
next_state <= S_DATA; |
||||
|
else |
||||
|
next_state <= S_STOP; |
||||
|
S_DATA: |
||||
|
if(rx_data_ready) //data receive complete |
||||
|
next_state <= S_IDLE; |
||||
|
else |
||||
|
next_state <= S_DATA; |
||||
|
default: |
||||
|
next_state <= S_IDLE; |
||||
|
endcase |
||||
|
end |
||||
|
|
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
rx_data_valid <= 1'b0; |
||||
|
else if(state == S_STOP && next_state != state) |
||||
|
rx_data_valid <= 1'b1; |
||||
|
else if(state == S_DATA && rx_data_ready) |
||||
|
rx_data_valid <= 1'b0; |
||||
|
end |
||||
|
|
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
rx_data <= 8'd0; |
||||
|
else if(state == S_STOP && next_state != state) |
||||
|
rx_data <= rx_bits;//latch received data |
||||
|
end |
||||
|
|
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
begin |
||||
|
bit_cnt <= 3'd0; |
||||
|
end |
||||
|
else if(state == S_REC_BYTE) |
||||
|
if(cycle_cnt == CYCLE - 1) |
||||
|
bit_cnt <= bit_cnt + 3'd1; |
||||
|
else |
||||
|
bit_cnt <= bit_cnt; |
||||
|
else |
||||
|
bit_cnt <= 3'd0; |
||||
|
end |
||||
|
|
||||
|
|
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
cycle_cnt <= 16'd0; |
||||
|
else if((state == S_REC_BYTE && cycle_cnt == CYCLE - 1) || next_state != state) |
||||
|
cycle_cnt <= 16'd0; |
||||
|
else |
||||
|
cycle_cnt <= cycle_cnt + 16'd1; |
||||
|
end |
||||
|
//receive serial data bit data |
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
rx_bits <= 8'd0; |
||||
|
else if(state == S_REC_BYTE && cycle_cnt == CYCLE/2 - 1) |
||||
|
rx_bits[bit_cnt] <= rx_pin; |
||||
|
else |
||||
|
rx_bits <= rx_bits; |
||||
|
end |
||||
|
endmodule |
||||
@ -0,0 +1,161 @@ |
|||||
|
////////////////////////////////////////////////////////////////////////////////// |
||||
|
// // |
||||
|
// // |
||||
|
// Author: meisq // |
||||
|
// msq@qq.com // |
||||
|
// ALINX(shanghai) Technology Co.,Ltd // |
||||
|
// heijin // |
||||
|
// WEB: http://www.alinx.cn/ // |
||||
|
// BBS: http://www.heijin.org/ // |
||||
|
// // |
||||
|
////////////////////////////////////////////////////////////////////////////////// |
||||
|
// // |
||||
|
// Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd // |
||||
|
// All rights reserved // |
||||
|
// // |
||||
|
// This source file may be used and distributed without restriction provided // |
||||
|
// that this copyright statement is not removed from the file and that any // |
||||
|
// derivative work contains the original copyright notice and the associated // |
||||
|
// disclaimer. // |
||||
|
// // |
||||
|
////////////////////////////////////////////////////////////////////////////////// |
||||
|
|
||||
|
//================================================================================ |
||||
|
// Revision History: |
||||
|
// Date By Revision Change Description |
||||
|
//-------------------------------------------------------------------------------- |
||||
|
//2017/8/1 1.0 Original |
||||
|
//*******************************************************************************/ |
||||
|
module uart_tx |
||||
|
#( |
||||
|
parameter CLK_FRE = 50, //clock frequency(Mhz) |
||||
|
parameter BAUD_RATE = 115200 //serial baud rate |
||||
|
) |
||||
|
( |
||||
|
input clk, //clock input |
||||
|
input rst_n, //asynchronous reset input, low active |
||||
|
input[7:0] tx_data, //data to send |
||||
|
input tx_data_valid, //data to be sent is valid |
||||
|
output reg tx_data_ready, //send ready |
||||
|
output tx_pin //serial data output |
||||
|
); |
||||
|
//calculates the clock cycle for baud rate |
||||
|
localparam CYCLE = CLK_FRE * 1000000 / BAUD_RATE; |
||||
|
//state machine code |
||||
|
localparam S_IDLE = 1; |
||||
|
localparam S_START = 2;//start bit |
||||
|
localparam S_SEND_BYTE = 3;//data bits |
||||
|
localparam S_STOP = 4;//stop bit |
||||
|
reg[2:0] state; |
||||
|
reg[2:0] next_state; |
||||
|
reg[15:0] cycle_cnt; //baud counter |
||||
|
reg[2:0] bit_cnt;//bit counter |
||||
|
reg[7:0] tx_data_latch; //latch data to send |
||||
|
reg tx_reg; //serial data output |
||||
|
assign tx_pin = tx_reg; |
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
state <= S_IDLE; |
||||
|
else |
||||
|
state <= next_state; |
||||
|
end |
||||
|
|
||||
|
always@(*) |
||||
|
begin |
||||
|
case(state) |
||||
|
S_IDLE: |
||||
|
if(tx_data_valid == 1'b1) |
||||
|
next_state <= S_START; |
||||
|
else |
||||
|
next_state <= S_IDLE; |
||||
|
S_START: |
||||
|
if(cycle_cnt == CYCLE - 1) |
||||
|
next_state <= S_SEND_BYTE; |
||||
|
else |
||||
|
next_state <= S_START; |
||||
|
S_SEND_BYTE: |
||||
|
if(cycle_cnt == CYCLE - 1 && bit_cnt == 3'd7) |
||||
|
next_state <= S_STOP; |
||||
|
else |
||||
|
next_state <= S_SEND_BYTE; |
||||
|
S_STOP: |
||||
|
if(cycle_cnt == CYCLE - 1) |
||||
|
next_state <= S_IDLE; |
||||
|
else |
||||
|
next_state <= S_STOP; |
||||
|
default: |
||||
|
next_state <= S_IDLE; |
||||
|
endcase |
||||
|
end |
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
begin |
||||
|
tx_data_ready <= 1'b0; |
||||
|
end |
||||
|
else if(state == S_IDLE) |
||||
|
if(tx_data_valid == 1'b1) |
||||
|
tx_data_ready <= 1'b0; |
||||
|
else |
||||
|
tx_data_ready <= 1'b1; |
||||
|
else if(state == S_STOP && cycle_cnt == CYCLE - 1) |
||||
|
tx_data_ready <= 1'b1; |
||||
|
end |
||||
|
|
||||
|
|
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
begin |
||||
|
tx_data_latch <= 8'd0; |
||||
|
end |
||||
|
else if(state == S_IDLE && tx_data_valid == 1'b1) |
||||
|
tx_data_latch <= tx_data; |
||||
|
|
||||
|
end |
||||
|
|
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
begin |
||||
|
bit_cnt <= 3'd0; |
||||
|
end |
||||
|
else if(state == S_SEND_BYTE) |
||||
|
if(cycle_cnt == CYCLE - 1) |
||||
|
bit_cnt <= bit_cnt + 3'd1; |
||||
|
else |
||||
|
bit_cnt <= bit_cnt; |
||||
|
else |
||||
|
bit_cnt <= 3'd0; |
||||
|
end |
||||
|
|
||||
|
|
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
cycle_cnt <= 16'd0; |
||||
|
else if((state == S_SEND_BYTE && cycle_cnt == CYCLE - 1) || next_state != state) |
||||
|
cycle_cnt <= 16'd0; |
||||
|
else |
||||
|
cycle_cnt <= cycle_cnt + 16'd1; |
||||
|
end |
||||
|
|
||||
|
always@(posedge clk or negedge rst_n) |
||||
|
begin |
||||
|
if(rst_n == 1'b0) |
||||
|
tx_reg <= 1'b1; |
||||
|
else |
||||
|
case(state) |
||||
|
S_IDLE,S_STOP: |
||||
|
tx_reg <= 1'b1; |
||||
|
S_START: |
||||
|
tx_reg <= 1'b0; |
||||
|
S_SEND_BYTE: |
||||
|
tx_reg <= tx_data_latch[bit_cnt]; |
||||
|
default: |
||||
|
tx_reg <= 1'b1; |
||||
|
endcase |
||||
|
end |
||||
|
|
||||
|
endmodule |
||||
@ -1,35 +0,0 @@ |
|||||
`timescale 1ns / 1ns |
|
||||
////////////////////////////////////////////////////////////////////////////////// |
|
||||
// Module Name: vtf_led_test |
|
||||
////////////////////////////////////////////////////////////////////////////////// |
|
||||
|
|
||||
module vtf_led_test; |
|
||||
// Inputs |
|
||||
reg sys_clk; |
|
||||
reg rst_n; |
|
||||
|
|
||||
// Outputs |
|
||||
wire [3:0] led; |
|
||||
|
|
||||
// Instantiate the Unit Under Test (UUT) |
|
||||
led_test uut ( |
|
||||
.sys_clk(sys_clk), |
|
||||
.rst_n(rst_n), |
|
||||
.led(led) |
|
||||
); |
|
||||
|
|
||||
initial begin |
|
||||
// Initialize Inputs |
|
||||
sys_clk = 0; |
|
||||
rst_n = 0; |
|
||||
|
|
||||
// Wait 100 ns for global reset to finish |
|
||||
#1000; |
|
||||
rst_n = 1; |
|
||||
// Add stimulus here |
|
||||
#20000; |
|
||||
// $stop; |
|
||||
end |
|
||||
|
|
||||
always #10 sys_clk = ~ sys_clk; //20ns |
|
||||
endmodule |
|
||||
@ -0,0 +1,30 @@ |
|||||
|
`timescale 1ns / 1ns |
||||
|
module test_baud_rate_gen; |
||||
|
// Inputs |
||||
|
reg clk_50m; |
||||
|
reg rst_n; |
||||
|
|
||||
|
wire rxclk_en; |
||||
|
wire txclk_en; |
||||
|
|
||||
|
baud_rate_gen baud_rate_gen_impl ( |
||||
|
.clk_50m (clk_50m), |
||||
|
.rxclk_en(rxclk_en), |
||||
|
.txclk_en(txclk_en) |
||||
|
); |
||||
|
|
||||
|
initial begin |
||||
|
// Initialize Inputs |
||||
|
clk_50m = 0; |
||||
|
rst_n = 0; |
||||
|
|
||||
|
#100; |
||||
|
rst_n = 1; |
||||
|
|
||||
|
#15; |
||||
|
|
||||
|
#100000; |
||||
|
$stop; |
||||
|
end |
||||
|
always #10 clk_50m = ~clk_50m; //20ns 50MHZ |
||||
|
endmodule |
||||
@ -0,0 +1,50 @@ |
|||||
|
`timescale 1ns / 1ns |
||||
|
module test_top; |
||||
|
// Inputs |
||||
|
reg clk_50m; |
||||
|
reg rst_n; |
||||
|
|
||||
|
wire rxclk_en; |
||||
|
wire txclk_en; |
||||
|
|
||||
|
wire [3:0] led; |
||||
|
wire test_io3; |
||||
|
wire test_io4; |
||||
|
wire test_io5; |
||||
|
wire test_io6; |
||||
|
wire test_io7; |
||||
|
wire test_io8; |
||||
|
wire test_io9; |
||||
|
wire test_io10; |
||||
|
wire test_io11; |
||||
|
|
||||
|
Top top_impl ( |
||||
|
.sys_clk(clk_50m), |
||||
|
.rst_n(rst_n), |
||||
|
.led(led), |
||||
|
.test_io3(test_io3), |
||||
|
.test_io4(test_io4), |
||||
|
.test_io5(test_io5), |
||||
|
.test_io6(test_io6), |
||||
|
.test_io7(test_io7), |
||||
|
.test_io8(test_io8), |
||||
|
.test_io9(test_io9), |
||||
|
.test_io10(test_io10), |
||||
|
.test_io11(test_io11) |
||||
|
); |
||||
|
|
||||
|
initial begin |
||||
|
// Initialize Inputs |
||||
|
clk_50m = 0; |
||||
|
rst_n = 0; |
||||
|
|
||||
|
#100; |
||||
|
rst_n = 1; |
||||
|
|
||||
|
#15; |
||||
|
|
||||
|
#300000; |
||||
|
$stop; |
||||
|
end |
||||
|
always #10 clk_50m = ~clk_50m; //20ns 50MHZ |
||||
|
endmodule |
||||
@ -0,0 +1,51 @@ |
|||||
|
`timescale 1ns / 1ns |
||||
|
module test_transmitter; |
||||
|
// Inputs |
||||
|
reg clk_50m; |
||||
|
reg rst_n; |
||||
|
|
||||
|
|
||||
|
reg [7:0] din; |
||||
|
reg wr_en; |
||||
|
wire tx; |
||||
|
wire tx_busy; |
||||
|
|
||||
|
wire rxclk_en; |
||||
|
wire txclk_en; |
||||
|
|
||||
|
|
||||
|
baud_rate_gen baud_rate_gen_impl ( |
||||
|
.clk_50m (clk_50m), |
||||
|
.rxclk_en(rxclk_en), |
||||
|
.txclk_en(txclk_en) |
||||
|
); |
||||
|
|
||||
|
transmitter transmitter_impl ( |
||||
|
.din(din), |
||||
|
.wr_en(wr_en), |
||||
|
.clk_50m(clk_50m), |
||||
|
.clken(txclk_en), |
||||
|
.tx(tx), |
||||
|
.tx_busy(tx_busy) |
||||
|
); |
||||
|
|
||||
|
initial begin |
||||
|
// Initialize Inputs |
||||
|
clk_50m = 0; |
||||
|
rst_n = 0; |
||||
|
|
||||
|
#10; |
||||
|
rst_n = 1; |
||||
|
|
||||
|
#11; |
||||
|
din = 8'h55; |
||||
|
wr_en = 1'b1; |
||||
|
|
||||
|
#15; |
||||
|
wr_en = 0; |
||||
|
|
||||
|
#300000; |
||||
|
$stop; |
||||
|
end |
||||
|
always #10 clk_50m = ~clk_50m; //20ns 50MHZ |
||||
|
endmodule |
||||
@ -0,0 +1,66 @@ |
|||||
|
`timescale 1ns / 1ns |
||||
|
module test_uart_reg_reader; |
||||
|
// Inputs |
||||
|
reg clk_50m; |
||||
|
reg rst_n; |
||||
|
|
||||
|
reg [31:0] reg_data; |
||||
|
wire [7:0] reg_add; |
||||
|
wire reg_add_valid; |
||||
|
reg uart_rx_pin; |
||||
|
wire uart_tx_pin; |
||||
|
|
||||
|
uart_reg_reader uart_reg_reader_impl ( |
||||
|
.clk(clk_50m), |
||||
|
.rst_n(rst_n), |
||||
|
.reg_data(reg_data), |
||||
|
.reg_add(reg_add), |
||||
|
.reg_add_valid(reg_add_valid), |
||||
|
.uart_rx_pin(uart_rx_pin), |
||||
|
.uart_tx_pin(uart_tx_pin) |
||||
|
); |
||||
|
|
||||
|
|
||||
|
initial begin |
||||
|
// Initialize Inputs |
||||
|
clk_50m = 0; |
||||
|
rst_n = 0; |
||||
|
reg_data = 0; |
||||
|
uart_rx_pin = 1; |
||||
|
|
||||
|
#10; |
||||
|
rst_n = 1; |
||||
|
|
||||
|
#1000; |
||||
|
uart_rx_pin = 1; |
||||
|
|
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 0; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 1; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 0; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 1; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 0; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 1; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 0; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 1; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 0; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 1; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 0; |
||||
|
#(8.680 * 1000); |
||||
|
uart_rx_pin = 1; |
||||
|
|
||||
|
#(100 * 8.680 * 1000); |
||||
|
$stop; |
||||
|
end |
||||
|
always #10 clk_50m = ~clk_50m; //20ns 50MHZ |
||||
|
endmodule |
||||
Reference in new issue