Pango 06100103 Distributed Shift Register Distributed Shift Register 1.2 ShiftRegister Logos PGL22G MBG324 -6 IP Compiler

DATA_WIDTH 1 SHIFT_REG_TYPE dynamic_latency VARIABLE_MAX_DEPTH 1024 RST_TYPE ASYNC FIXED_DEPTH 1024 SHIFT_REG_TYPE_BOOL true din din input left addr addr input left 9 0 clk clk input left rst rst input left dout dout output right