// Created by IP Generator (Version 2021.1-SP7 build 86875)
// Instantiation Template
//
// Insert the following codes into your Verilog file.
//   * Change the_instance_name to your own instance name.
//   * Change the signal names in the port associations


ShiftRegister the_instance_name (
  .din(din),      // input
  .addr(addr),    // input [9:0]
  .clk(clk),      // input
  .rst(rst),      // input
  .dout(dout)     // output
);