-- Created by IP Generator (Version 2021.1-SP7 build 86875)
-- Instantiation Template
--
-- Insert the following codes into your VHDL file.
--   * Change the_instance_name to your own instance name.
--   * Change the net names in the port map.


COMPONENT ShiftRegister
  PORT (
    din : IN STD_LOGIC;
    addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    clk : IN STD_LOGIC;
    rst : IN STD_LOGIC;
    dout : OUT STD_LOGIC
  );
END COMPONENT;


the_instance_name : ShiftRegister
  PORT MAP (
    din => din,
    addr => addr,
    clk => clk,
    rst => rst,
    dout => dout
  );