IP Generator (Version 2021.1-SP7 build 86875)
Check out license ...
Start generating at 2024-03-20 17:08
Instance: ShiftRegister (D:\workspace\p_lusterinc\xsync_fpge\ipcore\ShiftRegister\ShiftRegister.idf)
IP: Distributed Shift Register (1.2)
Part: Logos-PGL22G-MBG324--6
Create directory 'rtl' ...
Copy 'rtl\ipm_distributed_sdpram_v1_2.v.xml' to 'rtl' ...
Copy 'rtl\ipm_distributed_shiftregister_v1_2.v.xml' to 'rtl' ...
Compile file 'rtl\ipm_distributed_sdpram_v1_2.v.xml' to 'rtl\ipm_distributed_sdpram_v1_2_ShiftRegister.v' ...
Compile file 'rtl\ipm_distributed_shiftregister_v1_2.v.xml' to 'rtl\ipm_distributed_shiftregister_v1_2_ShiftRegister.v' ...
Copy 'ipm_distributed_shiftregister_wrapper_v1_2.v.xml' ...
Copy 'ipm_distributed_shiftregister_wrapper_v1_2_tb.v.xml' ...
Compile file 'ipm_distributed_shiftregister_wrapper_v1_2.v.xml' to 'ShiftRegister.v' ...
Found top module 'ShiftRegister' in file 'ShiftRegister.v'.
Compile file 'ipm_distributed_shiftregister_wrapper_v1_2_tb.v.xml' to 'ShiftRegister_tb.v' ...
Create template file 'ShiftRegister_tmpl.v' ...
Create template file 'ShiftRegister_tmpl.vhdl' ...
There are 3 source files to synthesize.
Synthesis is disabled.
Done: 0 error(s), 0 warning(s)