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15 lines
439 B
15 lines
439 B
// Created by IP Generator (Version 2021.1-SP7 build 86875)
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// Instantiation Template
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//
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// Insert the following codes into your Verilog file.
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// * Change the_instance_name to your own instance name.
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// * Change the signal names in the port associations
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ShiftRegister the_instance_name (
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.din(din), // input
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.addr(addr), // input [9:0]
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.clk(clk), // input
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.rst(rst), // input
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.dout(dout) // output
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);
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