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27 lines
577 B
27 lines
577 B
-- Created by IP Generator (Version 2021.1-SP7 build 86875)
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-- Instantiation Template
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--
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-- Insert the following codes into your VHDL file.
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-- * Change the_instance_name to your own instance name.
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-- * Change the net names in the port map.
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COMPONENT ShiftRegister
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PORT (
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din : IN STD_LOGIC;
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addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
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clk : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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dout : OUT STD_LOGIC
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);
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END COMPONENT;
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the_instance_name : ShiftRegister
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PORT MAP (
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din => din,
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addr => addr,
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clk => clk,
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rst => rst,
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dout => dout
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);
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