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p_lusterinc_xsync
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xsync_fpge
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59
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4.2 MiB
Verilog
99.3%
VHDL
0.7%
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030eb27861
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xsync_fpge
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zhaohe
030eb27861
添加延时模块
1 year ago
..
bak
timecode is ok
1 year ago
src
添加延时模块
1 year ago
test
add timecode input
2 years ago