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p_lusterinc_xsync
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xsync_fpge
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71
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4.2 MiB
Verilog
99.3%
VHDL
0.7%
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250b6ad8a8
master
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xsync_fpge
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zhaohe
250b6ad8a8
V003
1 year ago
..
bak
timecode 添加频率探测功能
1 year ago
src
V003
1 year ago
test
add timecode input
2 years ago