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157 lines
4.4 KiB
157 lines
4.4 KiB
module uart_reg_reader #(
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parameter CLK_FRE = 50, //clock frequency(Mhz)
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parameter BAUD_RATE = 115200 //serial baud rate
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) (
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input clk, //clock input
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input rst_n, //asynchronous reset input, low active
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input wire [31:0] reg_data, //received serial data
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output reg [31:0] reg_add,
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output reg reg_add_valid,
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input wire uart_rx_pin,
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output wire uart_tx_pin
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);
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//
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// overtime
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// |----------------------^
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// v |
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// IDLE ---------------> READ REG ADD ---------------> READ_REG ---------------> SEND_REG_DATA
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// ^ |
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// |------------------------------------------------------------------------------------v
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//
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//
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//
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//
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parameter STATE_IDLE = 0;
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parameter STATE_READ_REG_ADD = 1;
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parameter STATE_READ_REG = 2;
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parameter STATE_SEND_REG_DATA = 3;
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parameter STATE_WAIT_SEND_END = 4;
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wire [7:0] rx_data;
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wire rx_data_valid;
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wire rx_data_ready;
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wire tx_data_ready;
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reg [7:0] tx_data = 0;
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reg tx_data_valid = 0;
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reg [7:0] state = 0;
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reg [7:0] rxpacket_num = 0;
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reg [7:0] txpacket_num = 0;
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reg [7:0] rxdatacache = 0; //接收数据buffer
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uart_rx #(
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.CLK_FRE (CLK_FRE),
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.BAUD_RATE(BAUD_RATE)
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) uart_rx_impl (
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.clk (clk), // input
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.rst_n (rst_n), // input
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.rx_data (rx_data), // output
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.rx_data_valid(rx_data_valid), // output
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.rx_data_ready(rx_data_ready), // input
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.rx_pin (uart_rx_pin) // input
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);
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uart_tx #(
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.CLK_FRE (CLK_FRE),
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.BAUD_RATE(BAUD_RATE)
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) uart_tx_impl (
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.clk (clk), // input
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.rst_n (rst_n), // input
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.tx_data (tx_data), // input
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.tx_data_valid(tx_data_valid), // input
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.tx_data_ready(tx_data_ready), // output
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.tx_pin (uart_tx_pin) // output
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);
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assign rx_data_ready = 1'b1;
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reg [ 7:0] substep = 0;
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reg [31:0] reg_data_cache = 0;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= STATE_IDLE;
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rxpacket_num <= 0;
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txpacket_num <= 0;
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substep <= 0;
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reg_add <= 0;
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reg_add_valid <= 0;
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end else begin
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case (state)
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STATE_IDLE: begin
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rxpacket_num <= 0;
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txpacket_num <= 0;
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substep <= 0;
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state <= STATE_READ_REG_ADD;
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end
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STATE_READ_REG_ADD: begin
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if (rxpacket_num == 1) begin
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state <= STATE_READ_REG;
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end else if (rx_data_valid) begin
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rxdatacache <= rx_data;
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rxpacket_num <= rxpacket_num + 1;
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end
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end
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STATE_READ_REG: begin
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case (substep)
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0: begin
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reg_add_valid <= 1;
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reg_add[7:0] <= rxdatacache;
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substep <= 1;
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end
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1: begin
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tx_data_valid <= 0;
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substep <= 0;
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state <= STATE_SEND_REG_DATA;
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end
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endcase
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end
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STATE_SEND_REG_DATA: begin
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case (substep)
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0: begin
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case (txpacket_num)
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0: begin
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tx_data[7:0] <= reg_data_cache[7:0];
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end
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1: begin
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tx_data[7:0] <= reg_data_cache[15:8];
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end
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2: begin
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tx_data[7:0] <= reg_data_cache[23:16];
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end
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3: begin
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tx_data[7:0] <= reg_data_cache[31:24];
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end
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default: begin
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tx_data[7:0] <= 0;
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end
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endcase
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tx_data_valid <= 1;
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txpacket_num <= txpacket_num + 1;
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substep <= 1;
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end
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1: begin
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tx_data_valid <= 0;
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substep <= 2;
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end
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2: begin
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if (tx_data_ready) begin
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if (txpacket_num != 4) begin
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substep <= 0;
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end else begin
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substep <= 0;
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state <= STATE_IDLE;
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end
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end
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end
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endcase
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end
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default begin
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state <= STATE_IDLE;
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end
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endcase
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end
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end
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endmodule
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