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```https://iflytop1.feishu.cn/docx/Fk3CdIRNZoal1XxCGgjc9q1Dn1f```
```注意事项: 倍频和分频的前提建立在输入频率稳定的情况才有效的。如果输入频率在+-一定范围内变化，输出波形可能会出现异常
```
```核心板引脚分配:
define_attribute {p:rst_n} {PAP_IO_DIRECTION} {INPUT}define_attribute {p:rst_n} {PAP_IO_LOC} {U12}define_attribute {p:rst_n} {PAP_IO_VCCIO} {3.3}define_attribute {p:rst_n} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:sys_clk} {PAP_IO_DIRECTION} {INPUT}define_attribute {p:sys_clk} {PAP_IO_LOC} {B5}define_attribute {p:sys_clk} {PAP_IO_VCCIO} {3.3}define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33}
```
```TTL OUTPUT 1,2,3,4 丝印正确，正常输出
```
```SIGNAL_GENERATOR 启动方式: 1.寄存器控制启动 2.外部触发启动 3.TIMECODE触发启动 帧格式: TIMECODE: 25/30/... GENLOCK: .... 产生: 1.start_state_sig (高电平表示拍照进行中) 2.timecode_sig[64] 3.timecode_tirgger_sig[1] 4.genlock_sig[1] 帧信号,场信号 5.秒信号
TTL_INPUTTIMECODE_INPUTTIMECODE_OUTPUT
GENLOCK_INPUT
```
```1. 修改启动方式2. 修改TIMECODE启动时间戳
```
```
// timeocde[0->63]// 0 1 2 3 4 5 6 7// 帧秒分时 U0U1U2U3
```
```插件: Documenter - TerosHDL 0.1.4 documentation Verilog-HDL/SystemVerilog/Bluespec SystemVerilog```
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