xsync_fpge_v2/source/src/sys_signal_delayer.v

module sys_signal_delayer #(
    parameter REG_START_ADD  = 0,
    parameter SYS_CLOCK_FREQ = 10000000,
    parameter SIG_BUS_WIDTH  = 15
) (

    input clk,   //! 时钟输入
    input rst_n, //! 复位输入

    input       [31:0] addr,     //! 寄存器地址
    input       [31:0] wr_data,  //! 写入数据
    input              wr_en,    //! 写使能
    output wire [31:0] rd_data,  //! 读出数据

    /*******************************************************************************
     *                                输入信号延迟                                 *
     *******************************************************************************/
    input  [SIG_BUS_WIDTH:0] sig_in,
    output [SIG_BUS_WIDTH:0] sig_out
);

  reg  [31:0] r1_ctrl_reg_index;
  reg  [31:0] r2_delay_cnt_ctrl;
  reg  [31:0] delay_ctrl        [SIG_BUS_WIDTH:0];

  wire [31:0] reg_wr_index;
  zutils_register_advanced #(
      .REG_START_ADD(REG_START_ADD)
  ) _register (
      .clk       (clk),
      .rst_n     (rst_n),
      .addr      (addr),
      .wr_data   (wr_data),
      .wr_en     (wr_en),
      .rd_data   (rd_data),
      .reg1      (r1_ctrl_reg_index),
      .reg2      (r2_delay_cnt_ctrl),
      .reg_wr_sig(reg_wr_sig),
      .reg_index (reg_wr_index)
  );

  reg     delayer_rst_n_ctrl;
  integer m;
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      r1_ctrl_reg_index <= 0;
      r2_delay_cnt_ctrl <= delay_ctrl[r1_ctrl_reg_index][31:0];

      for (m = 0; m <= SIG_BUS_WIDTH; m = m + 1) begin
        delay_ctrl[m] <= 0;
      end
      delayer_rst_n_ctrl <= 1;
    end else begin

      case (reg_wr_sig)
        0: begin
          delayer_rst_n_ctrl <= 1;
          // r2_delay_cnt_ctrl  <= delay_ctrl[r1_ctrl_reg_index][31:0];
        end
        1: begin
          delayer_rst_n_ctrl <= 0;
          case (reg_wr_index)
            1: begin
              if (wr_data <= SIG_BUS_WIDTH) begin
                r1_ctrl_reg_index <= wr_data;
                r2_delay_cnt_ctrl <= delay_ctrl[wr_data][31:0];
              end
            end
            2: begin
              delay_ctrl[r1_ctrl_reg_index][31:0] <= wr_data;
              r2_delay_cnt_ctrl                   <= wr_data;
            end
          endcase
        end
      endcase
    end
  end

  assign delayer_rst_n = delayer_rst_n_ctrl & rst_n;
  genvar i;
  generate
    for (i = 0; i <= SIG_BUS_WIDTH; i = i + 1) begin
      zutils_sig_delayer_v2 sig_delayer_inst (
          .clk      (clk),
          .rst_n    (delayer_rst_n),
          .delay_cnt(delay_ctrl[i]),
          .in       (sig_in[i]),
          .out      (sig_out[i])
      );
      // assign sig_out[i] = sig_in[i];
    end
  endgenerate

  // assign sig_out   = sig_in;


endmodule