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`define REGADDOFF__FPGA_INFO 16'h0020`define REGADDOFF__TTLIN 16'h0100`define REGADDOFF__TIMECODE_IN 16'h0120`define REGADDOFF__GENLOCK_IN 16'h0130`define REGADDOFF__INTERNAL_TIMECODE 16'h0300`define REGADDOFF__INTERNAL_GENLOCK 16'h0310`define REGADDOFF__INTERNAL_CLOCK 16'h0320`define REGADDOFF__INTERNAL_SIG_EN_CONTRLER 16'h03A0`define REGADDOFF__TTLOUT1 16'h0200`define REGADDOFF__TTLOUT2 16'h0210`define REGADDOFF__TTLOUT3 16'h0220`define REGADDOFF__TTLOUT4 16'h0230`define REGADDOFF__TIMECODE_OUT 16'h0240`define REGADDOFF__GENLOCK_OUT 16'h0250`define REGADDOFF__CAMERA_SYNC_OUT 16'h0260`define REGADDOFF__SYS_TIMECODE 16'h0400`define REGADDOFF__SYS_GENLOCK 16'h0410`define REGADDOFF__SYS_CLOCK 16'h0420`define REGADDOFF__RECORD_SIG_GENERATOR 16'h0500`define REGADDOFF__DELAYER 16'h0600
`define SIGNAL_LOGIC0 32'd0`define SIGNAL_LOGIC1 32'd1`define SIGNAL_TTLIN1 32'd2`define SIGNAL_TTLIN2 32'd3`define SIGNAL_TTLIN3 32'd4`define SIGNAL_TTLIN4 32'd5`define SIGNAL_EXT_GENLOCK_FREQ 32'd6`define SIGNAL_EXT_TIMECODE_FREQ 32'd7`define SIGNAL_INTERNAL_TIMECODE_FREQ 32'd8`define SIGNAL_INTERNAL_GENLOCK_FREQ 32'd9`define SIGNAL_INTERNAL_CLOCK_SIG 32'd10`define SIGNAL_SYS_CLK_OUTPUT 32'd11`define SIGNAL_SYS_GENLOCK_OUTPUT 32'd12`define SIGNAL_SYS_TIMECODE_FREQ_OUTPUT 32'd13`define SIGNAL_BUSINESS_RECORD_SIG 32'd14`define SIGNAL_BUSINESS_RECORD_EXPOSURE_SIG 32'd15`define SIGNAL_BUSINESS_RECORD_EN_RSING_EDGE_SIG 32'd16`define SIGNAL_BUSINESS_RECORD_EN_FALLING_EDGE_SIG 32'd17`define SIGNAL_BUSINESS_RECORD_EN_EDGE_SIG 32'd18
`define TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH 32'd1000`define FREQ_DETECT_BIAS_DEFAULT 32'd10`define VERSION 32'd3
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