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  1. //
  2. // @功能:
  3. // 1. 功能:同步输出,脉冲输出
  4. // 2. 输出脉冲
  5. // 3. 输出脉冲时长可调
  6. // 4. 输出极性可调
  7. //
  8. module ttl_output #(
  9. parameter REG_START_ADD = 0,
  10. parameter SYS_CLOCK_FREQ = 10000000,
  11. parameter TEST = 0,
  12. parameter ID = 1
  13. ) (
  14. input clk, //clock input
  15. input rst_n, //asynchronous reset input, low active
  16. //寄存器读写接口
  17. input [31:0] addr,
  18. input [31:0] wr_data,
  19. input wr_en,
  20. output wire [31:0] rd_data,
  21. input [31:0] signal_in,
  22. output ttloutput, //ttl输出信号
  23. output ttloutput_state_led //ttl输出状态信号
  24. );
  25. /*******************************************************************************
  26. * 寄存器列表 *
  27. *******************************************************************************/
  28. //
  29. // 输入信号选择器
  30. // 0: 信号0
  31. // 1: 信号1
  32. // ...
  33. // x: 信号x
  34. wire [31:0] reg_input_signal_select;
  35. //
  36. // 输出信号选择器
  37. // [0]
  38. // 0:输出0
  39. // 1:输出1
  40. // 2:测试信号输出
  41. // 3:原始信号
  42. // 4:原始信号翻转输出
  43. // 5:脉冲输出
  44. // 6:脉冲信号翻转输出
  45. localparam REG1_INIT = TEST ? 2 : 0;
  46. wire [31:0] reg_output_signal_select;
  47. //
  48. // 配置寄存器
  49. // [0] 脉冲输入时候触发信号 0:上升沿 1:下降沿触发
  50. //
  51. wire [31:0] reg_config;
  52. assign pluse_input_trigger_signal = reg_config[0];
  53. //
  54. // 脉冲模式-有效电平长度:
  55. // 0~0xffffffff
  56. //
  57. wire [31:0] reg_pulse_mode_valid_len; // 脉冲模式-有效电平长度: 0~0xffffffff
  58. //
  59. // 脉冲模式-触发延时:
  60. // 0~0xffffffff
  61. //
  62. wire [31:0] reg_pulse_mode_trigger_delay; // 脉冲模式-触发延时: 0~0xffffffff
  63. zutils_register16 #(
  64. .REG_START_ADD(REG_START_ADD),
  65. .REG1_INIT(REG1_INIT)
  66. ) _register (
  67. .clk(clk),
  68. .rst_n(rst_n),
  69. .addr(addr),
  70. .wr_data(wr_data),
  71. .wr_en(wr_en),
  72. .rd_data(rd_data),
  73. .reg0(reg_input_signal_select),
  74. .reg1(reg_output_signal_select),
  75. .reg2(reg_config),
  76. .reg3(reg_pulse_mode_valid_len),
  77. .reg4(reg_pulse_mode_trigger_delay)
  78. );
  79. /*******************************************************************************
  80. * 内部信号 *
  81. *******************************************************************************/
  82. //脉冲输出
  83. wire pluse_output;
  84. // 输入信号上升沿事件
  85. wire in_signal_rising_edge;
  86. // 输入信号下降沿事件
  87. wire in_signal_falling_edge;
  88. // 输入信号上升沿或下降沿事件
  89. wire in_signal_edge;
  90. // 输出的脉冲触发信号的触发信号
  91. wire signal_src_trigger;
  92. assign signal_src_trigger = (pluse_input_trigger_signal==0) ? (in_signal_rising_edge) : (in_signal_falling_edge);
  93. wire signal_in_choose;
  94. zutils_multiplexer_32t1 _signal_select (
  95. .chooseindex(reg_input_signal_select),
  96. .signal(signal_in),
  97. .signalout(signal_in_choose)
  98. );
  99. // 边沿检测
  100. zutils_edge_detecter _signal_in (
  101. .clk(clk),
  102. .rst_n(rst_n),
  103. .in_signal(signal_in_choose),
  104. .in_signal_rising_edge(in_signal_rising_edge),
  105. .in_signal_falling_edge(in_signal_falling_edge),
  106. .in_signal_edge(in_signal_edge)
  107. );
  108. // 短脉冲触发生成长脉冲
  109. zutils_pluse_generator _pluse_generator (
  110. .clk(clk),
  111. .rst_n(rst_n),
  112. .pluse_width(reg_pulse_mode_valid_len),
  113. .pluse_delay(reg_pulse_mode_trigger_delay),
  114. .trigger(signal_src_trigger),
  115. .output_signal(ttl_after_process_output)
  116. );
  117. zutils_pwm_generator #(
  118. .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
  119. .OUTPUT_FREQ(1000 * ID)
  120. ) _test_signal_generator (
  121. .clk(clk),
  122. .rst_n(rst_n),
  123. .output_signal(test_signal_output)
  124. );
  125. wire [15:0] signal_output_select_in;
  126. assign signal_output_select_in[0] = 1'b0;
  127. assign signal_output_select_in[1] = 1'b1;
  128. assign signal_output_select_in[2] = test_signal_output;
  129. assign signal_output_select_in[3] = signal_in_choose;
  130. assign signal_output_select_in[4] = !signal_in_choose;
  131. assign signal_output_select_in[5] = ttl_after_process_output;
  132. assign signal_output_select_in[6] = !ttl_after_process_output;
  133. assign signal_output_select_in[7] = 1'b0;
  134. assign signal_output_select_in[15:8] = 8'b0;
  135. zutils_multiplexer_16t1 _signal_output_select (
  136. .chooseindex(reg_output_signal_select),
  137. .signal(signal_output_select_in),
  138. .signalout(ttloutput)
  139. );
  140. // assign ttloutput_state_led = !ttloutput;
  141. assign ttloutput_state_led = 1;
  142. endmodule