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xsync_fpge_v2
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xsync_fpge_v2/impl.tcl

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2 years ago
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  1. #Generated by Fabric Compiler ( version 2021.1-SP7 <build 86875> ) at Fri Dec 8 16:54:29 2023
  3. add_design "D:/workspace/fpga_demo/led_test/source/led_test.v"
  4. set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
  5. compile -top_module led_test
  6. add_constraint "D:/workspace/fpga_demo/led_test/led_test.fdc"
  7. synthesize -ads -selected_syn_tool_opt 2
  8. dev_map
  9. pnr
  10. pnr
  11. pnr
  12. pnr
  13. pnr
  14. pnr
  15. synthesize -ads -selected_syn_tool_opt 2
  16. dev_map
  17. pnr
  18. report_timing
  19. gen_bit_stream
  20. synthesize -ads -selected_syn_tool_opt 2
  21. dev_map
  22. pnr
  23. report_timing
  24. gen_bit_stream
  25. add_design D:/workspace/fpga_demo/led_test/ipcore/clk_wiz_0/clk_wiz_0.idf
  26. add_design D:/workspace/fpga_demo/led_test/ipcore/ram/ram.idf
  27. remove_design -force D:/workspace/fpga_demo/led_test/ipcore/clk_wiz_0/clk_wiz_0.idf
  28. gen_bit_stream
  29. gen_bit_stream
  30. gen_bit_stream
  31. gen_bit_stream
  32. set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
  33. compile -top_module led_test
  34. synthesize -ads -selected_syn_tool_opt 2
  35. dev_map
  36. pnr
  37. report_timing
  38. gen_bit_stream
  39. set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
  40. compile -top_module led_test
  41. synthesize -ads -selected_syn_tool_opt 2
  42. dev_map
  43. pnr
  44. report_timing
  45. gen_bit_stream
  46. set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
  47. compile -top_module led_test
  48. set_arch -family Logos -device PGL22G -speedgrade -6 -package MBG324
  49. compile -top_module led_test
  50. synthesize -ads -selected_syn_tool_opt 2
  51. dev_map
  52. pnr
  53. report_timing
  54. gen_bit_stream
  55. add_simulation "D:/workspace/fpga_demo/led_test/source/vtf_led.test.v"
  56. remove_simulation -force "D:/workspace/fpga_demo/led_test/source/vtf_led.test.v"
  57. add_simulation "D:/workspace/fpga_demo/led_test/source/test.v"
  58. add_design "D:/workspace/fpga_demo/led_test/source/source/async.v"