xsync_fpge_v2/source/led_test.v

`timescale 1ns/1ns
module led_test 
(             
  sys_clk,      // system clock 50Mhz on board
  rst_n,          // reset ,low active            
  led             // LED,use for control the LED signal on board
 );
            
input         sys_clk;
input         rst_n;
output [3:0]  led;

//define the time counter
reg [31:0]   timer;                  
reg [3:0]    led;

          
  always @(posedge sys_clk or negedge rst_n)    
    begin
      if (~rst_n)                           
          timer <= 32'd0;                     // when the reset signal valid,time counter clearing
      else if (timer == 32'd199_9999_9)    //4 seconds count(50M*4-1=199999999)
          timer <= 32'd0;                       //count done,clearing the time counter
      else
		    timer <= timer + 1'b1;            //timer counter = timer counter + 1
    end

  always @(posedge sys_clk or negedge rst_n)   
    begin
      if (~rst_n)                      
          led <= 4'b0000;                  //when the reset signal active         
      else if (timer == 32'd49_999_9)    //time counter count to 1st sec,LED1 Extinguish 
          led <= 4'b0001;                 
      else if (timer == 32'd99_999_9)    //time counter count to 2nd sec,LED2 Extinguish 
      begin
          led <= 4'b0010;                  
      end
      else if (timer == 32'd149_999_9)   //time counter count to 3nd sec,LED3 Extinguish 
          led <= 4'b0100;                                          
      else if (timer == 32'd199_999_9)   //time counter count to 4nd sec,LED4 Extinguish 
          led <= 4'b1000;                         
    end
    
endmodule