xsync_fpge_v2/source/test/test_app_top.v

`timescale 10ns / 10ns
module test_app_top;


  reg        sys_clk;
  reg        sys_rst_n;



  reg        genlock_in_hsync;
  reg        genlock_in_vsync;
  reg        genlock_in_fsync;

  wire [9:0] genlock_out_dac;
  wire       genlock_out_dac_clk;

  reg        sync_ttl_in1;
  reg        sync_ttl_in2;
  reg        sync_ttl_in3;
  reg        sync_ttl_in4;
  wire       sync_ttl_out1;
  wire       sync_ttl_out2;
  wire       sync_ttl_out3;
  wire       sync_ttl_out4;

  reg        timecode_headphone_in;
  wire        timecode_bnc_in;


  wire       timecode_out_bnc;
  wire       timecode_out_bnc_select;

  wire       timecode_out_headphone;
  wire       timecode_out_headphone_select;

  wire       stm32if_start_signal_out;
  wire       stm32if_camera_sync_out;
  wire       stm32if_timecode_sync_out;

  //SPI 串行总线1
  reg        spi1_cs_pin;
  reg        spi1_clk_pin;
  reg        spi1_rx_pin;
  wire       spi1_tx_pin;

  AppTop appTop (
      .sys_clk                      (sys_clk),
      .sys_rst_n                    (sys_rst_n),
      .genlock_in_hsync             (genlock_in_hsync),
      .genlock_in_vsync             (genlock_in_vsync),
      .genlock_in_fsync             (genlock_in_fsync),
      .genlock_out_dac              (genlock_out_dac),
      .genlock_out_dac_clk          (genlock_out_dac_clk),
      .sync_ttl_in1                 (sync_ttl_in1),
      .sync_ttl_in2                 (sync_ttl_in2),
      .sync_ttl_in3                 (sync_ttl_in3),
      .sync_ttl_in4                 (sync_ttl_in4),
      .sync_ttl_out1                (sync_ttl_out1),
      .sync_ttl_out2                (sync_ttl_out2),
      .sync_ttl_out3                (sync_ttl_out3),
      .sync_ttl_out4                (sync_ttl_out4),
      .timecode_headphone_in        (timecode_headphone_in),
      .timecode_bnc_in              (timecode_bnc_in),
      .timecode_out_bnc             (timecode_out_bnc),
      .timecode_out_bnc_select      (timecode_out_bnc_select),
      .timecode_out_headphone       (timecode_out_headphone),
      .timecode_out_headphone_select(timecode_out_headphone_select),
      .stm32if_start_signal_out     (stm32if_start_signal_out),
      .stm32if_camera_sync_out      (stm32if_camera_sync_out),
      .stm32if_timecode_sync_out    (stm32if_timecode_sync_out),
      .spi1_cs_pin                  (spi1_cs_pin),
      .spi1_clk_pin                 (spi1_clk_pin),
      .spi1_rx_pin                  (spi1_rx_pin),
      .spi1_tx_pin                  (spi1_tx_pin)
  );



  initial begin
    sys_clk               = 0;
    sys_rst_n             = 0;


    genlock_in_hsync      = 0;
    genlock_in_vsync      = 0;
    genlock_in_fsync      = 0;
    sync_ttl_in1          = 0;
    sync_ttl_in2          = 0;
    sync_ttl_in3          = 0;
    sync_ttl_in4          = 0;
    timecode_headphone_in = 0;
    // timecode_bnc_in       = 0;
    spi1_cs_pin           = 0;
    spi1_clk_pin          = 0;
    spi1_rx_pin           = 0;




    #100;
    sys_rst_n = 1;

    #100;
  end
  assign timecode_bnc_in = timecode_out_bnc;
  always #5 sys_clk = ~sys_clk;  // 50MHZ时钟
  
endmodule