p_lusterinc_xsync
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xsync_fpge_v2
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v101

master
haoran 10 months ago
parent
1e448b9fac
commit
04a09a0b20
8 changed files with 145 additions and 103 deletions
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  1. 1
      .gitignore
  2. 25
      release/v1.0.1/Top101.bgr
  3. BIN
      release/v1.0.1/Top101.sbit
  4. 2
      source/src/config.v
  5. 2
      source/src/sys/sys_clock.v
  6. 4
      xsync.fdc
  7. 208
      xsync.pds
  8. 6
      xsync.pds.lock

1
.gitignore
View File

@ -21,3 +21,4 @@ out/*
multiseed_summary.csv
constraint_check/constraint_check.ccr
multiseed_summary.csv
temp_projects/

25
release/v1.0.1/Top101.bgr
View File

@ -0,0 +1,25 @@
Generated by Fabric Compiler ( version 2022.2-SP4.2 <build 132111> ) at Fri Oct 11 15:01:50 2024
Start Generating Programming File...
Reading design from DB takes 5.406250 sec.
The bitstream file is "F:/company/FZMotion/LIST/test tool/xsync_fpge_v2/generate_bitstream/Top.sbit"
Generate programming file takes 36.484375 sec.
Generating Programming File done.
Inputs and Outputs :
+------------------------------------------------------------------------------------------------+
| Type | File Name
+------------------------------------------------------------------------------------------------+
| Input | F:/company/FZMotion/LIST/test tool/xsync_fpge_v2/place_route/Top_pnr.adf
| Output | F:/company/FZMotion/LIST/test tool/xsync_fpge_v2/generate_bitstream/Top.sbit
| | F:/company/FZMotion/LIST/test tool/xsync_fpge_v2/generate_bitstream/Top.smsk
| | F:/company/FZMotion/LIST/test tool/xsync_fpge_v2/generate_bitstream/bgr.db
| | F:/company/FZMotion/LIST/test tool/xsync_fpge_v2/generate_bitstream/Top.bgr
+------------------------------------------------------------------------------------------------+
Flow Command: gen_bit_stream -unused_io_status {KEEPER}
Peak memory: 1,243 MB
Total CPU time to gen_bit_stream completion : 0h:0m:56s
Process Total CPU time to gen_bit_stream completion : 0h:0m:56s
Total real time to gen_bit_stream completion : 0h:1m:2s

BIN
release/v1.0.1/Top101.sbit
View File

2
source/src/config.v
View File

@ -43,4 +43,4 @@
`define TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH 32'd1000
`define FREQ_DETECT_BIAS_DEFAULT 32'd10
`define EXT_TIMECODE_FREQ_DETECT_BIAS_DEFAULT 32'd500
`define VERSION 32'h00010000 //32'h main(2byte) sub(1byte) fix(1byte)
`define VERSION 32'h00010001 //32'h main(2byte) sub(1byte) fix(1byte)

2
source/src/sys/sys_clock.v
View File

@ -12,7 +12,7 @@ module sys_clock #(
input wr_en,
output wire [31:0] rd_data,
input [31:0] signal_in,
input [31:0] signal_in,
output sys_clock
);

4
xsync.fdc
View File

@ -119,7 +119,7 @@ define_attribute {p:sync_ttl_in4} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_in4} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_in4} {PAP_IO_NONE} {TRUE}
define_attribute {p:sync_ttl_out1} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {N15}
define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {R14}
define_attribute {p:sync_ttl_out1} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out1} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out1} {PAP_IO_NONE} {TRUE}
@ -140,7 +140,7 @@ define_attribute {p:sync_ttl_out3} {PAP_IO_NONE} {TRUE}
define_attribute {p:sync_ttl_out3} {PAP_IO_DRIVE} {4}
define_attribute {p:sync_ttl_out3} {PAP_IO_SLEW} {SLOW}
define_attribute {p:sync_ttl_out4} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {R14}
define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {N15}
define_attribute {p:sync_ttl_out4} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out4} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out4} {PAP_IO_NONE} {TRUE}

208
xsync.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2022.2-SP4.2"
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Thu Aug 29 10:45:33 2024")
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Fri Oct 11 15:04:45 2024")
(_version "1.1.0")
(_status "initial")
(_project
@ -21,248 +21,248 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-08-28T22:14:00")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_pluse_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_edge_detecter.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_register.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_multiplexer_4t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_debug_led.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_signal_filter.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_clk_parser.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_multiplexer_16t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/output/ttl_output.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_reset_sig_gen.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_multiplexer_2t1.v"
(_format verilog)
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(_timespec "2024-10-11T14:47:56")
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(_format verilog)
(_timespec "2024-08-23T13:36:15")
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)
(_file "source/src/zutils/zutils_muti_debug_signal_gen.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_pwm_generator_advanced.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_register_advanced.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_genlock_clk_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_multiplexer_32t1_v2.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/ztutils_timecode_next_code.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_smpte_timecode_clk_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/timecode/timecode_nextcode.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/timecode/timecode_basesig_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/timecode/timecode_serialization.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/timecode/timecode_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/output/timecode_output.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/input/timecode_input.v"
(_format verilog)
(_timespec "2024-08-28T21:51:29")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/timecode/timecode_decoder.v"
(_format verilog)
(_timespec "2024-08-28T21:53:27")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/timecode/timecode_sample_sig_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/input/ttl_input.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/ztuils_sig_devide.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_signal_filter_advance.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/timecode/timecode_comparator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_freq_detector.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zsimple_pll.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_freq_detector_v2.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_multiplexer_8t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/spi_reg_bus.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/internal/internal_timecode_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/sys/sys_timecode.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/input/genlock_input_module.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/internal/internal_clock_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/internal/internal_genlock_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/sys/sys_genlock.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/sys/sys_clock.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:51:00")
)
(_file "source/src/output/camera_sync_signal_output.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/business/record_sig_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/sys_signal_delayer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_sig_delayer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_sig_delayer_v2.v"
(_format verilog)
(_timespec "2024-08-23T15:51:36")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_pluse_delayer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/internal/internal_sig_generator_en_contrler.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/zutils_timer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/zutils/breathing_lamp.v"
(_format verilog)
(_timespec "2024-08-28T18:42:17")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/src/app_top.v"
(_format verilog)
(_timespec "2024-08-28T18:43:10")
(_timespec "2024-10-11T14:47:56")
)
)
)
(_widget wgt_my_ips_src
(_input
(_ip "ipcore/ShiftRegister/ShiftRegister.idf"
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:55")
(_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v"
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:55")
)
(_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v"
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:55")
)
(_ip_source_item "ipcore/ShiftRegister/ShiftRegister.v"
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:55")
)
)
(_ip "ipcore/SPLL/SPLL.idf"
(_timespec "2024-08-28T18:24:17")
(_timespec "2024-10-11T14:47:55")
(_ip_source_item "ipcore/SPLL/SPLL.v"
(_timespec "2024-08-28T18:24:17")
(_timespec "2024-10-11T14:47:55")
)
)
)
@ -271,7 +271,7 @@
(_input
(_file "xsync.fdc"
(_format fdc)
(_timespec "2024-08-29T10:30:35")
(_timespec "2024-10-11T14:52:40")
)
)
)
@ -287,31 +287,31 @@
(_input
(_file "source/test/test_transmitter.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/test/test_baud_rate_gen.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/test/test_top.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/test/test_uart_reg_reader.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/test/test_spi_reg_reader.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/test/test_timecode_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
(_file "source/test/test_timecode_decoder.v" + "test_timecode_decoder:"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
(_timespec "2024-10-11T14:47:56")
)
)
)
@ -322,17 +322,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-08-29T10:35:00")
(_timespec "2024-10-11T14:54:12")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-08-29T10:35:00")
(_timespec "2024-10-11T14:54:12")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-08-29T10:35:00")
(_timespec "2024-10-11T14:54:12")
)
)
)
@ -347,25 +347,25 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-08-29T10:35:36")
(_timespec "2024-10-11T14:56:03")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-08-29T10:35:38")
(_timespec "2024-10-11T14:56:14")
)
(_file "synthesize/Top_controlsets.txt"
(_format text)
(_timespec "2024-08-29T10:35:33")
(_timespec "2024-10-11T14:55:41")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-08-29T10:35:40")
(_timespec "2024-10-11T14:56:19")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-08-29T10:35:40")
(_timespec "2024-10-11T14:56:18")
)
)
)
@ -386,21 +386,21 @@
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-08-29T10:35:53")
(_timespec "2024-10-11T14:56:49")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-08-29T10:35:48")
(_timespec "2024-10-11T14:56:36")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-08-29T10:35:53")
(_timespec "2024-10-11T14:56:49")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-08-29T10:35:53")
(_timespec "2024-10-11T14:56:49")
)
)
)
@ -409,7 +409,7 @@
(_input
(_file "device_map/xsync.pcf"
(_format pcf)
(_timespec "2024-08-29T10:35:53")
(_timespec "2024-10-11T14:56:49")
)
)
)
@ -430,33 +430,33 @@
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-08-29T10:43:27")
(_timespec "2024-10-11T15:01:22")
)
)
(_output
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-08-29T10:42:42")
(_timespec "2024-10-11T15:00:59")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-08-29T10:39:28")
(_timespec "2024-10-11T14:58:53")
)
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-08-29T10:43:28")
(_timespec "2024-10-11T15:01:23")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-08-29T10:42:42")
(_timespec "2024-10-11T15:00:59")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-08-29T10:43:27")
(_timespec "2024-10-11T15:01:23")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-08-29T10:43:28")
(_timespec "2024-10-11T15:01:23")
)
)
)
@ -467,9 +467,25 @@
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2024-10-11T15:04:40")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2024-10-11T15:04:44")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2024-10-11T15:04:44")
)
)
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
@ -492,19 +508,19 @@
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-08-29T10:45:29")
(_timespec "2024-10-11T15:02:23")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-08-29T10:45:30")
(_timespec "2024-10-11T15:02:24")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-08-29T10:45:33")
(_timespec "2024-10-11T15:02:27")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-08-29T10:45:33")
(_timespec "2024-10-11T15:02:27")
)
)
)

6
xsync.pds.lock
View File

@ -1,5 +1,5 @@
17672
22316
pds
ZHAOHE
f8caf121-d1d2-4c26-8a45-7e1d59cde8b6
DESKTOP-DNDSG5J
a2f5fbc6-b66a-4527-b91e-8f227e346271
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