diff --git a/README.md b/README.md index 719b432..401e5dd 100644 --- a/README.md +++ b/README.md @@ -17,9 +17,6 @@ define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33} ``` ``` -SPI2_CS 48 R2_13_N V14 -SPI2_MOSI 50 R2_13_P U14 -SPI2_SCK 54 R2_2_N V13 -SPI2_MISO 56 R2_2_P U13 - +TTL OUTPUT + 1,3,4 丝印正确，正常输出 ``` \ No newline at end of file diff --git a/led_test.pds b/led_test.pds index 511a28e..3fa527c 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 18:56:57 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Mon Jan 8 21:14:56 2024") (_version "1.0.5") (_status "initial") (_project @@ -19,7 +19,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-08T18:55:46") + (_timespec "2024-01-08T21:14:35") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -35,7 +35,7 @@ ) (_file "source/src/zutils/zutils_register.v" (_format verilog) - (_timespec "2024-01-08T18:05:38") + (_timespec "2024-01-08T19:03:09") ) (_file "source/src/zutils/zutils_multiplexer_4t1.v" (_format verilog) @@ -59,11 +59,11 @@ ) (_file "source/src/output/ttl_output.v" (_format verilog) - (_timespec "2024-01-08T15:16:56") + (_timespec "2024-01-08T20:10:41") ) (_file "source/src/zutils/zutils_pwm_generator.v" (_format verilog) - (_timespec "2024-01-08T17:43:42") + (_timespec "2024-01-08T19:25:32") ) (_file "source/src/rd_data_router.v" (_format verilog) @@ -109,7 +109,7 @@ ) (_file "source/test/test_top.v" + "test_top:" (_format verilog) - (_timespec "2024-01-08T18:12:26") + (_timespec "2024-01-08T19:17:37") ) (_file "source/test/test_uart_reg_reader.v" (_format verilog) @@ -128,17 +128,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-08T18:56:31") + (_timespec "2024-01-08T21:14:39") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-08T18:56:31") + (_timespec "2024-01-08T21:14:39") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-08T18:56:31") + (_timespec "2024-01-08T21:14:39") ) ) ) @@ -154,21 +154,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-01-08T18:56:35") + (_timespec "2024-01-08T21:14:41") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-01-08T18:56:35") + (_timespec "2024-01-08T21:14:41") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-01-08T18:56:35") + (_timespec "2024-01-08T21:14:41") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-08T18:56:36") + (_timespec "2024-01-08T21:14:41") ) ) ) @@ -189,21 +189,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-01-08T18:56:38") + (_timespec "2024-01-08T21:14:44") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-01-08T18:56:38") + (_timespec "2024-01-08T21:14:44") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-01-08T18:56:38") + (_timespec "2024-01-08T21:14:44") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-01-08T18:56:38") + (_timespec "2024-01-08T21:14:44") ) ) ) @@ -212,7 +212,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-01-08T18:56:38") + (_timespec "2024-01-08T21:14:44") ) ) ) @@ -226,33 +226,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-01-08T18:56:46") + (_timespec "2024-01-08T21:14:48") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-01-08T18:56:46") + (_timespec "2024-01-08T21:14:48") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-01-08T18:56:46") + (_timespec "2024-01-08T21:14:48") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-01-08T18:56:46") + (_timespec "2024-01-08T21:14:47") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-01-08T18:56:44") + (_timespec "2024-01-08T21:14:47") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-01-08T18:56:46") + (_timespec "2024-01-08T21:14:48") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-01-08T18:56:47") + (_timespec "2024-01-08T21:14:48") ) ) ) @@ -268,17 +268,17 @@ (_db_output (_file "report_timing/Top_rtp.adf" (_format adif) - (_timespec "2024-01-08T18:56:51") + (_timespec "2024-01-08T21:14:51") ) ) (_output (_file "report_timing/Top.rtr" (_format text) - (_timespec "2024-01-08T18:56:51") + (_timespec "2024-01-08T21:14:51") ) (_file "report_timing/rtr.db" (_format text) - (_timespec "2024-01-08T18:56:51") + (_timespec "2024-01-08T21:14:52") ) ) ) @@ -302,19 +302,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-01-08T18:56:56") + (_timespec "2024-01-08T21:14:56") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-01-08T18:56:56") + (_timespec "2024-01-08T21:14:56") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-01-08T18:56:56") + (_timespec "2024-01-08T21:14:56") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-01-08T18:56:57") + (_timespec "2024-01-08T21:14:56") ) ) ) diff --git a/source/src/debuger.v b/source/src/debuger.v new file mode 100644 index 0000000..a781cca --- /dev/null +++ b/source/src/debuger.v @@ -0,0 +1,29 @@ +/* + * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud + * rx/tx pair where the rx clcken oversamples by 16x. + */ +module rd_data_router ( + input [31:0] addr, + + input [31:0] stm32_rd_data, + input [31:0] fpga_test_rd_data, + input [31:0] control_sensor_rd_data, + input [31:0] ttlin1_rd_data, + input [31:0] ttlin2_rd_data, + input [31:0] ttlin3_rd_data, + input [31:0] ttlin4_rd_data, + input [31:0] timecode_in_rd_data, + input [31:0] genlock_in_rd_data, + input [31:0] ttlout1_rd_data, + input [31:0] ttlout2_rd_data, + input [31:0] ttlout3_rd_data, + input [31:0] ttlout4_rd_data, + input [31:0] timecode_out_rd_data, + input [31:0] genlock_out_rd_data, + input [31:0] stm32_if_rd_data, + input [31:0] debuger_rd_data, + + output reg [31:0] rd_data_out +); + +endmodule \ No newline at end of file diff --git a/source/src/output/ttl_output.v b/source/src/output/ttl_output.v index 176d6be..6c12bcd 100644 --- a/source/src/output/ttl_output.v +++ b/source/src/output/ttl_output.v @@ -7,7 +7,8 @@ // module ttl_output #( parameter REG_START_ADD = 0, - parameter TEST = 0 + parameter TEST = 0, + parameter ID = 1 ) ( input clk, //clock input input rst_n, //asynchronous reset input, low active @@ -124,7 +125,7 @@ module ttl_output #( zutils_pwm_generator #( .SYS_CLOCK_FREQ(50000000), - .OUTPUT_FREQ(1000) + .OUTPUT_FREQ(1000 * ID) ) _test_signal_generator ( .clk(clk), .rst_n(rst_n), @@ -132,21 +133,24 @@ module ttl_output #( ); + + wire [15:0] signal_output_select_in; + assign signal_output_select_in[0] = 1'b0; + assign signal_output_select_in[1] = 1'b1; + assign signal_output_select_in[2] = test_signal_output; + assign signal_output_select_in[3] = signal_in_choose; + assign signal_output_select_in[4] = !signal_in_choose; + assign signal_output_select_in[5] = ttl_after_process_output; + assign signal_output_select_in[6] = !ttl_after_process_output; + assign signal_output_select_in[7] = 1'b0; + assign signal_output_select_in[15:8] = 8'b0; + zutils_multiplexer_16t1 _signal_output_select ( .chooseindex(reg_output_signal_select), - .signal({ - 8'b0, - /*7*/ 0, - /*6*/ 0, - /*5*/ ttl_after_process_output, - /*4*/ !ttl_after_process_output, - /*3*/ signal_in_choose, - /*2*/ test_signal_output, - /*1*/ 1, - /*0*/ 0 - }), + .signal(signal_output_select_in), .signalout(ttloutput) ); - assign ttloutput_state_led = ttloutput; + // assign ttloutput_state_led = !ttloutput; + assign ttloutput_state_led = 1; endmodule diff --git a/source/src/top.v b/source/src/top.v index 671fe8c..058b2d4 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -148,13 +148,13 @@ module Top ( /******************************************************************************* * DEBUG_LED * *******************************************************************************/ - zutils_debug_led #( - .PERIOD_COUNT(10000000) - ) core_board_debug_led_inst ( - .clk(sys_clk), - .rst_n(rst_n), - .debug_led(core_board_debug_led) - ); + // zutils_debug_led #( + // .PERIOD_COUNT(10000000) + // ) core_board_debug_led_inst ( + // .clk(sys_clk), + // .rst_n(rst_n), + // .debug_led(core_board_debug_led) + // ); /******************************************************************************* * SPIREADER * @@ -220,11 +220,12 @@ module Top ( * 输出组件 * *******************************************************************************/ - // wire [7:0] ttl_output_signal_in; + wire [7:0] ttl_output_signal_in; // ttl_output #( // .REG_START_ADD(`REG_ADD_OFF_TTLIN1), - // .TEST(HARDWARE_TEST_MODE) + // .TEST(HARDWARE_TEST_MODE), + // .ID(1) // ) ttl_output_1 ( // .clk (sys_clk), // .rst_n(rst_n), @@ -242,7 +243,8 @@ module Top ( // ttl_output #( // .REG_START_ADD(`REG_ADD_OFF_TTLIN2), - // .TEST(HARDWARE_TEST_MODE) + // .TEST(HARDWARE_TEST_MODE), + // .ID(2) // ) ttl_output_2 ( // .clk (sys_clk), // .rst_n(rst_n), @@ -260,7 +262,8 @@ module Top ( // ttl_output #( // .REG_START_ADD(`REG_ADD_OFF_TTLIN3), - // .TEST(HARDWARE_TEST_MODE) + // .TEST(HARDWARE_TEST_MODE), + // .ID(3) // ) ttl_output_3 ( // .clk (sys_clk), // .rst_n(rst_n), @@ -278,7 +281,8 @@ module Top ( // ttl_output #( // .REG_START_ADD(`REG_ADD_OFF_TTLIN4), - // .TEST(HARDWARE_TEST_MODE) + // .TEST(HARDWARE_TEST_MODE), + // .ID(4) // ) ttl_output_4 ( // .clk (sys_clk), // .rst_n(rst_n), @@ -295,28 +299,39 @@ module Top ( // ); - rd_data_router rd_data_router_inst ( - .addr(reg_reader_bus_addr), +// rd_data_router rd_data_router_inst ( +// .addr(reg_reader_bus_addr), + +// .stm32_rd_data(stm32_rd_data), +// .fpga_test_rd_data(fpga_test_rd_data), +// .control_sensor_rd_data(control_sensor_rd_data), +// .ttlin1_rd_data(ttlin1_rd_data), +// .ttlin2_rd_data(ttlin2_rd_data), +// .ttlin3_rd_data(ttlin3_rd_data), +// .ttlin4_rd_data(ttlin4_rd_data), +// .timecode_in_rd_data(timecode_in_rd_data), +// .genlock_in_rd_data(genlock_in_rd_data), + +// .ttlout1_rd_data(ttlout1_rd_data), // ok +// .ttlout2_rd_data(ttlout2_rd_data), // ok +// .ttlout3_rd_data(ttlout3_rd_data), // ok +// .ttlout4_rd_data(ttlout4_rd_data), // ok + +// .timecode_out_rd_data(timecode_out_rd_data), +// .genlock_out_rd_data(genlock_out_rd_data), +// .stm32_if_rd_data(stm32_if_rd_data), +// .debuger_rd_data(debuger_rd_data), + +// .rd_data_out(reg_reader_bus_rd_data) +// ); + assign fpga_test_rd_data = reg_reader_bus_rd_data; + + assign debug_signal_output[0] = spi2_cs_pin; + assign debug_signal_output[1] = spi2_clk_pin; + assign debug_signal_output[2] = spi2_rx_pin; + assign debug_signal_output[3] = spi2_tx_pin; + assign core_board_debug_led = 1; + - .stm32_rd_data(stm32_rd_data), - .fpga_test_rd_data(fpga_test_rd_data), - .control_sensor_rd_data(control_sensor_rd_data), - .ttlin1_rd_data(ttlin1_rd_data), - .ttlin2_rd_data(ttlin2_rd_data), - .ttlin3_rd_data(ttlin3_rd_data), - .ttlin4_rd_data(ttlin4_rd_data), - .timecode_in_rd_data(timecode_in_rd_data), - .genlock_in_rd_data(genlock_in_rd_data), - .ttlout1_rd_data(ttlout1_rd_data), // ok - .ttlout2_rd_data(ttlout2_rd_data), // ok - .ttlout3_rd_data(ttlout3_rd_data), // ok - .ttlout4_rd_data(ttlout4_rd_data), // ok - .timecode_out_rd_data(timecode_out_rd_data), - .genlock_out_rd_data(genlock_out_rd_data), - .stm32_if_rd_data(stm32_if_rd_data), - .debuger_rd_data(debuger_rd_data), - - .rd_data_out(reg_reader_bus_rd_data) - ); endmodule diff --git a/source/src/zutils/zutils_pwm_generator.v b/source/src/zutils/zutils_pwm_generator.v index d55efb5..ae30e69 100644 --- a/source/src/zutils/zutils_pwm_generator.v +++ b/source/src/zutils/zutils_pwm_generator.v @@ -20,11 +20,17 @@ module zutils_pwm_generator #( output_signal <= 0; end else begin if (counter == 0) begin - counter <= COUNT - 1; output_signal <= 1; - end else begin - counter <= counter - 1; + counter <= counter + 1; + end else if (counter == COUNT / 2) begin + output_signal <= 0; + counter <= counter + 1; + end else if (counter == COUNT) begin output_signal <= 0; + counter <= 0; + end else begin + output_signal <= output_signal; + counter <= counter + 1; end end end diff --git a/source/src/zutils/zutils_register.v b/source/src/zutils/zutils_register.v index 22301e5..1f15c0e 100644 --- a/source/src/zutils/zutils_register.v +++ b/source/src/zutils/zutils_register.v @@ -66,6 +66,25 @@ module zutils_register16 #( assign regE = data[14]; assign regF = data[15]; + initial begin + data[0] <= REG0_INIT; + data[1] <= REG1_INIT; + data[2] <= REG2_INIT; + data[3] <= REG3_INIT; + data[4] <= REG4_INIT; + data[5] <= REG5_INIT; + data[6] <= REG6_INIT; + data[7] <= REG7_INIT; + data[8] <= REG8_INIT; + data[9] <= REG9_INIT; + data[10] <= REGA_INIT; + data[11] <= REGB_INIT; + data[12] <= REGC_INIT; + data[13] <= REGD_INIT; + data[14] <= REGE_INIT; + data[15] <= REGF_INIT; + end + integer i; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin diff --git a/source/test/test_top.v b/source/test/test_top.v index 78c40a6..c515a29 100644 --- a/source/test/test_top.v +++ b/source/test/test_top.v @@ -10,6 +10,18 @@ module test_top; reg spi2_tx_pin; wire spi2_rx_pin; + wire sync_ttl_out1; + wire sync_ttl_out1_state_led; + + wire sync_ttl_out2; + wire sync_ttl_out2_state_led; + + wire sync_ttl_out3; + wire sync_ttl_out3_state_led; + + wire sync_ttl_out4; + wire sync_ttl_out4_state_led; + initial begin spi2_cs_pin = 1; spi2_clk_pin = 1; @@ -54,12 +66,18 @@ module test_top; .spi2_cs_pin (spi2_cs_pin), .spi2_clk_pin(spi2_clk_pin), .spi2_rx_pin (spi2_tx_pin), - .spi2_tx_pin (spi2_rx_pin) - - ); - + .spi2_tx_pin (spi2_rx_pin), + .sync_ttl_out1(sync_ttl_out1), + .sync_ttl_out1_state_led(sync_ttl_out1_state_led), + .sync_ttl_out2(sync_ttl_out2), + .sync_ttl_out2_state_led(sync_ttl_out2_state_led), + .sync_ttl_out3(sync_ttl_out3), + .sync_ttl_out3_state_led(sync_ttl_out3_state_led), + .sync_ttl_out4(sync_ttl_out4), + .sync_ttl_out4_state_led(sync_ttl_out4_state_led) + ); initial begin sys_clk = 0; @@ -78,6 +96,9 @@ module test_top; spi_write_reg(16'h0021, 32'h00000020); spi_write_reg(16'h0022, 32'h00000200); spi_write_reg(16'h0023, 32'h00002000); + + #100000000; + $stop; end always #1 sys_clk = ~sys_clk; // 50MHZ时钟 endmodule