Browse Source

v106

master
zhaohe 9 months ago
parent
commit
1c699be709
  1. 2
      README.md
  2. BIN
      release/v1.0.6.7z
  3. BIN
      release/v1.0.6/xsync_v106.sbit
  4. BIN
      release/v1.0.6/xsync_v106.sfc
  5. 2
      source/src/config.v
  6. 4
      source/src/internal/internal_sig_generator_en_contrler.v
  7. 52
      xsync.pds

2
README.md

@ -28,6 +28,8 @@ cfg_gen_sfc -device_name W25Q128Q -opcode 107 -sbit_start_address 0 -sbit ./gene
v1.0.5
1. 修复timecode识别出错的BUG(为什么能修复不知道)
2. 优化系统总线相关代码
v1.0.6
1. 开机默认timecode不启动
```

BIN
release/v1.0.6.7z

BIN
release/v1.0.6/xsync_v106.sbit

BIN
release/v1.0.6/xsync_v106.sfc

2
source/src/config.v

@ -43,4 +43,4 @@
`define TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH 32'd1000
`define FREQ_DETECT_BIAS_DEFAULT 32'd10
`define EXT_TIMECODE_FREQ_DETECT_BIAS_DEFAULT 32'd5000
`define VERSION 32'h00010005 //32'h main(2byte) sub(1byte) fix(1byte)
`define VERSION 32'h00010006 //32'h main(2byte) sub(1byte) fix(1byte)

4
source/src/internal/internal_sig_generator_en_contrler.v

@ -37,8 +37,8 @@ module internal_sig_generator_en_contrler #(
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
r1_en <= 32'hFFFF_FFFF;
// r1_en <= 32'h0;
// r1_en <= 32'hFFFF_FFFF;
r1_en <= 32'h0;
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)

52
xsync.pds

@ -1,5 +1,5 @@
(_flow fab_demo "2022.2-SP4.2"
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Sun Nov 3 14:19:41 2024")
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Sun Nov 3 17:27:00 2024")
(_version "1.1.0")
(_status "initial")
(_project
@ -229,7 +229,7 @@
)
(_file "source/src/internal/internal_sig_generator_en_contrler.v"
(_format verilog)
(_timespec "2024-11-03T12:54:48")
(_timespec "2024-11-03T17:10:02")
)
(_file "source/src/zutils/zutils_timer.v"
(_format verilog)
@ -334,17 +334,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-11-03T14:04:52")
(_timespec "2024-11-03T17:12:52")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-11-03T14:04:52")
(_timespec "2024-11-03T17:12:52")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-11-03T14:04:52")
(_timespec "2024-11-03T17:12:52")
)
)
)
@ -359,25 +359,25 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-11-03T14:07:59")
(_timespec "2024-11-03T17:15:49")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-11-03T14:08:14")
(_timespec "2024-11-03T17:16:04")
)
(_file "synthesize/Top_controlsets.txt"
(_format text)
(_timespec "2024-11-03T14:07:44")
(_timespec "2024-11-03T17:15:35")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-11-03T14:08:21")
(_timespec "2024-11-03T17:16:12")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-11-03T14:08:21")
(_timespec "2024-11-03T17:16:12")
)
)
)
@ -398,21 +398,21 @@
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-11-03T14:09:25")
(_timespec "2024-11-03T17:16:59")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-11-03T14:08:59")
(_timespec "2024-11-03T17:16:40")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-11-03T14:09:25")
(_timespec "2024-11-03T17:17:00")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-11-03T14:09:25")
(_timespec "2024-11-03T17:17:00")
)
)
)
@ -421,7 +421,7 @@
(_input
(_file "device_map/xsync.pcf"
(_format pcf)
(_timespec "2024-11-03T14:09:25")
(_timespec "2024-11-03T17:17:00")
)
)
)
@ -442,33 +442,33 @@
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-11-03T14:17:48")
(_timespec "2024-11-03T17:25:08")
)
)
(_output
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-11-03T14:16:59")
(_timespec "2024-11-03T17:24:22")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-11-03T14:13:13")
(_timespec "2024-11-03T17:20:44")
)
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-11-03T14:17:49")
(_timespec "2024-11-03T17:25:10")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-11-03T14:16:58")
(_timespec "2024-11-03T17:24:22")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-11-03T14:17:48")
(_timespec "2024-11-03T17:25:09")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-11-03T14:17:49")
(_timespec "2024-11-03T17:25:10")
)
)
)
@ -504,19 +504,19 @@
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-11-03T14:19:36")
(_timespec "2024-11-03T17:26:56")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-11-03T14:19:37")
(_timespec "2024-11-03T17:26:56")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-11-03T14:19:41")
(_timespec "2024-11-03T17:27:00")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-11-03T14:19:41")
(_timespec "2024-11-03T17:27:00")
)
)
)

Loading…
Cancel
Save