forked from p_lusterinc_xsync/xsync_fpge
8 changed files with 30 additions and 177 deletions
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5.gitignore
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111constraint_check/constraint_check.ccr
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39multiseed_summary.csv
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BINrelease/v1.0.0/Topv100.sbit
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BINrelease/v1.0.0/Topv100.sfc
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52xsync.pds
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##### Written on 2024/08/29 09:31:59 ############################### |
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##### INFO ################################################## |
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Current device : |
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PG2L100H-6FBG484 |
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Top Module : |
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Top |
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Constraint File(s) : |
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D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc |
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##### SUMMARY ###################################################### |
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Found 0 error(s), 19 critical warning(s), 15 warning(s), out of 348 constraint(s) |
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Inapplicable constraints(except overwritten constraints): |
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******************************************** |
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define_attribute {p:stm32_rst_n} {PAP_IO_LOC} {AA19} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 12)] | Port stm32_rst_n has been placed at location AA19, whose type is share pin. |
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define_attribute {p:genlock_in_hsync} {PAP_IO_LOC} {M15} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 17)] | Port genlock_in_hsync has been placed at location M15, whose type is share pin. |
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define_attribute {p:genlock_in_vsync} {PAP_IO_LOC} {M16} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 21)] | Port genlock_in_vsync has been placed at location M16, whose type is share pin. |
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define_attribute {p:genlock_in_fsync} {PAP_IO_LOC} {L16} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 25)] | Port genlock_in_fsync has been placed at location L16, whose type is share pin. |
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define_attribute {p:sync_ttl_in3} {PAP_IO_LOC} {M13} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 97)] | Port sync_ttl_in3 has been placed at location M13, whose type is share pin. |
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define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 101)] | Port sync_ttl_in4 has been placed at location L13, whose type is share pin. |
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define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {N14} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 111)] | Port sync_ttl_out2 has been placed at location N14, whose type is share pin. |
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define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {R17} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 117)] | Port sync_ttl_out3 has been placed at location R17, whose type is share pin. |
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define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {R14} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 123)] | Port sync_ttl_out4 has been placed at location R14, whose type is share pin. |
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define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 129)] | Port timecode_headphone_in has been placed at location L15, whose type is share pin. |
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define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {L14} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 133)] | Port timecode_bnc_in has been placed at location L14, whose type is share pin. |
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define_attribute {p:timecode_out_bnc} {PAP_IO_LOC} {P17} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 137)] | Port timecode_out_bnc has been placed at location P17, whose type is share pin. |
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define_attribute {p:timecode_out_bnc_select} {PAP_IO_LOC} {R18} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 143)] | Port timecode_out_bnc_select has been placed at location R18, whose type is share pin. |
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define_attribute {p:timecode_out_headphone} {PAP_IO_LOC} {R16} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 149)] | Port timecode_out_headphone has been placed at location R16, whose type is share pin. |
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define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {Y22} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 167)] | Port stm32if_camera_sync_out has been placed at location Y22, whose type is share pin. |
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define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {AB20} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 173)] | Port stm32if_timecode_sync_out has been placed at location AB20, whose type is share pin. |
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define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {P14} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 183)] | Port spi1_clk_pin has been placed at location P14, whose type is share pin. |
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define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {P15} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 187)] | Port spi1_rx_pin has been placed at location P15, whose type is share pin. |
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define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {P16} |
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C: ConstraintEditor-2002: [D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc(line number: 191)] | Port spi1_tx_pin has been placed at location P16, whose type is share pin. |
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Constraints with issues: |
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******************************************** |
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Issues without commands: |
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******************************************** |
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Unconstrained ports: |
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******************************************** |
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W: ConstraintEditor-4019: Port 'genlock_in_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'genlock_out_dac[9]' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'genlock_out_dac_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'sync_ttl_in1_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'sync_ttl_in2_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'sync_ttl_in3_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'sync_ttl_in4_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'sync_ttl_out1_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'sync_ttl_out2_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'sync_ttl_out3_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'sync_ttl_out4_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'timecode_bnc_in_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'timecode_headphone_in_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'timecode_out_bnc_state_led' unspecified I/O constraint. |
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W: ConstraintEditor-4019: Port 'timecode_out_headphone_state_led' unspecified I/O constraint. |
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Constraints with matching wildcard expressions: |
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******************************************** |
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@ -1,39 +0,0 @@ |
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version,2022.2-SP4.2<build 132111> |
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project name,xsync.pds |
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Single Seed: |
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Seed,State,Convergence,Setup(Slow),Setup(Fast),Hold(Slow),Hold(Fast),Recovery(Slow),Recovery(Fast),Removal(Slow),Removal(Fast),PBM-GP,PBM-PreGP,PBM-PostGP,LP,Total Placement Cpu Time,Detailed routing,Total Routing Cpu Time,Wire Length After Post-GP,Wire Length After LP,Wire Length After DP,Routing Arc Length,Worst Slack After GP Timing,Worst Slack After LP Timing,Worst Slack Before RP,Worst Slack Before DP,Worst Slack After DP,Worst Slack After Placement,Worst Slack After TA By Preroute,TNS After DP,TNS Before Route,Setup(Slow) Total Failing TNS,Setup(Slow) Total Failing Endpoints,Hold(Slow) Total Failing THS,Hold(Slow) Total Failing Endpoints,Power |
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single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,0.48,55.33,10.75,15.23,NA,NA,NA,195954,NA,NA,991796,991796,991796,991796,NA,0,0,NA,NA,NA,NA,NA |
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Pass Rate/Convergence Rate,0.00%,0.00% |
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Synthesize: |
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control_set,424 |
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Synthesize Performance Summary: |
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slack category,Synthesize Setup WNS,Synthesize Setup TNS,Synthesize Recovery WNS,Synthesize Recovery TNS |
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slack value,992.726,0.000,996.032,0.000 |
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Synthesize Process Cpu Time,0h:0m:19s |
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Device Map: |
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Device Map Resource Usage Summary: |
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Logic Utilization,LUT,FF,DRM,APM,Distributed RAM,HSSTHP,USCM,HCKB,RCKB |
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Used,12576,10121,0,0,0,NA,1,0,0 |
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Available,66600,133200,155,240,19900,NA,32,96,24 |
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Utilization(%),19%,8%,0%,0%,0%,NA,4%,0%,0% |
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Device Map Process Cpu Time,0h:0m:32s |
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Project Configurations: |
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top module,Top |
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compile, |
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synthesize," -ads " |
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device map, |
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place & route," -gplace_seed 8 |
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-seed_step 4 |
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-saved_outcome 4 |
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-parallel 4 |
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-share_router_control_signal false |
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-check_clk_net_route_by_srb false |
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-fix_hold_violation_in_route false " |
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Test Parameters Configurations: |
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testparam, |
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