p_lusterinc_xsync
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xsync_fpge_v2
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V003

master
zhaohe 1 year ago
parent
555e55c3bb
commit
250b6ad8a8
7 changed files with 91 additions and 25 deletions
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  1. 6
      led_test.fdc
  2. 102
      led_test.pds
  3. BIN
      release/v0.0.3/Top.sbit
  4. BIN
      release/v0.0.3/Top.sfc
  5. BIN
      release/v0.0.3/Top003.sbit
  6. BIN
      release/v0.0.3/Top003.sfc
  7. 8
      source/src/top.v

6
led_test.fdc
View File

@ -576,6 +576,6 @@ define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:sync_ttl_in1} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:sync_ttl_in2} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:sync_ttl_in3} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:sync_ttl_in4} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:timecode_bnc_in} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:timecode_headphone_in} {PAP_IO_PULLDW} {TRUE}
define_attribute {p:sync_ttl_in4} {PAP_IO_NONE} {TRUE}
define_attribute {p:timecode_bnc_in} {PAP_IO_NONE} {TRUE}
define_attribute {p:timecode_headphone_in} {PAP_IO_NONE} {TRUE}

102
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Mar 29 13:15:57 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Mar 29 14:58:03 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-27T15:36:20")
(_timespec "2024-03-29T14:52:17")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -264,7 +264,7 @@
(_input
(_file "led_test.fdc"
(_format fdc)
(_timespec "2024-03-27T14:50:54")
(_timespec "2024-03-29T14:52:06")
)
)
)
@ -315,17 +315,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-03-29T13:13:19")
(_timespec "2024-03-29T14:52:35")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-03-29T13:13:15")
(_timespec "2024-03-29T14:52:32")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-03-29T13:13:19")
(_timespec "2024-03-29T14:52:35")
)
)
)
@ -341,21 +341,21 @@
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-03-29T13:15:34")
(_timespec "2024-03-29T14:53:10")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-03-29T13:15:42")
(_timespec "2024-03-29T14:53:12")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-03-29T13:15:49")
(_timespec "2024-03-29T14:53:13")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-03-29T13:15:49")
(_timespec "2024-03-29T14:53:13")
)
)
)
@ -376,21 +376,21 @@
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-03-29T13:15:57")
(_timespec "2024-03-29T14:53:19")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-03-29T13:15:54")
(_timespec "2024-03-29T14:53:16")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-03-29T13:15:57")
(_timespec "2024-03-29T14:53:19")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-03-29T13:15:57")
(_timespec "2024-03-29T14:53:19")
)
)
)
@ -399,7 +399,7 @@
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-03-29T13:15:57")
(_timespec "2024-03-29T14:53:19")
)
)
)
@ -409,7 +409,7 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
@ -417,6 +417,38 @@
(_option share_router_control_signal (_boolean FALSE))
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option fix_hold_violation_in_route (_boolean FALSE))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-29T14:57:34")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-29T14:57:34")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-29T14:57:34")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-29T14:57:34")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-29T14:56:04")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-29T14:57:34")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-29T14:57:35")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -425,8 +457,24 @@
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_attribute _auto_exe_lock (_switch OFF))
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2024-03-29T14:57:43")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2024-03-29T14:57:43")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2024-03-29T14:57:44")
)
)
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
@ -444,8 +492,26 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option unused_io_status (_string "KEEPER"))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-03-29T14:58:03")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-03-29T14:58:03")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-03-29T14:58:03")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-03-29T14:58:03")
)
)
)
)
)

BIN
release/v0.0.3/Top.sbit
View File

BIN
release/v0.0.3/Top.sfc
View File

BIN
release/v0.0.3/Top003.sbit
View File

BIN
release/v0.0.3/Top003.sfc
View File

8
source/src/top.v
View File

@ -277,7 +277,7 @@ module Top (
assign sys_sig_delay_in[0] = sync_ttl_in1; //
assign sys_sig_delay_in[1] = sync_ttl_in2; //
assign sys_sig_delay_in[2] = sync_ttl_in3; //
assign sys_sig_delay_in[3] = sync_ttl_in4; //
assign sys_sig_delay_in[3] = !sync_ttl_in4; //
assign sys_sig_delay_in[4] = timecode_headphone_in; //
assign sys_sig_delay_in[5] = timecode_bnc_in; //
assign sys_sig_delay_in[7] = genlock_in_vsync; //
@ -719,8 +719,8 @@ module Top (
assign debug_signal_output[2] = af_delay__sync_ttl_in2;
assign debug_signal_output[3] = genlock_in_vsync;
assign debug_signal_output[4] = af_delay__genlock_in_vsync;
assign debug_signal_output[5] = timecode_headphone_in | timecode_bnc_in;
assign debug_signal_output[6] = af_delay__timecode_headphone_in | af_delay__timecode_bnc_in;
assign debug_signal_output[5] = !timecode_headphone_in | !timecode_bnc_in;
assign debug_signal_output[6] = !af_delay__timecode_headphone_in | !af_delay__timecode_bnc_in;
assign debug_signal_output[7] = sync_ttl_out1;
assign debug_signal_output[8] = sync_ttl_out2;
assign debug_signal_output[9] = sync_ttl_out3;
@ -728,7 +728,7 @@ module Top (
assign debug_signal_output[11] = sync_ttl_in1;
assign debug_signal_output[12] = sync_ttl_in2;
assign debug_signal_output[13] = sync_ttl_in3;
assign debug_signal_output[15] = sync_ttl_in4;
assign debug_signal_output[15] = !sync_ttl_in4;
endmodule
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