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xsync_fpge_v2
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update

master
zhaohe 1 year ago
parent
693e7550da
commit
2a2f0c530f
4 changed files with 146 additions and 31 deletions
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  1. 130
      led_test.pds
  2. 1
      source/src/config.v
  3. 41
      source/src/input/timecode_input.v
  4. 5
      source/src/top.v

130
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Mar 26 21:40:59 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Mar 26 22:08:39 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -19,7 +19,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-03-26T21:21:35")
(_timespec "2024-03-26T22:07:22")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -131,7 +131,7 @@
)
(_file "source/src/input/timecode_input.v"
(_format verilog)
(_timespec "2024-03-26T21:40:57")
(_timespec "2024-03-26T22:03:36")
)
(_file "source/src/timecode/timecode_decoder.v"
(_format verilog)
@ -315,17 +315,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-03-26T21:40:58")
(_timespec "2024-03-26T22:07:42")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-03-26T21:40:57")
(_timespec "2024-03-26T22:07:41")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-03-26T21:40:58")
(_timespec "2024-03-26T22:07:42")
)
)
)
@ -335,9 +335,29 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-03-26T22:07:54")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-03-26T22:07:54")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-03-26T22:07:55")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-03-26T22:07:55")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))
@ -352,14 +372,34 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-03-26T22:07:58")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-03-26T22:07:57")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-03-26T22:07:58")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-03-26T22:07:58")
)
)
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/led_test.pcf"
(_format pcf)
(_timespec "2024-03-26T21:39:24")
(_timespec "2024-03-26T22:07:58")
)
)
)
@ -369,7 +409,7 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
@ -378,6 +418,38 @@
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option mode (_string "fast"))
(_option fix_hold_violation_in_route (_boolean FALSE))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-03-26T22:08:18")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-03-26T22:08:18")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-03-26T22:08:17")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-03-26T22:08:17")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-03-26T22:08:04")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-03-26T22:08:18")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-03-26T22:08:19")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -386,8 +458,24 @@
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_attribute _auto_exe_lock (_switch OFF))
(_db_output
(_file "report_timing/Top_rtp.adf"
(_format adif)
(_timespec "2024-03-26T22:08:23")
)
)
(_output
(_file "report_timing/Top.rtr"
(_format text)
(_timespec "2024-03-26T22:08:23")
)
(_file "report_timing/rtr.db"
(_format text)
(_timespec "2024-03-26T22:08:24")
)
)
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
@ -405,7 +493,25 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-03-26T22:08:38")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-03-26T22:08:38")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-03-26T22:08:38")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-03-26T22:08:39")
)
)
)
)
)

1
source/src/config.v
View File

@ -42,4 +42,5 @@
`define TTL_OUTPUT_TRIGGER_MODE_SIG_WIDTH 32'd1000
`define FREQ_DETECT_BIAS_DEFAULT 32'd10
`define EXT_TIMECODE_FREQ_DETECT_BIAS_DEFAULT 32'd500
`define VERSION 32'd3

41
source/src/input/timecode_input.v
View File

@ -22,6 +22,7 @@ module timecode_input_parser #(
output reg [31:0] timecode_format,
output reg [63:0] timecode_data,
output reg timecode_serial_data,
output timecode_is_detected,
/*******************************************************************************
* 指示灯状态输出 *
@ -63,7 +64,7 @@ module timecode_input_parser #(
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rA_freq_bias <= `FREQ_DETECT_BIAS_DEFAULT;
rA_freq_bias <= `EXT_TIMECODE_FREQ_DETECT_BIAS_DEFAULT;
end else begin
if (reg_wr_sig) begin
case (reg_wr_index)
@ -99,11 +100,13 @@ module timecode_input_parser #(
);
zutils_freq_detector_v2 freq_detector1 (
.clk (clk),
.rst_n (rst_n),
.freq_detect_bias(rA_freq_bias),
.pluse_input (ch1_timecode_tigger_sig),
.pluse_width_cnt (ch1_freq)
.clk (clk),
.rst_n (rst_n),
.freq_detect_bias (rA_freq_bias),
.pluse_input (ch1_timecode_tigger_sig),
.pluse_width_cnt (ch1_freq),
.pluse_width_cnt_lock(ch1_pluse_width_cnt_lock)
);
timecode_decoder #(
@ -119,11 +122,12 @@ module timecode_input_parser #(
zutils_freq_detector_v2 freq_detector2 (
.clk (clk),
.rst_n (rst_n),
.freq_detect_bias(rA_freq_bias),
.pluse_input (ch2_timecode_tigger_sig),
.pluse_width_cnt (ch2_freq)
.clk (clk),
.rst_n (rst_n),
.freq_detect_bias (rA_freq_bias),
.pluse_input (ch2_timecode_tigger_sig),
.pluse_width_cnt (ch2_freq),
.pluse_width_cnt_lock(ch2_pluse_width_cnt_lock)
);
@ -149,37 +153,39 @@ module timecode_input_parser #(
r4_timecode1 <= 0;
timecode_tigger_sig <= 0;
if (ch1_freq != 0) begin
if (ch1_pluse_width_cnt_lock) begin
state <= 1;
freq_cache <= ch1_freq;
end else if (ch2_freq != 0) begin
end else if (ch2_pluse_width_cnt_lock) begin
state <= 2;
freq_cache <= ch2_freq;
end
end
1: begin
if (freq_cache != ch1_freq) begin
if (!ch1_pluse_width_cnt_lock) begin
state <= 0;
freq_cache <= 0;
end else begin
r5_freq <= ch1_freq;
r5_freq <= freq_cache;
r1_timecode_sig_selt <= 1;
r3_timecode0 <= ch1_timecode_data[31:0];
r4_timecode1 <= ch1_timecode_data[63:32];
timecode_data <= ch1_timecode_data;
timecode_tigger_sig <= ch1_timecode_tigger_sig;
end
end
2: begin
if (freq_cache != ch2_freq) begin
if (!ch2_pluse_width_cnt_lock) begin
state <= 0;
freq_cache <= 0;
end else begin
r5_freq <= ch2_freq;
r5_freq <= freq_cache;
r1_timecode_sig_selt <= 2;
r3_timecode0 <= ch2_timecode_data[31:0];
r4_timecode1 <= ch2_timecode_data[63:32];
timecode_data <= ch2_timecode_data;
timecode_tigger_sig <= ch2_timecode_tigger_sig;
end
end
@ -192,5 +198,6 @@ module timecode_input_parser #(
assign timecode_headphone_in_state_led = 1;
assign timecode_bnc_in_state_led = 1;
assign timecode_is_detected = (state == 1) || (state == 2);
endmodule

5
source/src/top.v
View File

@ -417,6 +417,7 @@ module Top (
.timecode_format (ext_timecode_format), //[31:0]
.timecode_data (ext_timecode_data), //[63:0]
.timecode_serial_data (ext_timecode_serial_data),
.timecode_is_detected (timecode_is_detected),
.timecode_headphone_in_state_led(timecode_headphone_in_state_led),
.timecode_bnc_in_state_led (timecode_bnc_in_state_led)
);
@ -715,8 +716,8 @@ module Top (
assign debug_signal_output[0] = timecode_bnc_in;
assign debug_signal_output[1] = af_delay__timecode_headphone_in;
assign debug_signal_output[2] = timecode_headphone_in;
assign debug_signal_output[3] = sync_ttl_in1;
assign debug_signal_output[2] = timecode_is_detected;
assign debug_signal_output[3] = timecode_is_detected;
assign debug_signal_output[4] = sync_ttl_in1;
// assign debug_signal_output[5] = af_delay__sync_ttl_in1;
// assign debug_signal_output[6] = af_delay__sync_ttl_in1;

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