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xsync_fpge_v2
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led light is ok

master
zhaohe 11 months ago
parent
6354e7acf9
commit
2b5aedd202
9 changed files with 820 additions and 310 deletions
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  1. 80
      constraint_check/constraint_check.ccr
  2. 1
      msg_level.txt
  3. 39
      multiseed_summary.csv
  4. 5
      pin.csv
  5. 78
      source/src/top.v
  6. 499
      xsync.backup_1.pds
  7. 299
      xsync.fdc
  8. 124
      xsync.pds
  9. 5
      xsync.pds.lock

80
constraint_check/constraint_check.ccr
View File

@ -0,0 +1,80 @@
##### Written on 2024/08/25 21:01:31 ###############################
##### INFO ##################################################
Current device :
PG2L100H-6FBG484
Top Module :
Top
Constraint File(s) :
D:/workspace/p_lusterinc_xsync/xsync_fpge_v2/xsync.fdc
##### SUMMARY ######################################################
Found 0 error(s), 0 critical warning(s), 41 warning(s), out of 17 constraint(s)
Inapplicable constraints(except overwritten constraints):
********************************************
Constraints with issues:
********************************************
Issues without commands:
********************************************
Unconstrained ports:
********************************************
W: ConstraintEditor-4019: Port Bus 'debug_signal_output' unspecified I/O constraint.
W: ConstraintEditor-4019: Port Bus 'genlock_out_dac' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'genlock_in_fsync' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'genlock_in_hsync' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'genlock_in_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'genlock_in_vsync' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'genlock_out_dac_clk' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'genlock_out_dac_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'spi1_clk_pin' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'spi1_cs_pin' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'spi1_rx_pin' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'spi1_tx_pin' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'stm32if_camera_sync_out' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'stm32if_start_signal_out' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'stm32if_timecode_sync_out' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_in1' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_in1_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_in2' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_in2_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_in3' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_in3_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_in4' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_in4_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_out1' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_out1_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_out2' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_out2_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_out3' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_out3_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_out4' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'sync_ttl_out4_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'timecode_bnc_in' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'timecode_bnc_in_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'timecode_headphone_in' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'timecode_headphone_in_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'timecode_out_bnc' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'timecode_out_bnc_select' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'timecode_out_bnc_state_led' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'timecode_out_headphone' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'timecode_out_headphone_select' unspecified I/O constraint.
W: ConstraintEditor-4019: Port 'timecode_out_headphone_state_led' unspecified I/O constraint.
Constraints with matching wildcard expressions:
********************************************

1
msg_level.txt
View File

@ -5,3 +5,4 @@ Verilog-2023=0
Verilog-2024=0
Verilog-2036=0
Verilog-2042=0
******=49d3732cd2f12b1bbdf8dc6dcdbcee83f7b37cf2ff29bc5c9449729318bcfbb0

39
multiseed_summary.csv
View File

@ -0,0 +1,39 @@
version,2022.2-SP4.2<build 132111>
project name,xsync.pds
Single Seed:
Seed,State,Convergence,Setup(Slow),Setup(Fast),Hold(Slow),Hold(Fast),Recovery(Slow),Recovery(Fast),Removal(Slow),Removal(Fast),PBM-GP,PBM-PreGP,PBM-PostGP,LP,Total Placement Cpu Time,Detailed routing,Total Routing Cpu Time,Wire Length After Post-GP,Wire Length After LP,Wire Length After DP,Routing Arc Length,Worst Slack After GP Timing,Worst Slack After LP Timing,Worst Slack Before RP,Worst Slack Before DP,Worst Slack After DP,Worst Slack After Placement,Worst Slack After TA By Preroute,TNS After DP,TNS Before Route,Setup(Slow) Total Failing TNS,Setup(Slow) Total Failing Endpoints,Hold(Slow) Total Failing THS,Hold(Slow) Total Failing Endpoints,Power
single,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,NA,0.00,1.41,0.02,2.11,NA,NA,NA,672,NA,NA,997904,997904,997904,997904,NA,0,0,NA,NA,NA,NA,NA
Pass Rate/Convergence Rate,0.00%,0.00%
Synthesize:
control_set,3
Synthesize Performance Summary:
slack category,Synthesize Setup WNS,Synthesize Setup TNS,Synthesize Recovery WNS,Synthesize Recovery TNS
slack value,997.343,0.000,NA,NA
Synthesize Process Cpu Time,0h:0m:2s
Device Map:
Device Map Resource Usage Summary:
Logic Utilization,LUT,FF,DRM,APM,Distributed RAM,HSSTHP,USCM,HCKB,RCKB
Used,45,29,0,0,0,NA,1,0,0
Available,66600,133200,155,240,19900,NA,32,96,24
Utilization(%),1%,1%,0%,0%,0%,NA,4%,0%,0%
Device Map Process Cpu Time,0h:0m:2s
Project Configurations:
top module,Top
compile,
synthesize," -ads "
device map,
place & route," -gplace_seed 8
-seed_step 4
-saved_outcome 4
-parallel 4
-share_router_control_signal false
-check_clk_net_route_by_srb false
-fix_hold_violation_in_route false "
Test Parameters Configurations:
testparam,

5
pin.csv
View File

@ -65,7 +65,4 @@ AA15,debug_signal_output[12],OUTPUT
AB15,debug_signal_output[13],OUTPUT
Y16,debug_signal_output[14],OUTPUT
AA16,debug_signal_output[15],OUTPUT
W5,core_board_debug_led,OUTPUT
N/A,debug_signal_output[14] ,OUTPUT
N/A,debug_signal_output[15] ,OUTPUT
W5,core_board_debug_led,OUTPUT
W5,core_board_debug_led,OUTPUT

78
source/src/top.v
View File

@ -65,15 +65,81 @@ module Top (
output [15:0] debug_signal_output,
output wire core_board_debug_led
output reg core_board_debug_led
);
//parameter define
parameter CNT_2US_MAX = 7'd100;
parameter CNT_2MS_MAX = 10'd1000;
parameter CNT_2S_MAX = 10'd1000;
//reg define
reg [6:0] cnt_2us;
reg [9:0] cnt_2ms;
reg [9:0] cnt_2s;
reg inc_dec_flag; //亮度递增/递减 0:递增 1:递减
//*****************************************************
//** main code
//*****************************************************
//cnt_2us:计数2us
always@(posedge ex_clk or negedge ex_rst_n) begin
if(!ex_rst_n)
cnt_2us <= 7'b0;
else if(cnt_2us == (CNT_2US_MAX - 7'b1 ))
cnt_2us <= 7'b0;
else
cnt_2us <= cnt_2us + 7'b1;
end
//cnt_2ms:计数2ms
always@(posedge ex_clk or negedge ex_rst_n) begin
if(!ex_rst_n)
cnt_2ms <= 10'b0;
else if(cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1))
cnt_2ms <= 10'b0;
else if(cnt_2us == CNT_2US_MAX - 7'b1)
cnt_2ms <= cnt_2ms + 10'b1;
else
cnt_2ms <= cnt_2ms;
end
//cnt_2s:计数2s
always@(posedge ex_clk or negedge ex_rst_n) begin
if(!ex_rst_n)
cnt_2s <= 10'b0;
else if(cnt_2s == (CNT_2S_MAX - 10'b1) && cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1))
cnt_2s <= 10'b0;
else if(cnt_2ms == (CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1))
cnt_2s <= cnt_2s + 10'b1;
else
cnt_2s <= cnt_2s;
end
//inc_dec_flag为低电平，led灯由暗变亮，inc_dec_flag为高电平，led灯由亮变暗
always@(posedge ex_clk or negedge ex_rst_n) begin
if(!ex_rst_n)
inc_dec_flag <= 1'b0;
else if(cnt_2s == (CNT_2S_MAX - 10'b1) && cnt_2ms ==( CNT_2MS_MAX - 10'b1) && cnt_2us == (CNT_2US_MAX - 7'b1))
inc_dec_flag <= ~inc_dec_flag;
else
inc_dec_flag <= inc_dec_flag;
end
//led:输出信号连接到外部的led灯
always@(posedge ex_clk or negedge ex_rst_n) begin
if(!ex_rst_n)
core_board_debug_led <= 1'b0;
else if((inc_dec_flag == 1'b1 && cnt_2ms >= cnt_2s) || (inc_dec_flag == 1'b0 && cnt_2ms <= cnt_2s))
core_board_debug_led <= 1'b1;
else
core_board_debug_led <= 1'b0;
end
/*
localparam SYS_CLOCK_FREQ = 10000000;
wire sys_clk; //! 系统时钟
wire sys_rst_n; //! 系统复位
@ -721,5 +787,5 @@ module Top (
assign debug_signal_output[13] = sync_ttl_in3;
assign debug_signal_output[15] = !sync_ttl_in4;
*/
endmodule

499
xsync.backup_1.pds
View File

@ -0,0 +1,499 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Sun Aug 25 17:14:25 2024")
(_version "1.0.5")
(_status "initial")
(_project
)
(_task tsk_setup
(_widget wgt_select_arch
(_input
(_part
(_family Logos2)
(_device PG2L100H)
(_speedgrade -6)
(_package FBG484)
)
)
)
(_widget wgt_my_design_src
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-08-25T17:07:32")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_pluse_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_edge_detecter.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_register.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_4t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_debug_led.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_signal_filter.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_clk_parser.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_16t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/output/ttl_output.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_reset_sig_gen.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_2t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_32t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_muti_debug_signal_gen.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_pwm_generator_advanced.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_register_advanced.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_genlock_clk_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_32t1_v2.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/ztutils_timecode_next_code.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_smpte_timecode_clk_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_nextcode.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_basesig_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_serialization.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/output/timecode_output.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/input/timecode_input.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_decoder.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_sample_sig_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/input/ttl_input.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/ztuils_sig_devide.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_signal_filter_advance.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/timecode/timecode_comparator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_freq_detector.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zsimple_pll.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_freq_detector_v2.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_multiplexer_8t1.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/spi_reg_bus.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/internal/internal_timecode_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/sys/sys_timecode.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/input/genlock_input_module.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/internal/internal_clock_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/internal/internal_genlock_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/sys/sys_genlock.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/sys/sys_clock.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/output/camera_sync_signal_output.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/business/record_sig_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/sys_signal_delayer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_sig_delayer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_sig_delayer_v2.v"
(_format verilog)
(_timespec "2024-08-23T15:51:36")
)
(_file "source/src/zutils/zutils_pluse_delayer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/internal/internal_sig_generator_en_contrler.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/src/zutils/zutils_timer.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
)
)
(_widget wgt_my_ips_src
(_input
(_ip "ipcore/ShiftRegister/ShiftRegister.idf"
(_timespec "2024-08-23T13:36:15")
(_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_sdpram_v1_2_ShiftRegister.v"
(_timespec "2024-08-23T13:36:15")
)
(_ip_source_item "ipcore/ShiftRegister/rtl/ipm_distributed_shiftregister_v1_2_ShiftRegister.v"
(_timespec "2024-08-23T13:36:15")
)
(_ip_source_item "ipcore/ShiftRegister/ShiftRegister.v"
(_timespec "2024-08-23T13:36:15")
)
)
(_ip "ipcore/SPLL/SPLL.idf"
(_timespec "2024-08-23T14:44:49")
(_ip_source_item "ipcore/SPLL/SPLL.v"
(_timespec "2024-08-23T14:44:49")
)
)
)
)
(_widget wgt_import_logic_con_file
(_input
(_file "xsync.fdc"
(_format fdc)
(_timespec "2024-08-23T15:44:26")
)
)
)
(_widget wgt_edit_user_cons
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_simulation
(_option compiled_lib_location (_string "pango_sim_libraries"))
(_option verilog_options (_string ""))
(_option gen_param (_string ""))
(_option simulate_runtime (_string "10000ms"))
(_option sim_exe_dir (_string "C:/modeltech64_10.5/win64"))
(_input
(_file "source/test/test_transmitter.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_baud_rate_gen.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_top.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_uart_reg_reader.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_spi_reg_reader.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_timecode_generator.v"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
(_file "source/test/test_timecode_decoder.v" + "test_timecode_decoder:"
(_format verilog)
(_timespec "2024-08-23T13:36:15")
)
)
)
)
(_task tsk_compile
(_command cmd_compile
(_gci_state (_integer 2))
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-08-25T17:07:35")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-08-25T17:07:35")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-08-25T17:07:35")
)
)
)
(_widget wgt_rtl_view
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 2))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-08-25T17:07:42")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-08-25T17:07:42")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-08-25T17:07:42")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-08-25T17:07:42")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_map_constraint
)
(_widget wgt_my_fic_src
)
(_widget wgt_inserter_gui_view
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-08-25T17:07:50")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-08-25T17:07:50")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-08-25T17:07:50")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-08-25T17:07:50")
)
)
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/xsync.pcf"
(_format pcf)
(_timespec "2024-08-25T17:07:50")
)
)
)
(_widget wgt_edit_route_cons
(_attribute _click_to_run (_switch ON))
)
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 2))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
(_option parallel (_integer 4))
(_option share_router_control_signal (_boolean FALSE))
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option fix_hold_violation_in_route (_boolean FALSE))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-08-25T17:08:10")
)
)
(_output
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-08-25T17:08:10")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-08-25T17:08:10")
)
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-08-25T17:08:10")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-08-25T17:08:02")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-08-25T17:08:10")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-08-25T17:08:10")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
)
(_widget wgt_timing_analysis
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
)
(_command cmd_report_power
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
(_command cmd_gen_netlist
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 2))
(_option unused_io_status (_string "KEEPER"))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-08-25T17:08:26")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-08-25T17:08:26")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-08-25T17:08:26")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-08-25T17:08:27")
)
)
)
)
)

299
xsync.fdc
View File

@ -1,290 +1,17 @@
define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:core_board_debug_led} {PAP_IO_LOC} {W5}
define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {1.5}
define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {8}
define_attribute {p:core_board_debug_led} {PAP_IO_UNUSED} {TRUE}
define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {FAST}
define_attribute {p:ex_clk} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:ex_clk} {PAP_IO_LOC} {R4}
define_attribute {p:ex_clk} {PAP_IO_VCCIO} {3.3}
define_attribute {p:ex_clk} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:ex_clk} {PAP_IO_VCCIO} {1.5}
define_attribute {p:ex_clk} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:ex_clk} {PAP_IO_NONE} {TRUE}
define_attribute {p:ex_rst_n} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:ex_rst_n} {PAP_IO_LOC} {U7}
define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {3.3}
define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:genlock_in_hsync} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:genlock_in_hsync} {PAP_IO_LOC} {M15}
define_attribute {p:genlock_in_hsync} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_in_hsync} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:genlock_in_vsync} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:genlock_in_vsync} {PAP_IO_LOC} {M16}
define_attribute {p:genlock_in_vsync} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_in_vsync} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:genlock_in_fsync} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:genlock_in_fsync} {PAP_IO_LOC} {L16}
define_attribute {p:genlock_in_fsync} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_in_fsync} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:genlock_out_dac[0]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:genlock_out_dac[0]} {PAP_IO_LOC} {E14}
define_attribute {p:genlock_out_dac[0]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_out_dac[0]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:genlock_out_dac[0]} {PAP_IO_DRIVE} {4}
define_attribute {p:genlock_out_dac[0]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:genlock_out_dac[1]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:genlock_out_dac[1]} {PAP_IO_LOC} {E13}
define_attribute {p:genlock_out_dac[1]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_out_dac[1]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:genlock_out_dac[1]} {PAP_IO_DRIVE} {4}
define_attribute {p:genlock_out_dac[1]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:genlock_out_dac[2]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:genlock_out_dac[2]} {PAP_IO_LOC} {F14}
define_attribute {p:genlock_out_dac[2]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_out_dac[2]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:genlock_out_dac[2]} {PAP_IO_DRIVE} {4}
define_attribute {p:genlock_out_dac[2]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:genlock_out_dac[3]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:genlock_out_dac[3]} {PAP_IO_LOC} {F13}
define_attribute {p:genlock_out_dac[3]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_out_dac[3]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:genlock_out_dac[3]} {PAP_IO_DRIVE} {4}
define_attribute {p:genlock_out_dac[3]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:genlock_out_dac[4]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:genlock_out_dac[4]} {PAP_IO_LOC} {C22}
define_attribute {p:genlock_out_dac[4]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_out_dac[4]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:genlock_out_dac[4]} {PAP_IO_DRIVE} {4}
define_attribute {p:genlock_out_dac[4]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:genlock_out_dac[5]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:genlock_out_dac[5]} {PAP_IO_LOC} {B22}
define_attribute {p:genlock_out_dac[5]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_out_dac[5]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:genlock_out_dac[5]} {PAP_IO_DRIVE} {4}
define_attribute {p:genlock_out_dac[5]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:genlock_out_dac[6]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:genlock_out_dac[6]} {PAP_IO_LOC} {C20}
define_attribute {p:genlock_out_dac[6]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_out_dac[6]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:genlock_out_dac[6]} {PAP_IO_DRIVE} {4}
define_attribute {p:genlock_out_dac[6]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:genlock_out_dac[7]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:genlock_out_dac[7]} {PAP_IO_LOC} {D20}
define_attribute {p:genlock_out_dac[7]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_out_dac[7]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:genlock_out_dac[7]} {PAP_IO_DRIVE} {4}
define_attribute {p:genlock_out_dac[7]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:genlock_out_dac[8]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:genlock_out_dac[8]} {PAP_IO_LOC} {C19}
define_attribute {p:genlock_out_dac[8]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_out_dac[8]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:genlock_out_dac[8]} {PAP_IO_DRIVE} {4}
define_attribute {p:genlock_out_dac[8]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:genlock_out_dac_clk} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:genlock_out_dac_clk} {PAP_IO_LOC} {C18}
define_attribute {p:genlock_out_dac_clk} {PAP_IO_VCCIO} {3.3}
define_attribute {p:genlock_out_dac_clk} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:genlock_out_dac_clk} {PAP_IO_DRIVE} {4}
define_attribute {p:genlock_out_dac_clk} {PAP_IO_SLEW} {SLOW}
define_attribute {p:sync_ttl_in1} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:sync_ttl_in1} {PAP_IO_LOC} {K18}
define_attribute {p:sync_ttl_in1} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_in1} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:sync_ttl_in2} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:sync_ttl_in2} {PAP_IO_LOC} {K19}
define_attribute {p:sync_ttl_in2} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_in2} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:sync_ttl_in3} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:sync_ttl_in3} {PAP_IO_LOC} {M13}
define_attribute {p:sync_ttl_in3} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_in3} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:sync_ttl_in4} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:sync_ttl_in4} {PAP_IO_LOC} {L13}
define_attribute {p:sync_ttl_in4} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_in4} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:sync_ttl_out1} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out1} {PAP_IO_LOC} {AA8}
define_attribute {p:sync_ttl_out1} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out1} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out1} {PAP_IO_DRIVE} {4}
define_attribute {p:sync_ttl_out1} {PAP_IO_SLEW} {SLOW}
define_attribute {p:sync_ttl_out2} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out2} {PAP_IO_LOC} {V9}
define_attribute {p:sync_ttl_out2} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out2} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out2} {PAP_IO_DRIVE} {4}
define_attribute {p:sync_ttl_out2} {PAP_IO_SLEW} {SLOW}
define_attribute {p:sync_ttl_out3} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out3} {PAP_IO_LOC} {V8}
define_attribute {p:sync_ttl_out3} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out3} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out3} {PAP_IO_DRIVE} {4}
define_attribute {p:sync_ttl_out3} {PAP_IO_SLEW} {SLOW}
define_attribute {p:sync_ttl_out4} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:sync_ttl_out4} {PAP_IO_LOC} {T6}
define_attribute {p:sync_ttl_out4} {PAP_IO_VCCIO} {3.3}
define_attribute {p:sync_ttl_out4} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:sync_ttl_out4} {PAP_IO_DRIVE} {4}
define_attribute {p:sync_ttl_out4} {PAP_IO_SLEW} {SLOW}
define_attribute {p:timecode_headphone_in} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:timecode_headphone_in} {PAP_IO_LOC} {L15}
define_attribute {p:timecode_headphone_in} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_headphone_in} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:timecode_bnc_in} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:timecode_bnc_in} {PAP_IO_LOC} {L14}
define_attribute {p:timecode_bnc_in} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_bnc_in} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:timecode_out_bnc} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:timecode_out_bnc} {PAP_IO_LOC} {W9}
define_attribute {p:timecode_out_bnc} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_out_bnc} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:timecode_out_bnc} {PAP_IO_DRIVE} {4}
define_attribute {p:timecode_out_bnc} {PAP_IO_SLEW} {SLOW}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_LOC} {R6}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_DRIVE} {4}
define_attribute {p:timecode_out_bnc_select} {PAP_IO_SLEW} {SLOW}
define_attribute {p:timecode_out_headphone} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:timecode_out_headphone} {PAP_IO_LOC} {Y9}
define_attribute {p:timecode_out_headphone} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_out_headphone} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:timecode_out_headphone} {PAP_IO_DRIVE} {4}
define_attribute {p:timecode_out_headphone} {PAP_IO_SLEW} {SLOW}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_LOC} {T3}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_VCCIO} {3.3}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_DRIVE} {4}
define_attribute {p:timecode_out_headphone_select} {PAP_IO_SLEW} {SLOW}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_LOC} {Y21}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_VCCIO} {3.3}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_DRIVE} {4}
define_attribute {p:stm32if_start_signal_out} {PAP_IO_SLEW} {SLOW}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_LOC} {Y22}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_VCCIO} {3.3}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_DRIVE} {4}
define_attribute {p:stm32if_camera_sync_out} {PAP_IO_SLEW} {SLOW}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_LOC} {AB20}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_VCCIO} {3.3}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_DRIVE} {4}
define_attribute {p:stm32if_timecode_sync_out} {PAP_IO_SLEW} {SLOW}
define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {W7}
define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {V7}
define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT}
define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {Y7}
define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33}
define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {Y8}
define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3}
define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4}
define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[0]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[0]} {PAP_IO_LOC} {Y11}
define_attribute {p:debug_signal_output[0]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[0]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[0]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[0]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[1]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[1]} {PAP_IO_LOC} {Y12}
define_attribute {p:debug_signal_output[1]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[1]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[1]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[1]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[2]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[2]} {PAP_IO_LOC} {AA10}
define_attribute {p:debug_signal_output[2]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[2]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[2]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[2]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[3]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[3]} {PAP_IO_LOC} {AA11}
define_attribute {p:debug_signal_output[3]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[3]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[3]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[3]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[4]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[4]} {PAP_IO_LOC} {AB11}
define_attribute {p:debug_signal_output[4]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[4]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[4]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[4]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[5]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[5]} {PAP_IO_LOC} {AB12}
define_attribute {p:debug_signal_output[5]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[5]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[5]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[5]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[6]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[6]} {PAP_IO_LOC} {W11}
define_attribute {p:debug_signal_output[6]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[6]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[6]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[6]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[7]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[7]} {PAP_IO_LOC} {W12}
define_attribute {p:debug_signal_output[7]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[7]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[7]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[7]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[8]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[8]} {PAP_IO_LOC} {AA13}
define_attribute {p:debug_signal_output[8]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[8]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[8]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[8]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[9]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[9]} {PAP_IO_LOC} {AB13}
define_attribute {p:debug_signal_output[9]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[9]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[9]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[9]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[10]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[10]} {PAP_IO_LOC} {Y13}
define_attribute {p:debug_signal_output[10]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[10]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[10]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[10]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[11]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[11]} {PAP_IO_LOC} {AA14}
define_attribute {p:debug_signal_output[11]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[11]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[11]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[11]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[12]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[12]} {PAP_IO_LOC} {AA15}
define_attribute {p:debug_signal_output[12]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[12]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[12]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[12]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[13]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[13]} {PAP_IO_LOC} {AB15}
define_attribute {p:debug_signal_output[13]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[13]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[13]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[13]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[14]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[14]} {PAP_IO_LOC} {Y16}
define_attribute {p:debug_signal_output[14]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[14]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[14]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[14]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:debug_signal_output[15]} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:debug_signal_output[15]} {PAP_IO_LOC} {AA16}
define_attribute {p:debug_signal_output[15]} {PAP_IO_VCCIO} {3.3}
define_attribute {p:debug_signal_output[15]} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:debug_signal_output[15]} {PAP_IO_DRIVE} {4}
define_attribute {p:debug_signal_output[15]} {PAP_IO_SLEW} {SLOW}
define_attribute {p:core_board_debug_led} {PAP_IO_DIRECTION} {OUTPUT}
define_attribute {p:core_board_debug_led} {PAP_IO_LOC} {W5}
define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3}
define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33}
define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4}
define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW}
define_attribute {p:ex_rst_n} {PAP_IO_VCCIO} {1.5}
define_attribute {p:ex_rst_n} {PAP_IO_STANDARD} {LVCMOS15}
define_attribute {p:ex_rst_n} {PAP_IO_NONE} {TRUE}

124
xsync.pds
View File

@ -1,8 +1,10 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Fri Aug 23 15:51:49 2024")
(_version "1.0.5")
(_flow fab_demo "2022.2-SP4.2"
(_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2<build 132111>) at Sun Aug 25 21:02:11 2024")
(_version "1.1.0")
(_status "initial")
(_project
(_option prj_work_dir (_string "."))
(_option prj_impl_dir (_string "."))
)
(_task tsk_setup
(_widget wgt_select_arch
@ -19,7 +21,7 @@
(_input
(_file "source/src/top.v" + "Top:"
(_format verilog)
(_timespec "2024-08-23T15:50:29")
(_timespec "2024-08-25T21:00:01")
)
(_file "source/src/spi_reg_reader.v"
(_format verilog)
@ -261,7 +263,7 @@
(_input
(_file "xsync.fdc"
(_format fdc)
(_timespec "2024-08-23T15:44:26")
(_timespec "2024-08-25T21:00:42")
)
)
)
@ -312,17 +314,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-08-23T15:51:49")
(_timespec "2024-08-25T21:01:25")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-08-23T15:51:45")
(_timespec "2024-08-25T21:01:25")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-08-23T15:51:49")
(_timespec "2024-08-25T21:01:25")
)
)
)
@ -332,9 +334,32 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 0))
(_option ads (_switch ON))
(_gci_state (_integer 2))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-08-25T21:01:32")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-08-25T21:01:32")
)
(_file "synthesize/Top_controlsets.txt"
(_format text)
(_timespec "2024-08-25T21:01:32")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-08-25T21:01:32")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-08-25T21:01:32")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))
@ -349,14 +374,34 @@
)
(_task tsk_devmap
(_command cmd_devmap
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_db_output
(_file "device_map/Top_map.adf"
(_format adif)
(_timespec "2024-08-25T21:01:41")
)
)
(_output
(_file "device_map/Top_dmr.prt"
(_format text)
(_timespec "2024-08-25T21:01:41")
)
(_file "device_map/Top.dmr"
(_format text)
(_timespec "2024-08-25T21:01:42")
)
(_file "device_map/dmr.db"
(_format text)
(_timespec "2024-08-25T21:01:42")
)
)
)
(_widget wgt_edit_placement_cons
(_attribute _click_to_run (_switch ON))
(_input
(_file "device_map/xsync.pcf"
(_format pcf)
(_timespec "2024-08-23T15:46:12")
(_timespec "2024-08-25T21:01:41")
)
)
)
@ -366,7 +411,7 @@
)
(_task tsk_pnr
(_command cmd_pnr
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option gplace_seed (_integer 8))
(_option seed_step (_integer 4))
(_option saved_outcome (_integer 4))
@ -374,6 +419,38 @@
(_option share_router_control_signal (_boolean FALSE))
(_option check_clk_net_route_by_srb (_boolean FALSE))
(_option fix_hold_violation_in_route (_boolean FALSE))
(_db_output
(_file "place_route/Top_pnr.adf"
(_format adif)
(_timespec "2024-08-25T21:01:59")
)
)
(_output
(_file "place_route/clock_utilization.txt"
(_format text)
(_timespec "2024-08-25T21:01:59")
)
(_file "place_route/Top_plc.adf"
(_format adif)
(_timespec "2024-08-25T21:01:54")
)
(_file "place_route/Top.prr"
(_format text)
(_timespec "2024-08-25T21:01:59")
)
(_file "place_route/Top_prr.prt"
(_format text)
(_timespec "2024-08-25T21:01:59")
)
(_file "place_route/Top_pnr.netlist"
(_format text)
(_timespec "2024-08-25T21:01:59")
)
(_file "place_route/prr.db"
(_format text)
(_timespec "2024-08-25T21:01:59")
)
)
)
(_widget wgt_power_calculator
(_attribute _click_to_run (_switch ON))
@ -384,6 +461,7 @@
(_command cmd_report_post_pnr_timing
(_gci_state (_integer 0))
(_attribute _auto_exe_lock (_switch OFF))
(_attribute _auto_exe (_switch OFF))
)
(_widget wgt_arch_browser
(_attribute _click_to_run (_switch ON))
@ -401,8 +479,26 @@
)
(_task tsk_gen_bitstream
(_command cmd_gen_bitstream
(_gci_state (_integer 0))
(_gci_state (_integer 2))
(_option unused_io_status (_string "KEEPER"))
(_output
(_file "generate_bitstream/Top.sbit"
(_format text)
(_timespec "2024-08-25T21:02:10")
)
(_file "generate_bitstream/Top.smsk"
(_format text)
(_timespec "2024-08-25T21:02:10")
)
(_file "generate_bitstream/bgr.db"
(_format text)
(_timespec "2024-08-25T21:02:11")
)
(_file "generate_bitstream/Top.bgr"
(_format text)
(_timespec "2024-08-25T21:02:11")
)
)
)
)
)

5
xsync.pds.lock
View File

@ -0,0 +1,5 @@
19944
pds
ZHAOHE
f8caf121-d1d2-4c26-8a45-7e1d59cde8b6
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