From 32c7b86802bec59df8e0863efb12eeddf2832196 Mon Sep 17 00:00:00 2001
From: zhaohe <h_zhaohe@163.com>
Date: Tue, 5 Mar 2024 19:21:12 +0800
Subject: [PATCH] fix genlock input module bug

---
 led_test.pds                            | 82 +++++++--------------------------
 source/src/input/genlock_input_module.v |  2 +-
 2 files changed, 17 insertions(+), 67 deletions(-)

diff --git a/led_test.pds b/led_test.pds
index ef40965..815de4e 100644
--- a/led_test.pds
+++ b/led_test.pds
@@ -1,5 +1,5 @@
 (_flow fab_demo "2021.1-SP7"
-    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Mar  5 18:16:08 2024")
+    (_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Tue Mar  5 19:20:17 2024")
     (_version "1.0.5")
     (_status "initial")
     (_project 
@@ -187,7 +187,7 @@
                 )
                 (_file "source/src/input/genlock_input_module.v"
                     (_format verilog)
-                    (_timespec "2024-03-05T16:12:36")
+                    (_timespec "2024-03-05T19:17:12")
                 )
                 (_file "source/src/internal/internal_clock_generator.v"
                     (_format verilog)
@@ -275,17 +275,17 @@
             (_db_output
                 (_file "compile/Top_comp.adf"
                     (_format adif)
-                    (_timespec "2024-03-05T18:04:58")
+                    (_timespec "2024-03-05T19:17:20")
                 )
             )
             (_output
                 (_file "compile/Top.cmr"
                     (_format verilog)
-                    (_timespec "2024-03-05T18:04:55")
+                    (_timespec "2024-03-05T19:17:18")
                 )
                 (_file "compile/cmr.db"
                     (_format text)
-                    (_timespec "2024-03-05T18:04:58")
+                    (_timespec "2024-03-05T19:17:21")
                 )
             )
         )
@@ -301,21 +301,21 @@
             (_db_output
                 (_file "synthesize/Top_syn.adf"
                     (_format adif)
-                    (_timespec "2024-03-05T18:07:21")
+                    (_timespec "2024-03-05T19:19:41")
                 )
             )
             (_output
                 (_file "synthesize/Top_syn.vm"
                     (_format structural_verilog)
-                    (_timespec "2024-03-05T18:07:32")
+                    (_timespec "2024-03-05T19:19:53")
                 )
                 (_file "synthesize/Top.snr"
                     (_format text)
-                    (_timespec "2024-03-05T18:07:39")
+                    (_timespec "2024-03-05T19:20:01")
                 )
                 (_file "synthesize/snr.db"
                     (_format text)
-                    (_timespec "2024-03-05T18:07:40")
+                    (_timespec "2024-03-05T19:20:01")
                 )
             )
         )
@@ -336,21 +336,21 @@
             (_db_output
                 (_file "device_map/Top_map.adf"
                     (_format adif)
-                    (_timespec "2024-03-05T18:07:55")
+                    (_timespec "2024-03-05T19:20:16")
                 )
             )
             (_output
                 (_file "device_map/Top_dmr.prt"
                     (_format text)
-                    (_timespec "2024-03-05T18:07:43")
+                    (_timespec "2024-03-05T19:20:04")
                 )
                 (_file "device_map/Top.dmr"
                     (_format text)
-                    (_timespec "2024-03-05T18:07:55")
+                    (_timespec "2024-03-05T19:20:16")
                 )
                 (_file "device_map/dmr.db"
                     (_format text)
-                    (_timespec "2024-03-05T18:07:55")
+                    (_timespec "2024-03-05T19:20:17")
                 )
             )
         )
@@ -359,7 +359,7 @@
             (_input
                 (_file "device_map/led_test.pcf"
                     (_format pcf)
-                    (_timespec "2024-03-05T18:07:55")
+                    (_timespec "2024-03-05T19:20:16")
                 )
             )
         )
@@ -369,40 +369,8 @@
     )
     (_task tsk_pnr
         (_command cmd_pnr
-            (_gci_state (_integer 2))
+            (_gci_state (_integer 0))
             (_option mode (_string "fast"))
-            (_db_output
-                (_file "place_route/Top_pnr.adf"
-                    (_format adif)
-                    (_timespec "2024-03-05T18:14:38")
-                )
-            )
-            (_output
-                (_file "place_route/Top.prr"
-                    (_format text)
-                    (_timespec "2024-03-05T18:14:38")
-                )
-                (_file "place_route/Top_prr.prt"
-                    (_format text)
-                    (_timespec "2024-03-05T18:14:36")
-                )
-                (_file "place_route/clock_utilization.txt"
-                    (_format text)
-                    (_timespec "2024-03-05T18:14:36")
-                )
-                (_file "place_route/Top_plc.adf"
-                    (_format adif)
-                    (_timespec "2024-03-05T18:09:05")
-                )
-                (_file "place_route/Top_pnr.netlist"
-                    (_format text)
-                    (_timespec "2024-03-05T18:14:38")
-                )
-                (_file "place_route/prr.db"
-                    (_format text)
-                    (_timespec "2024-03-05T18:14:40")
-                )
-            )
         )
         (_widget wgt_power_calculator
             (_attribute _click_to_run (_switch ON))
@@ -431,25 +399,7 @@
     )
     (_task tsk_gen_bitstream
         (_command cmd_gen_bitstream
-            (_gci_state (_integer 2))
-            (_output
-                (_file "generate_bitstream/Top.sbit"
-                    (_format text)
-                    (_timespec "2024-03-05T18:16:06")
-                )
-                (_file "generate_bitstream/Top.smsk"
-                    (_format text)
-                    (_timespec "2024-03-05T18:16:06")
-                )
-                (_file "generate_bitstream/Top.bgr"
-                    (_format text)
-                    (_timespec "2024-03-05T18:16:06")
-                )
-                (_file "generate_bitstream/bgr.db"
-                    (_format text)
-                    (_timespec "2024-03-05T18:16:08")
-                )
-            )
+            (_gci_state (_integer 0))
         )
     )
 )
diff --git a/source/src/input/genlock_input_module.v b/source/src/input/genlock_input_module.v
index 89d95f8..a2a8413 100644
--- a/source/src/input/genlock_input_module.v
+++ b/source/src/input/genlock_input_module.v
@@ -63,7 +63,7 @@ module genlock_input_module #(
       .pluse_width_cnt (r2_genlock_freq)
   );
 
-  assign genlock_freq_signal  = genlock_in_hsync;
+  assign genlock_freq_signal  = genlock_in_vsync;
   assign genlock_in_state_led = 1;
 
 endmodule