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xsync_fpge_v2
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update

master
zhaohe 2 years ago
parent
72b8507a77
commit
3e1d0ae64e
18 changed files with 612 additions and 278 deletions
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  1. 64
      led_test.pds
  2. 38
      source/src/timecode/timecode_basesig_generator.v
  3. 179
      source/src/timecode/timecode_generator.v
  4. 232
      source/src/timecode/timecode_nextcode.v
  5. 118
      source/src/timecode/timecode_serialization.v
  6. 51
      source/src/xsync_internal_generator.v
  7. 2
      source/src/xsync_internal_sub/internal_timecode_generator.v
  8. 63
      source/src/zutils/ztutils_timecode_next_code_v2.v
  9. 20
      source/src/zutils/zutils_genlock_clk_generator.v
  10. 2
      source/src/zutils/zutils_muti_debug_signal_gen.v
  11. 2
      source/src/zutils/zutils_pluse_generator.v
  12. 2
      source/src/zutils/zutils_pwm_generator.v
  13. 6
      source/src/zutils/zutils_pwm_generator_advanced.v
  14. 14
      source/src/zutils/zutils_smpte_timecode_clk_generator.v
  15. 2
      source/src/zutils/zutils_timecode_convert.v
  16. 2
      source/src/zutils/zutils_timecode_serial_data_gen.v
  17. 90
      source/test/test_timecode_generator.v
  18. 3
      source/test/test_top.v

64
led_test.pds
View File

@ -1,5 +1,5 @@
(_flow fab_demo "2021.1-SP7"
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Wed Jan 10 17:10:03 2024")
(_comment "Generated by Fabric Compiler (version on 2021.1-SP7<build 86875>) at Wed Jan 10 21:54:43 2024")
(_version "1.0.5")
(_status "initial")
(_project
@ -27,7 +27,7 @@
)
(_file "source/src/zutils/zutils_pluse_generator.v"
(_format verilog)
(_timespec "2024-01-09T14:45:57")
(_timespec "2024-01-10T20:51:41")
)
(_file "source/src/zutils/zutils_edge_detecter.v"
(_format verilog)
@ -63,7 +63,7 @@
)
(_file "source/src/zutils/zutils_pwm_generator.v"
(_format verilog)
(_timespec "2024-01-08T22:15:09")
(_timespec "2024-01-10T20:45:33")
)
(_file "source/src/rd_data_router.v"
(_format verilog)
@ -83,15 +83,15 @@
)
(_file "source/src/zutils/zutils_muti_debug_signal_gen.v"
(_format verilog)
(_timespec "2024-01-09T10:38:50")
(_timespec "2024-01-10T20:51:41")
)
(_file "source/src/xsync_internal_generator.v"
(_format verilog)
(_timespec "2024-01-10T17:10:01")
(_timespec "2024-01-10T20:51:41")
)
(_file "source/src/zutils/zutils_pwm_generator_advanced.v"
(_format verilog)
(_timespec "2024-01-09T19:23:36")
(_timespec "2024-01-10T20:50:52")
)
(_file "source/src/zutils/zutils_register_advanced.v"
(_format verilog)
@ -99,7 +99,7 @@
)
(_file "source/src/zutils/zutils_genlock_clk_generator.v"
(_format verilog)
(_timespec "2024-01-09T20:08:58")
(_timespec "2024-01-10T21:10:08")
)
(_file "source/src/zutils/zutils_multiplexer_32t1_v2.v"
(_format verilog)
@ -111,23 +111,27 @@
)
(_file "source/src/zutils/zutils_smpte_timecode_clk_generator.v"
(_format verilog)
(_timespec "2024-01-09T20:17:36")
(_timespec "2024-01-10T20:51:41")
)
(_file "source/src/xsync_internal_sub/internal_timecode_generator.v"
(_format verilog)
(_timespec "2024-01-10T16:57:53")
(_timespec "2024-01-10T20:51:41")
)
(_file "source/src/timecode/timecode_nextcode.v"
(_format verilog)
(_timespec "2024-01-10T15:05:22")
(_timespec "2024-01-10T19:49:22")
)
(_file "source/src/timecode/timecode_basesig_generator.v"
(_format verilog)
(_timespec "2024-01-10T15:06:49")
(_timespec "2024-01-10T20:52:39")
)
(_file "source/src/timecode/timecode_serialization.v"
(_format verilog)
(_timespec "2024-01-10T16:55:47")
(_timespec "2024-01-10T21:45:29")
)
(_file "source/src/timecode/timecode_generator.v"
(_format verilog)
(_timespec "2024-01-10T21:12:26")
)
)
)
@ -170,9 +174,9 @@
(_format verilog)
(_timespec "2023-12-13T19:30:23")
)
(_file "source/test/test_top.v" + "test_top:"
(_file "source/test/test_top.v"
(_format verilog)
(_timespec "2024-01-08T22:10:21")
(_timespec "2024-01-10T21:14:18")
)
(_file "source/test/test_uart_reg_reader.v"
(_format verilog)
@ -182,6 +186,10 @@
(_format verilog)
(_timespec "2023-12-15T22:10:16")
)
(_file "source/test/test_timecode_generator.v" + "test_timecode_generator:"
(_format verilog)
(_timespec "2024-01-10T21:54:42")
)
)
)
)
@ -191,17 +199,17 @@
(_db_output
(_file "compile/Top_comp.adf"
(_format adif)
(_timespec "2024-01-10T14:20:35")
(_timespec "2024-01-10T20:00:19")
)
)
(_output
(_file "compile/Top.cmr"
(_format verilog)
(_timespec "2024-01-10T14:20:34")
(_timespec "2024-01-10T20:00:18")
)
(_file "compile/cmr.db"
(_format text)
(_timespec "2024-01-10T14:20:35")
(_timespec "2024-01-10T20:00:19")
)
)
)
@ -211,9 +219,29 @@
)
(_task tsk_synthesis
(_command cmd_synthesize
(_gci_state (_integer 0))
(_gci_state (_integer 3))
(_option ads (_switch ON))
(_option selected_syn_tool_opt (_integer 2))
(_db_output
(_file "synthesize/Top_syn.adf"
(_format adif)
(_timespec "2024-01-10T20:00:28")
)
)
(_output
(_file "synthesize/Top_syn.vm"
(_format structural_verilog)
(_timespec "2024-01-10T20:00:29")
)
(_file "synthesize/Top.snr"
(_format text)
(_timespec "2024-01-10T20:00:29")
)
(_file "synthesize/snr.db"
(_format text)
(_timespec "2024-01-10T20:00:29")
)
)
)
(_widget wgt_tech_view
(_attribute _click_to_run (_switch ON))

38
source/src/timecode/timecode_basesig_generator.v
View File

@ -1,12 +1,16 @@
module timecode_basesig_generator #(
parameter SYS_CLOCK_FREQ = 50000000
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk,
input rst_n,
input [31:0] timecode_format,
input wire ctrl_sig,
output reg out_timecode_trigger_sig,
output reg out_first_frame_sig,
input wire en,
output out_timecode_trigger_sig,
output reg out_first_frame_sig,
output reg [7:0] out_frame_num,
output reg out_drop_frame
@ -32,61 +36,61 @@ module timecode_basesig_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2398)
.OUTPUT_FREQ_P00(2398)
) fps2398format (
.clk(clk),
.rst_n(rst_n),
.ctrl_sig(ctrl_sig),
.ctrl_sig(en),
.output_signal(fps2398format_clk)
);
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2400)
.OUTPUT_FREQ_P00(2400)
) fps2400format (
.clk(clk),
.rst_n(rst_n),
.ctrl_sig(ctrl_sig),
.ctrl_sig(en),
.output_signal(fps2400format_clk)
);
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2500)
.OUTPUT_FREQ_P00(2500)
) fps2500format (
.clk(clk),
.rst_n(rst_n),
.ctrl_sig(ctrl_sig),
.ctrl_sig(en),
.output_signal(fps2500format_clk)
);
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2997)
.OUTPUT_FREQ_P00(2997)
) fps2997format (
.clk(clk),
.rst_n(rst_n),
.ctrl_sig(ctrl_sig),
.ctrl_sig(en),
.output_signal(fps2997format_clk)
);
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2997)
.OUTPUT_FREQ_P00(2997)
) fps2997dropformat (
.clk(clk),
.rst_n(rst_n),
.ctrl_sig(ctrl_sig),
.ctrl_sig(en),
.output_signal(fps2997dropformat_clk)
);
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(3000)
.OUTPUT_FREQ_P00(3000)
) fps3000format (
.clk(clk),
.rst_n(rst_n),
.ctrl_sig(ctrl_sig),
.ctrl_sig(en),
.output_signal(fps3000format_clk)
);
@ -113,7 +117,7 @@ module timecode_basesig_generator #(
always @(posedge clk or negedge rst_n) begin
if (!rst_n || !ctrl_sig) begin
if (!rst_n || !en) begin
out_first_frame_sig <= 1;
end else begin
if (out_first_frame_sig && out_timecode_trigger_sig) begin

179
source/src/timecode/timecode_generator.v
View File

@ -1,6 +1,6 @@
module timecode_generator #(
parameter SYS_CLOCK_FREQ = 50000000
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk, //clock input
input rst_n, //asynchronous reset input, low active
@ -9,141 +9,102 @@ module timecode_generator #(
input timecode0_wen,
input [31:0] timecode0,
output [31:0] timecode0_export,
input timecode1_wen,
input [31:0] timecode1,
output [31:0] timecode1_export,
input en,
output reg out_timecode_serial_data,
output reg out_trigger_sig,
output reg [31:0] out_timecode0,
output reg [31:0] out_timecode1
output wire out_timecode_serial_data,
output wire out_trigger_sig,
output wire [31:0] out_timecode0,
output wire [31:0] out_timecode1
);
// Rate 1/2Fe 1Fe
// 23.98 F/s 260.7 us 521.4 us
// 24.00 F/s 260.4 us 520.8 us
// 25.00 F/s 250.0 us 500.0 us
// 29.97 F/s 208.5 us 417.1 us
// 30.00 F/s 208.3 us 416.7 us
localparam FPS2398Format = 0;
localparam FPS2400Format = 1;
localparam FPS2500Format = 2;
localparam FPS2997Format = 3;
localparam FPS2997DropFormat = 4;
localparam FPS3000Format = 5;
localparam FPS2398FormatOneHalfFe = (260.7 * 1000) / (1000000000 / SYS_CLOCK_FREQ);
localparam FPS2400FormatOneHalfFe = (260.4 * 1000) / (1000000000 / SYS_CLOCK_FREQ);
localparam FPS2500FormatOneHalfFe = (250.0 * 1000) / (1000000000 / SYS_CLOCK_FREQ);
localparam FPS2997FormatOneHalfFe = (208.5 * 1000) / (1000000000 / SYS_CLOCK_FREQ);
localparam FPS2997DropFormatOneHalfFe = (208.5 * 1000) / (1000000000 / SYS_CLOCK_FREQ);
localparam FPS3000FormatOneHalfFe = (208.3 * 1000) / (1000000000 / SYS_CLOCK_FREQ);
reg [31:0] timecode_onehalf_bit_count;
always @(*) begin
case (freqtimecode_format)
FPS2398Format: timecode_onehalf_bit_count = FPS2398FormatOneHalfFe;
FPS2400Format: timecode_onehalf_bit_count = FPS2400FormatOneHalfFe;
FPS2500Format: timecode_onehalf_bit_count = FPS2500FormatOneHalfFe;
FPS2997Format: timecode_onehalf_bit_count = FPS2997FormatOneHalfFe;
FPS2997DropFormat: timecode_onehalf_bit_count = FPS2997DropFormatOneHalfFe;
FPS3000Format: timecode_onehalf_bit_count = FPS3000FormatOneHalfFe;
default: timecode_onehalf_bit_count = FPS2398FormatOneHalfFe;
endcase
end
/*******************************************************************************
* workflag *
*******************************************************************************/
reg workflag;
reg endsig;
//
//
reg [31:0] timecode_tc_cache;
reg [31:0] timecode_uc_cache;
reg [64:0] timecode_bit_val;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
workflag <= 0;
timecode_tc_cache <= 0;
timecode_uc_cache <= 0;
end else begin
if (trigger_sig) begin
timecode_tc_cache <= timecode_tc_data;
timecode_uc_cache <= timecode_uc_data;
workflag <= 1;
end else if (workflag && endsig) begin
workflag <= 0;
end
end
end
wire [7:0] out_frame_num;
wire out_drop_frame;
/*******************************************************************************
* tigger_sig *
*******************************************************************************/
reg [31:0] halfbitcount;
reg tigger_sig;
always @(posedge clk or negedge rst_n) begin
if (!rst_n || !workflag) begin
halfbitcount <= 0;
tigger_sig <= 0;
end else begin
if (halfbitcount == timecode_onehalf_bit_count) begin
halfbitcount <= 0;
end else begin
halfbitcount <= halfbitcount + 1;
end
wire frame_trigger_sig;
wire first_frame_sig;
if (halfbitcount == 0) begin
tigger_sig <= 1;
end else begin
tigger_sig <= 0;
end
end
end
//
// trigger : | | | | | |
// onebitoff: 0000000001111111111000000001111111110000000001
// bitoff : 0000000000000000000111111111111111112222222222
//
//
timecode_basesig_generator #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) basesig_generator (
.clk(clk),
.rst_n(rst_n),
.timecode_format(timecode_format),
.en(en),
.out_timecode_trigger_sig(frame_trigger_sig), //帧时钟触发信号
.out_first_frame_sig(first_frame_sig),
.out_frame_num(out_frame_num),
.out_drop_frame(out_drop_frame)
);
reg [ 1:0] onebitoff;
reg [31:0] bitoff;
reg [63:0] timecode;
wire [63:0] timecode_next;
timecode_nextcode nextcode (
.frame_mum(out_frame_num),
.drop(out_drop_frame),
.timecode(timecode),
.timecode_next(timecode_next)
);
reg timecode_trigger_sig;
always @(posedge clk or negedge rst_n) begin
if (!rst_n || !workflag) begin
onebitoff <= 1;
bitoff <= 0;
if (!rst_n) begin
timecode <= 0;
timecode_trigger_sig <= 0;
end else if (!en) begin
if (timecode0_wen || timecode1_wen) begin
if (timecode0_wen) begin
timecode[31:0] <= timecode0;
end
if (timecode1_wen) begin
timecode[63:32] <= timecode1;
end
end
end else begin
if (tigger_sig) begin
if (onebit_off == 1) begin
bitoff <= bitoff + 1;
onebit_off <= 0;
end else begin
onebit_off <= 1;
if (frame_trigger_sig) begin
if (!first_frame_sig) begin
timecode <= timecode_next;
end
timecode_trigger_sig <= 1;
end else begin
timecode_trigger_sig <= 0;
end
end
end
assign timecode0_export = timecode[31:0];
assign timecode1_export = timecode[63:32];
wire [63:0] out_timecode;
timecode_serialization #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) serialization (
.clk(clk),
.rst_n(rst_n),
.timecode_format(timecode_format),
reg change_sig;
.trigger_sig(timecode_trigger_sig),
.timecode(timecode),
.out_timecode_serial_data(out_timecode_serial_data),
.out_trigger_sig(out_trigger_sig),
.out_timecode(out_timecode)
);
// out_timecode0
// out_timecode1
assign out_timecode0 = out_timecode[31:0];
assign out_timecode1 = out_timecode[63:32];
endmodule

232
source/src/timecode/timecode_nextcode.v
View File

@ -47,6 +47,24 @@ module timecode_nextcode (
// reg [63:0] next_frame;
reg [63:0] next_frame;
wire [7:0] n_10hour;
wire [7:0] n_hour;
wire [7:0] n_10min;
wire [7:0] n_min;
wire [7:0] n_10sec;
wire [7:0] n_sec;
wire [7:0] n_10frame;
wire [7:0] n_frame;
assign n_10hour[7:0] = next_frame[63:56];
assign n_hour[7:0] = next_frame[55:48];
assign n_10min[7:0] = next_frame[47:40];
assign n_min[7:0] = next_frame[39:32];
assign n_10sec[7:0] = next_frame[31:24];
assign n_sec[7:0] = next_frame[23:16];
assign n_10frame[7:0] = next_frame[15:8];
assign n_frame[7:0] = next_frame[7:0];
function [63:0] assign_timecode;
input [7:0] hour_tens;
@ -57,13 +75,22 @@ module timecode_nextcode (
input [7:0] sec_units;
input [7:0] frame_tens;
input [7:0] frame_units;
assign_timecode = {
frame_units, frame_tens, sec_units, sec_tens, min_units, min_tens, hour_units, hour_tens
};
begin
assign_timecode[7:0] = frame_units;
assign_timecode[15:8] = frame_tens;
assign_timecode[23:16] = sec_units;
assign_timecode[31:24] = sec_tens;
assign_timecode[39:32] = min_units;
assign_timecode[47:40] = min_tens;
assign_timecode[55:48] = hour_units;
assign_timecode[63:56] = hour_tens;
end
endfunction
always @(*) begin
/*******************************************************************************
* HOUR *
@ -125,5 +152,202 @@ module timecode_nextcode (
assign_timecode(hour10, hour, min10, min, sec10, sec, frame10, now_frame_units + 1);
end
end
assign timecode_next = next_frame;
// always @(*) begin
// /*******************************************************************************
// * HOUR *
// *******************************************************************************/
// if (houris23 && minis59 && secis59 && frameisfinal) begin //23:59:59:29
// n_10hour <= 0;
// n_hour <= 0;
// n_10min <= 0;
// n_min <= 0;
// n_10sec <= 0;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (houris19 && minis59 && secis59 && frameisfinal) begin //19:59:59:29
// n_10hour <= 2;
// n_hour <= 0;
// n_10min <= 0;
// n_min <= 0;
// n_10sec <= 0;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (houris09 && minis59 && secis59 && frameisfinal) begin //09:59:59:29
// n_10hour <= 1;
// n_hour <= 0;
// n_10min <= 0;
// n_min <= 0;
// n_10sec <= 0;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (minis59 && secis59 && frameisfinal) begin //xx:59:59:29
// n_10hour <= hour10;
// n_hour <= hour + 1;
// n_10min <= 0;
// n_min <= 0;
// n_10sec <= 0;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end /*******************************************************************************
// * MIN *
// *******************************************************************************/
// else if (minis49 && secis59 && frameisfinal) begin // xx:49:59:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= 5;
// n_min <= 0;
// n_10sec <= 0;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (minis39 && secis59 && frameisfinal) begin // xx:39:59:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= 4;
// n_min <= 0;
// n_10sec <= 0;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (minis29 && secis59 && frameisfinal) begin // xx:29:59:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= 3;
// n_min <= 0;
// n_10sec <= 0;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (minis19 && secis59 && frameisfinal) begin // xx:19:59:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= 2;
// n_min <= 0;
// n_10sec <= 0;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (minis09 && secis59 && frameisfinal) begin // xx:09:59:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= 1;
// n_min <= 0;
// n_10sec <= 0;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end /*******************************************************************************
// * SECOND *
// *******************************************************************************/
// else if (secis49 && frameisfinal) begin // xx:xx:49:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= min10;
// n_min <= min;
// n_10sec <= 5;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (secis39 && frameisfinal) begin // xx:xx:39:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= min10;
// n_min <= min;
// n_10sec <= 4;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (secis29 && frameisfinal) begin // xx:xx:29:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= min10;
// n_min <= min;
// n_10sec <= 3;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (secis19 && frameisfinal) begin // xx:xx:19:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= min10;
// n_min <= min;
// n_10sec <= 2;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (secis09 && frameisfinal) begin // xx:xx:09:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= min10;
// n_min <= min;
// n_10sec <= 1;
// n_sec <= 0;
// n_10frame <= 0;
// n_frame <= 0;
// end else if (frameisfinal) begin // xx:xx:xx:29
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= min10;
// n_min <= min;
// n_10sec <= sec10;
// n_sec <= sec;
// n_10frame <= 0;
// n_frame <= 0;
// end /*******************************************************************************
// * FRAME *
// *******************************************************************************/
// else if (frameis19) begin // xx:xx:xx:19
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= min10;
// n_min <= min;
// n_10sec <= sec10;
// n_sec <= sec;
// n_10frame <= 2;
// n_frame <= 0;
// end else
// if (frameis09) begin // xx:xx:xx:09
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= min10;
// n_min <= min;
// n_10sec <= sec10;
// n_sec <= sec;
// n_10frame <= 1;
// n_frame <= 0;
// end else begin
// n_10hour <= hour10;
// n_hour <= hour;
// n_10min <= min10;
// n_min <= min;
// n_10sec <= sec10;
// n_sec <= sec;
// n_10frame <= frame10;
// n_frame <= now_frame_units + 1;
// end
// end
// assign timecode_next = next_frame;
// assign timecode_next[7:0] = n_frame;
// assign timecode_next[15:8] = n_10frame;
// assign timecode_next[23:16] = n_sec;
// assign timecode_next[31:24] = n_10sec;
// assign timecode_next[39:32] = n_min;
// assign timecode_next[47:40] = n_10min;
// assign timecode_next[55:48] = n_hour;
// assign timecode_next[63:56] = n_10hour;
// wire [63:0] tmp_timecode_next;
// assign tmp_timecode_next = timecode + 1;
// assign timecode_next = tmp_timecode_next;
endmodule

118
source/src/timecode/timecode_serialization.v
View File

@ -1,6 +1,6 @@
module timecode_serialization #(
parameter SYS_CLOCK_FREQ = 50000000
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk,
input rst_n,
@ -84,7 +84,7 @@ module timecode_serialization #(
end else begin
if (trigger_sig && startflag) begin // 重启
oneframe_timeout_counter <= oneframe_timeout_count;
internal_ctrl_sig = RESTART_CTRL_SIG;
internal_ctrl_sig <= RESTART_CTRL_SIG;
startflag <= 1;
end else if (trigger_sig && !startflag) begin //启动
oneframe_timeout_counter <= oneframe_timeout_count;
@ -103,21 +103,17 @@ module timecode_serialization #(
end
reg workflag;
reg [79:0] in_timecode_cache;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
workflag <= 0;
in_timecode_cache <= 0;
end else begin
case (internal_ctrl_sig)
START_CTRL_SIG, RESTART_CTRL_SIG: begin
in_timecode_cache[63:0] <= timecode;
in_timecode_cache[63:0] <= timecode;
in_timecode_cache[79:64] <= 16'b1011_1111_1111_1100;
workflag <= 1;
end
STOP_CTRL_SIG: begin
workflag <= 0;
end
default: begin
end
@ -127,7 +123,7 @@ module timecode_serialization #(
//
// trigger : | | | | | |
// trigger : | | | | |
// onebitoff: 0000000001111111111000000001111111110000000001
// bitoff : 0000000000000000000111111111111111112222222222
//
@ -137,22 +133,30 @@ module timecode_serialization #(
reg [31:0] halfbitcount;
reg bit_tigger_sig;
always @(posedge clk) begin
if (!rst_n || !workflag) begin
if (!rst_n) begin
halfbitcount <= 0;
bit_tigger_sig <= 0;
end else begin
if (halfbitcount == timecode_onehalf_bit_count) begin
halfbitcount <= 0;
end else begin
halfbitcount <= halfbitcount + 1;
end
if (halfbitcount == 0) begin
bit_tigger_sig <= 1;
end else begin
bit_tigger_sig <= 0;
end
case (internal_ctrl_sig)
START_CTRL_SIG, RESTART_CTRL_SIG: begin
halfbitcount <= 0;
bit_tigger_sig <= 0;
end
STOP_CTRL_SIG: begin
halfbitcount <= 0;
bit_tigger_sig <= 0;
end
default: begin
if (halfbitcount == timecode_onehalf_bit_count) begin
halfbitcount <= 0;
bit_tigger_sig <= 1;
end else begin
halfbitcount <= halfbitcount + 1;
bit_tigger_sig <= 0;
end
end
endcase
end
end
@ -160,20 +164,33 @@ module timecode_serialization #(
reg [ 1:0] onebitoff;
reg [31:0] bitoff;
always @(posedge clk) begin
if (!rst_n || !workflag) begin
onebitoff <= 1;
if (!rst_n) begin
onebitoff <= 0;
bitoff <= 0;
end else begin
if (bit_tigger_sig) begin
if (onebitoff == 1) begin
if (bitoff < 79) begin
bitoff <= bitoff + 1;
end
case (internal_ctrl_sig)
START_CTRL_SIG, RESTART_CTRL_SIG: begin
onebitoff <= 0;
end else begin
onebitoff <= 1;
bitoff <= 0;
end
end
STOP_CTRL_SIG: begin
onebitoff <= 0;
bitoff <= 0;
end
default: begin
if (bit_tigger_sig) begin
if (onebitoff == 1) begin
if (bitoff < 79) begin
bitoff <= bitoff + 1;
end
onebitoff <= 0;
end else begin
onebitoff <= 1;
end
end
end
endcase
end
end
@ -183,18 +200,41 @@ module timecode_serialization #(
out_timecode_serial_data <= 0;
end else begin
if (bit_tigger_sig) begin
if (onebitoff == 1) begin
case (internal_ctrl_sig)
/*******************************************************************************
* 启动 *
*******************************************************************************/
START_CTRL_SIG: begin
out_timecode_serial_data <= ~out_timecode_serial_data;
end else begin
if (in_timecode_cache[bitoff] == 1) begin
out_timecode_serial_data <= ~out_timecode_serial_data;
end else begin
out_timecode_serial_data <= out_timecode_serial_data;
end
end
end
/*******************************************************************************
* 重启 *
*******************************************************************************/
RESTART_CTRL_SIG: begin
out_timecode_serial_data <= ~out_timecode_serial_data;
end
/*******************************************************************************
* 停止 *
*******************************************************************************/
STOP_CTRL_SIG: begin
out_timecode_serial_data <= out_timecode_serial_data;
end
default: begin
if (bit_tigger_sig) begin
if (onebitoff == 1) begin
out_timecode_serial_data <= ~out_timecode_serial_data;
end else begin
if (in_timecode_cache[bitoff] == 1) begin
out_timecode_serial_data <= ~out_timecode_serial_data;
end else begin
out_timecode_serial_data <= out_timecode_serial_data;
end
end
end
end
endcase
end
end

51
source/src/xsync_internal_generator.v
View File

@ -50,7 +50,7 @@
module xsync_internal_generator #(
parameter REG_START_ADD = 0,
parameter SYS_CLOCK_FREQ = 50000000,
parameter SYS_CLOCK_FREQ = 10000000,
parameter TEST = 0,
parameter ID = 1
) (
@ -266,6 +266,55 @@ module xsync_internal_generator #(
//
// module timecode_generator #(
// parameter SYS_CLOCK_FREQ = 10000000
// ) (
// input clk, //clock input
// input rst_n, //asynchronous reset input, low active
// input [31:0] timecode_format,
// input timecode0_wen,
// input [31:0] timecode0,
// input timecode1_wen,
// input [31:0] timecode1,
// input en,
// output wire out_timecode_serial_data,
// output wire out_trigger_sig,
// output wire [31:0] out_timecode0,
// output wire [31:0] out_timecode1
// );
// r6_timecode0
// r7_timecode1
timecode_generator #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
) timecode_generator_ist (
.clk (clk),
.rst_n(rst_n),
.timecode_format(r3_timecode_format),
.timecode0_wen(addr == 6),
.timecode0(wr_data),
.timecode1_wen(addr == 7),
.timecode1(wr_data),
.timecode0_export(r6_timecode0),
.timecode1_export(r7_timecode1),
.en(en),
.out_timecode_serial_data(out_timecode_serial_sig),
.out_trigger_sig(out_timecode_tirgger_sig),
.out_timecode0(out_timecode_sig[31:0]),
.out_timecode1(out_timecode_sig[63:32])
);
// internal_timecode_generator #(
// .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ)
// ) internal_timecode_generator (

2
source/src/xsync_internal_sub/internal_timecode_generator.v
View File

@ -1,6 +1,6 @@
module internal_timecode_generator #(
parameter SYS_CLOCK_FREQ = 50000000
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk, //clock input
input rst_n, //asynchronous reset input, low active

63
source/src/zutils/ztutils_timecode_next_code_v2.v
View File

@ -1,63 +0,0 @@
module ztutils_timecode_next_code (
input [31:0] frameFormat,
input [63:0] timecode_now,
output [31:0] timecode_next
);
// // timecode_next
// wire [7:0] frame;
// wire [7:0] sec;
// wire [7:0] min;
// wire [7:0] hour;
// reg [7:0] next_frame;
// reg [7:0] next_sec;
// reg [7:0] next_min;
// reg [7:0] next_hour;
// assign frame = timecode[7:0];
// assign sec = timecode[15:8];
// assign min = timecode[23:16];
// assign hour = timecode[31:24];
// always @(*) begin
// if (hour == 23 && min == 59 && sec == 59 && frame == (frameNum - 1)) begin
// next_frame <= 0;
// next_sec <= 0;
// next_min <= 0;
// next_hour <= 0;
// end else if (min == 59 && sec == 59 && frame == (frameNum - 1)) begin
// next_frame <= 0;
// next_sec <= 0;
// next_min <= 0;
// next_hour <= hour + 1;
// end else if (sec == 59 && frame == (frameNum - 1)) begin
// if (drop && !(min == 49 || min == 39 || min == 29 || min == 19 || min == 9)) begin
// //丢帧模式
// next_frame <= 2;
// next_sec <= 0;
// next_min <= min + 1;
// next_hour <= hour;
// end else begin
// //正常模式
// next_frame <= 0;
// next_sec <= 0;
// next_min <= min + 1;
// next_hour <= hour;
// end
// end else if (frame == (frameNum - 1)) begin
// next_frame <= 0;
// next_sec <= sec + 1;
// next_min <= min;
// next_hour <= hour;
// end else begin
// next_frame <= frame + 1;
// next_sec <= sec;
// next_min <= min;
// next_hour <= hour;
// end
// end
endmodule

20
source/src/zutils/zutils_genlock_clk_generator.v
View File

@ -1,5 +1,5 @@
module zutils_genlock_clk_generator #(
parameter SYS_CLOCK_FREQ = 50000000
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk, //clock input
input rst_n, //asynchronous reset input, low active
@ -20,7 +20,7 @@ module zutils_genlock_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2397)
.OUTPUT_FREQ_P00(2397)
) genlock_2397 (
.clk(clk),
.rst_n(rst_n),
@ -30,7 +30,7 @@ module zutils_genlock_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2398)
.OUTPUT_FREQ_P00(2398)
) genlock_2398 (
.clk(clk),
.rst_n(rst_n),
@ -40,7 +40,7 @@ module zutils_genlock_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2400)
.OUTPUT_FREQ_P00(2400)
) genlock_2400 (
.clk(clk),
.rst_n(rst_n),
@ -50,7 +50,7 @@ module zutils_genlock_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2500)
.OUTPUT_FREQ_P00(2500)
) genlock_2500 (
.clk(clk),
.rst_n(rst_n),
@ -60,7 +60,7 @@ module zutils_genlock_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2997)
.OUTPUT_FREQ_P00(2997)
) genlock_2997 (
.clk(clk),
.rst_n(rst_n),
@ -70,7 +70,7 @@ module zutils_genlock_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(3000)
.OUTPUT_FREQ_P00(3000)
) genlock_3000 (
.clk(clk),
.rst_n(rst_n),
@ -80,7 +80,7 @@ module zutils_genlock_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(5000)
.OUTPUT_FREQ_P00(5000)
) genlock_5000 (
.clk(clk),
.rst_n(rst_n),
@ -90,7 +90,7 @@ module zutils_genlock_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(5994)
.OUTPUT_FREQ_P00(5994)
) genlock_5994 (
.clk(clk),
.rst_n(rst_n),
@ -100,7 +100,7 @@ module zutils_genlock_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(6000)
.OUTPUT_FREQ_P00(6000)
) genlock_6000 (
.clk(clk),
.rst_n(rst_n),

2
source/src/zutils/zutils_muti_debug_signal_gen.v
View File

@ -1,5 +1,5 @@
module zutils_muti_debug_signal_gen #(
parameter SYS_CLOCK_FREQ = 50000000
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk,
input rst_n,

2
source/src/zutils/zutils_pluse_generator.v
View File

@ -1,5 +1,5 @@
module zutils_pluse_generator #(
parameter SYS_CLOCK_FREQ = 50000000
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk, //clock input
input rst_n, //asynchronous reset input, low active

2
source/src/zutils/zutils_pwm_generator.v
View File

@ -1,5 +1,5 @@
module zutils_pwm_generator #(
parameter SYS_CLOCK_FREQ = 50000000,
parameter SYS_CLOCK_FREQ = 10000000,
parameter OUTPUT_FREQ = 1000
) (
input clk,

6
source/src/zutils/zutils_pwm_generator_advanced.v
View File

@ -1,6 +1,6 @@
module zutils_pwm_generator_advanced #(
parameter SYS_CLOCK_FREQ = 50000000,
parameter OUTPUT_FREQ = 1000
parameter SYS_CLOCK_FREQ = 10000000,
parameter OUTPUT_FREQ_P00 = 1000 //10.00HZ
) (
input clk,
input rst_n,
@ -8,7 +8,7 @@ module zutils_pwm_generator_advanced #(
output reg output_signal
);
localparam COUNT = SYS_CLOCK_FREQ / OUTPUT_FREQ;
localparam COUNT = (SYS_CLOCK_FREQ * 100) / OUTPUT_FREQ_P00;
reg [31:0] counter = 0;
always @(posedge clk or negedge rst_n) begin

14
source/src/zutils/zutils_smpte_timecode_clk_generator.v
View File

@ -1,5 +1,5 @@
module zutils_smpte_timecode_clk_generator #(
parameter SYS_CLOCK_FREQ = 50000000
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk, //clock input
input rst_n, //asynchronous reset input, low active
@ -15,7 +15,7 @@ module zutils_smpte_timecode_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2398)
.OUTPUT_FREQ_P00(2398)
) fps2398format (
.clk(clk),
.rst_n(rst_n),
@ -25,7 +25,7 @@ module zutils_smpte_timecode_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2400)
.OUTPUT_FREQ_P00(2400)
) fps2400format (
.clk(clk),
.rst_n(rst_n),
@ -35,7 +35,7 @@ module zutils_smpte_timecode_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2500)
.OUTPUT_FREQ_P00(2500)
) fps2500format (
.clk(clk),
.rst_n(rst_n),
@ -45,7 +45,7 @@ module zutils_smpte_timecode_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2997)
.OUTPUT_FREQ_P00(2997)
) fps2997format (
.clk(clk),
.rst_n(rst_n),
@ -55,7 +55,7 @@ module zutils_smpte_timecode_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(2997)
.OUTPUT_FREQ_P00(2997)
) fps2997dropformat (
.clk(clk),
.rst_n(rst_n),
@ -65,7 +65,7 @@ module zutils_smpte_timecode_clk_generator #(
zutils_pwm_generator_advanced #(
.SYS_CLOCK_FREQ(SYS_CLOCK_FREQ),
.OUTPUT_FREQ(3000)
.OUTPUT_FREQ_P00(3000)
) fps3000format (
.clk(clk),
.rst_n(rst_n),

2
source/src/zutils/zutils_timecode_convert.v
View File

@ -14,7 +14,7 @@
module zutils_timecode_convert #(
parameter SYS_CLOCK_FREQ = 50000000
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk, //clock input
input rst_n, //asynchronous reset input, low active

2
source/src/zutils/zutils_timecode_serial_data_gen.v
View File

@ -1,6 +1,6 @@
module internal_timecode_generator #(
parameter SYS_CLOCK_FREQ = 50000000
parameter SYS_CLOCK_FREQ = 10000000
) (
input clk, //clock input
input rst_n, //asynchronous reset input, low active

90
source/test/test_timecode_generator.v
View File

@ -0,0 +1,90 @@
`timescale 10ns / 10ns
module test_timecode_generator;
// module timecode_generator #(
// parameter SYS_CLOCK_FREQ = 10000000
// ) (
// input clk, //clock input
// input rst_n, //asynchronous reset input, low active
// input [31:0] timecode_format,
// input timecode0_wen,
// input [31:0] timecode0,
// input timecode1_wen,
// input [31:0] timecode1,
// input en,
// output wire out_timecode_serial_data,
// output wire out_trigger_sig,
// output wire [31:0] out_timecode0,
// output wire [31:0] out_timecode1
// )
reg sys_clk;
reg rst_n;
reg [31:0] timecode_format;
reg timecode0_wen;
reg [31:0] timecode0;
reg timecode1_wen;
reg [31:0] timecode1;
reg en;
wire out_timecode_serial_data;
wire out_trigger_sig;
wire [31:0] out_timecode0;
wire [31:0] out_timecode1;
timecode_generator #(
.SYS_CLOCK_FREQ(10000000)
) timecode_generator_inst (
.clk(sys_clk),
.rst_n(rst_n),
.timecode_format(timecode_format),
.timecode0_wen(timecode0_wen),
.timecode0(timecode0),
.timecode1_wen(timecode1_wen),
.timecode1(timecode1),
.en(en),
.out_timecode_serial_data(out_timecode_serial_data),
.out_trigger_sig(out_trigger_sig),
.out_timecode0(out_timecode0),
.out_timecode1(out_timecode1)
);
localparam FPS2398Format = 0;
localparam FPS2400Format = 1;
localparam FPS2500Format = 2;
localparam FPS2997Format = 3;
localparam FPS2997DropFormat = 4;
localparam FPS3000Format = 5;
initial begin
sys_clk = 0;
rst_n = 0;
en = 0;
timecode0_wen = 0;
timecode1_wen = 0;
timecode0 = 0;
timecode1 = 0;
timecode_format = FPS2398Format;
#100;
rst_n = 1;
#100;
en = 1;
#100000000;
$stop;
end
always #5 sys_clk = ~sys_clk; // 50MHZ时钟
endmodule

3
source/test/test_top.v
View File

@ -1,4 +1,4 @@
`timescale 10ns / 10ns
`timescale 5ns / 5ns
module test_top;
reg sys_clk;
reg rst_n;
@ -86,6 +86,7 @@ module test_top;
#100;
rst_n = 1;
#100;
spi_write_reg(16'h0020, 32'h00000001);
spi_write_reg(16'h0021, 32'h00000010);

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