From 3ebac6a5d98d61364745f619036f158e70b2732c Mon Sep 17 00:00:00 2001 From: zhaohe Date: Sat, 23 Mar 2024 20:35:32 +0800 Subject: [PATCH] =?UTF-8?q?=E9=83=A8=E5=88=86=E6=A8=A1=E5=9D=97=E6=B7=BB?= =?UTF-8?q?=E5=8A=A0=E9=A2=91=E7=8E=87=E6=8E=A2=E6=B5=8B=E5=8A=9F=E8=83=BD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- led_test.pds | 24 +- source/src/input/timecode_input.v | 14 +- source/src/internal/internal_timecode_generator.v | 11 +- source/src/sys/sys_timecode.v | 14 + source/src/xsync_internal_generator.v | 315 ---------------------- 5 files changed, 44 insertions(+), 334 deletions(-) diff --git a/led_test.pds b/led_test.pds index 5132bab..2497fd9 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Mar 23 19:29:12 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sat Mar 23 20:35:10 2024") (_version "1.0.5") (_status "initial") (_project @@ -83,7 +83,7 @@ ) (_file "source/src/xsync_internal_generator.v" (_format verilog) - (_timespec "2024-03-04T18:58:03") + (_timespec "2024-03-23T19:55:54") ) (_file "source/src/zutils/zutils_pwm_generator_advanced.v" (_format verilog) @@ -131,7 +131,7 @@ ) (_file "source/src/input/timecode_input.v" (_format verilog) - (_timespec "2024-03-23T19:14:39") + (_timespec "2024-03-23T19:37:51") ) (_file "source/src/timecode/timecode_decoder.v" (_format verilog) @@ -179,11 +179,11 @@ ) (_file "source/src/internal/internal_timecode_generator.v" (_format verilog) - (_timespec "2024-03-23T16:37:37") + (_timespec "2024-03-23T20:29:33") ) (_file "source/src/sys/sys_timecode.v" (_format verilog) - (_timespec "2024-03-04T22:11:20") + (_timespec "2024-03-23T20:10:27") ) (_file "source/src/input/genlock_input_module.v" (_format verilog) @@ -315,17 +315,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-03-23T19:28:26") + (_timespec "2024-03-23T20:34:02") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-03-23T19:28:24") + (_timespec "2024-03-23T20:33:59") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-03-23T19:28:26") + (_timespec "2024-03-23T20:34:02") ) ) ) @@ -341,21 +341,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-03-23T19:29:07") + (_timespec "2024-03-23T20:34:48") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-03-23T19:29:10") + (_timespec "2024-03-23T20:35:00") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-03-23T19:29:12") + (_timespec "2024-03-23T20:35:09") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-03-23T19:29:12") + (_timespec "2024-03-23T20:35:10") ) ) ) diff --git a/source/src/input/timecode_input.v b/source/src/input/timecode_input.v index fe4014b..58b80bd 100644 --- a/source/src/input/timecode_input.v +++ b/source/src/input/timecode_input.v @@ -1,3 +1,4 @@ +`include "../config.v" module timecode_input_parser #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 10000000 @@ -73,6 +74,7 @@ module timecode_input_parser #( r1_timecode_sig_selt <= 1; r2_ch1_timecode_format <= 0; r6_ch2_timecode_format <= 0; + rA_freq_bias <= `FREQ_DETECT_BIAS_DEFAULT; end else begin if (reg_wr_sig) begin case (reg_wr_index) @@ -110,12 +112,12 @@ module timecode_input_parser #( ); zutils_freq_detector_v2 freq_detector1 ( - .clk (clk), - .rst_n (rst_n), - .freq_detect_bias(rA_freq_bias), - .pluse_input (ch1_timecode_tigger_sig), - .pluse_width_cnt (r5_ch1_freq) -); + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(rA_freq_bias), + .pluse_input (ch1_timecode_tigger_sig), + .pluse_width_cnt (r5_ch1_freq) + ); timecode_decoder #( .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) diff --git a/source/src/internal/internal_timecode_generator.v b/source/src/internal/internal_timecode_generator.v index ad68a96..0fd27e5 100644 --- a/source/src/internal/internal_timecode_generator.v +++ b/source/src/internal/internal_timecode_generator.v @@ -27,7 +27,7 @@ module internal_timecode_generator #( reg [31:0] reg2_timecode_format; //!内部时码格式 wire [31:0] reg3_timecode_data0; //!时码数值0 wire [31:0] reg4_timecode_data1; //!时码数值1 - + wire [31:0] reg5_detect_freq; //!输出频率探测 wire [31:0] reg_wr_index; //!寄存器写入时相对地址 @@ -91,6 +91,15 @@ module internal_timecode_generator #( .out_timecode1 (timecode_data[63:32]) ); + // reg5_detect_freq + + zutils_freq_detector_v2 freq_detector1 ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(1), + .pluse_input (timecode_tigger_sig), + .pluse_width_cnt (reg5_detect_freq) + ); assign timecode_format = reg2_timecode_format; endmodule diff --git a/source/src/sys/sys_timecode.v b/source/src/sys/sys_timecode.v index 16055b2..021089d 100644 --- a/source/src/sys/sys_timecode.v +++ b/source/src/sys/sys_timecode.v @@ -1,3 +1,4 @@ +`include "../config.v" module sys_timecode #( parameter REG_START_ADD = 0, parameter SYS_CLOCK_FREQ = 10000000 @@ -35,6 +36,8 @@ module sys_timecode #( wire [31:0] reg2_sys_timecode_format; //!内部时码格式 wire [31:0] reg3_sys_timecode_data0; //!时码数值0 wire [31:0] reg4_sys_timecode_data1; //!时码数值1 + wire [31:0] reg5_freq_detect; //! + reg [31:0] reg6_freq_detect_bias; //! wire [31:0] reg_wr_index; //!寄存器写入时相对地址 //!TTLOUT_寄存器自动赋值选择器 @@ -51,6 +54,8 @@ module sys_timecode #( .reg2 (reg2_sys_timecode_format), .reg3 (reg3_sys_timecode_data0), .reg4 (reg4_sys_timecode_data1), + .reg5 (reg5_freq_detect), + .reg6 (reg6_freq_detect_bias), .reg_wr_sig(reg_wr_sig), .reg_index (reg_wr_index) ); @@ -59,10 +64,12 @@ module sys_timecode #( always @(posedge clk or negedge rst_n) begin if (!rst_n) begin reg1_sys_timecode_selecter <= 0; + reg6_freq_detect_bias <= `FREQ_DETECT_BIAS_DEFAULT; end else begin if (reg_wr_sig) begin case (reg_wr_index) 1: reg1_sys_timecode_selecter <= wr_data; + 6: reg6_freq_detect_bias <= wr_data; default: begin end endcase @@ -88,6 +95,13 @@ module sys_timecode #( assign reg3_sys_timecode_data0 = sys_timecode_data[31:0]; assign reg4_sys_timecode_data1 = sys_timecode_data[63:32]; + zutils_freq_detector_v2 freq_detector1 ( + .clk (clk), + .rst_n (rst_n), + .freq_detect_bias(reg6_freq_detect_bias), + .pluse_input (sys_timecode_tigger_sig), + .pluse_width_cnt (reg5_freq_detect) + ); endmodule diff --git a/source/src/xsync_internal_generator.v b/source/src/xsync_internal_generator.v index ba50b72..e69de29 100644 --- a/source/src/xsync_internal_generator.v +++ b/source/src/xsync_internal_generator.v @@ -1,315 +0,0 @@ -// // SIGNAL_GENERATOR -// // 启动方式: -// // 1.寄存器控制启动 -// // 2.外部触发启动 -// // 3.TIMECODE触发启动 -// // 帧格式: -// // TIMECODE: -// // 25/30/... -// // GENLOCK: -// // .... -// // 产生: -// // 1.start_state_sig (高电平表示拍照进行中) -// // 2.timecode_sig[64] -// // 3.timecode_tirgger_sig[1] -// // 4.genlock_sig[1] 帧信号,场信号 -// // - -// // TIMECODE_FORMAT -// // FPS2398Format = 0, -// // FPS2400Format = 1, -// // FPS2500Format = 2, -// // FPS2997Format = 3, -// // FPS2997DropFormat = 4, -// // FPS3000Format = 5 - -// // GENLCOK_FORMAT -// // GENLOCK_FPS2397_FORMAT = 0 -// // GENLOCK_FPS2398_FORMAT = 1 -// // GENLOCK_FPS2400_FORMAT = 2 -// // GENLOCK_FPS2500_FORMAT = 3 -// // GENLOCK_FPS2997_FORMAT = 4 -// // GENLOCK_FPS3000_FORMAT = 5 -// // GENLOCK_FPS5000_FORMAT = 6 -// // GENLOCK_FPS5994_FORMAT = 7 -// // GENLOCK_FPS6000_FORMAT = 8 - - - -// module xsync_internal_generator #( -// parameter REG_START_ADD = 0, -// parameter SYS_CLOCK_FREQ = 10000000, -// parameter TEST = 0 -// ) ( -// input clk, //clock input -// input rst_n, //asynchronous reset input, low active - -// //寄存器读写接口 -// input [31:0] addr, -// input [31:0] wr_data, -// input wr_en, -// output wire [31:0] rd_data, - -// input wire ext_ttlin1_module_raw_sig, -// input wire ext_ttlin2_module_raw_sig, -// input wire ext_ttlin3_module_raw_sig, -// input wire ext_ttlin4_module_raw_sig, - -// input wire ext_timecode_tigger_sig, -// input wire [63:0] ext_timecode_data, -// input wire ext_genlock_signal, // - -// /******************************************************************************* -// * 内部时码信号输出 * -// *******************************************************************************/ -// output wire out_timecode_tirgger_sig, //输出时码译码有效信号 -// output wire [63:0] out_timecode_sig, // 输出时间 -// output wire out_timecode_serial_sig, - -// /******************************************************************************* -// * 内部GENLOCK信号输出 * -// *******************************************************************************/ -// output wire out_genlock_sig, -// /******************************************************************************* -// * 内部工作状态信号输出 * -// *******************************************************************************/ -// output wire out_en_flag - -// ); - -// localparam CTRL_REG_INDEX = 4; - - -// reg [31:0] r0_start_control_mode_reg; //控制模式选择寄存器 -// reg [31:0] r2_genlock_format; //genlock格式寄存器 -// reg [31:0] r3_timecode_format; //timecode格式寄存器 -// reg [31:0] r4_control_trigger_reg; // StartSigCtrl[0] TimecodeCtrl[1] GenlockCtrl[2] -// wire [31:0] r6_timecode0; //timecode0 belong to timecode_generator_ist -// wire [31:0] r7_timecode1; //timecode1 belong to timecode_generator_ist -// reg [31:0] r8_timecode_start0; // 时码启动寄存器0 -// reg [31:0] r9_timecode_start1; // 时码启动寄存器1 -// reg [31:0] rA_timecode_stop0; // 时码停止寄存器0 -// reg [31:0] rB_timecode_stop1; // 时码停止寄存器1 -// reg [31:0] rC_work_state; //工作状态 read only -// assign out_en_flag = rC_work_state[0]; - -// //写寄存器标志位 -// wire [31:0] reg_wr_index; - -// zutils_register_advanced #( -// .REG_START_ADD(REG_START_ADD) -// ) _register ( -// .clk(clk), -// .rst_n(rst_n), -// .addr(addr), -// .wr_data(wr_data), -// .wr_en(wr_en), -// .rd_data(rd_data), - -// .reg0(r0_start_control_mode_reg), -// .reg2(r2_genlock_format), -// .reg3(r3_timecode_format), -// .reg4(r4_control_trigger_reg), -// .reg6(r6_timecode0), -// .reg7(r7_timecode1), -// .reg8(r8_timecode_start0), -// .reg9(r9_timecode_start1), -// .regA(rA_timecode_stop0), -// .regB(rB_timecode_stop1), -// .regC(rC_work_state), - -// .reg_wr_sig(reg_wr_sig), -// .reg_index (reg_wr_index) -// ); - -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// r0_start_control_mode_reg <= 0; -// r2_genlock_format <= 0; -// r3_timecode_format <= 0; -// r4_control_trigger_reg <= 0; -// r8_timecode_start0 <= 0; -// r9_timecode_start1 <= 0; -// rA_timecode_stop0 <= 0; -// rB_timecode_stop1 <= 0; -// // rC_work_state <= 0; -// end else begin -// if (reg_wr_sig) begin -// case (reg_wr_index) -// 31'h0: r0_start_control_mode_reg <= wr_data; -// 31'h2: r2_genlock_format <= wr_data; -// 31'h3: r3_timecode_format <= wr_data; -// 31'h4: r4_control_trigger_reg <= wr_data; -// 31'h8: r8_timecode_start0 <= wr_data; -// 31'h9: r9_timecode_start1 <= wr_data; -// 31'hA: rA_timecode_stop0 <= wr_data; -// 31'hB: rB_timecode_stop1 <= wr_data; -// // 31'hC: rC_work_state <= wr_data; -// default: begin -// end -// endcase -// end -// end -// end -// /******************************************************************************* -// * StartSig输出 * -// *******************************************************************************/ - -// // 1.寄存器控制启动 -// // 2.外部触发启动 -// // 3.TIMECODE触发启动 -// // -// // 0.手动,启动停止 -// // 1.外部TIMECODE触发启动 -// // 2.外部TTL输入1_高电平触发,低电平停止 -// // 3.外部TTL输入2_高电平触发,低电平停止 -// // 4.外部TTL输入3_高电平触发,低电平停止 -// // 5.外部TTL输入4_高电平触发,低电平停止 -// // - - -// zutils_multiplexer_32t1_v2 ttlin_level_trigger_multi ( -// .chooseindex(r0_start_control_mode_reg), -// //in -// .in2(ext_ttlin1_module_raw_sig), -// .in3(ext_ttlin2_module_raw_sig), -// .in4(ext_ttlin3_module_raw_sig), -// .in5(ext_ttlin4_module_raw_sig), -// //out -// .out(ext_ttlinx_module_raw_sig) -// ); - -// wire timecode_start_trigger_sig; -// timecode_comparator timecode_comparator_inst ( -// .timecodeA0(ext_timecode_data[31:0]), -// .timecodeA1(ext_timecode_data[63:32]), -// .timecodeB0(r6_timecode0), -// .timecodeB1(r7_timecode1), -// .eq(timecode_start_trigger_sig) -// ); - -// reg start_sig; -// always @(posedge clk or negedge rst_n) begin -// if (!rst_n) begin -// start_sig <= 0; -// rC_work_state <= 0; -// end else begin -// case (r0_start_control_mode_reg[31:0]) -// 0: begin -// //寄存器控制启动 - -// if (reg_wr_sig && reg_wr_index == CTRL_REG_INDEX) begin -// if (wr_data[0] == 1) begin -// rC_work_state[0] <= 1; -// rC_work_state[31:1] <= 0; -// end else begin -// rC_work_state[0] <= 0; -// rC_work_state[31:1] <= 0; -// end -// end - -// end -// 1: begin -// //TIMECODE触发 -// if (ext_timecode_tigger_sig && timecode_start_trigger_sig) begin -// rC_work_state[0] <= 1; -// rC_work_state[31:1] <= 0; -// end else if (reg_wr_sig && reg_wr_index == CTRL_REG_INDEX) begin -// if (wr_data[0] == 1) begin -// rC_work_state[0] <= 1; -// rC_work_state[31:1] <= 0; -// end else begin -// rC_work_state[0] <= 0; -// rC_work_state[31:1] <= 0; -// end -// end -// end -// 2, 3, 4, 5: begin -// //外部电平控制 -// if (ext_ttlinx_module_raw_sig == 1) begin -// rC_work_state[0] <= 1; -// rC_work_state[31:1] <= 0; -// end else begin -// rC_work_state[0] <= 0; -// rC_work_state[31:1] <= 0; -// end - -// end -// default: begin -// end -// endcase -// end -// end - - -// /******************************************************************************* -// * GENLOCK_时钟输出 * -// *******************************************************************************/ - -// wire genlock_sig_output; -// zutils_genlock_clk_generator #( -// .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) -// ) genlock ( -// .clk(clk), -// .rst_n(rst_n), -// .ctrl_sig(out_en_flag), -// .genlock_fps2397_clk(genlock_fps2397_clk), -// .genlock_fps2398_clk(genlock_fps2398_clk), -// .genlock_fps2400_clk(genlock_fps2400_clk), -// .genlock_fps2500_clk(genlock_fps2500_clk), -// .genlock_fps2997_clk(genlock_fps2997_clk), -// .genlock_fps3000_clk(genlock_fps3000_clk), -// .genlock_fps5000_clk(genlock_fps5000_clk), -// .genlock_fps5994_clk(genlock_fps5994_clk), -// .genlock_fps6000_clk(genlock_fps6000_clk) -// ); - -// zutils_multiplexer_32t1_v2 genlock_clk_output_mult ( -// .chooseindex(r2_genlock_format), -// //in -// .in0(genlock_fps2397_clk), -// .in1(genlock_fps2398_clk), -// .in2(genlock_fps2400_clk), -// .in3(genlock_fps2500_clk), -// .in4(genlock_fps2997_clk), -// .in5(genlock_fps3000_clk), -// .in6(genlock_fps5000_clk), -// .in7(genlock_fps5994_clk), -// .in8(genlock_fps6000_clk), -// //out -// .out(genlock_sig_output) -// ); -// assign out_genlock_sig = genlock_sig_output; - -// /******************************************************************************* -// * smpte_timecode_clk_generator * -// *******************************************************************************/ -// assign timecode0_wen = reg_wr_sig && reg_wr_index == 6; -// assign timecode1_wen = reg_wr_sig && reg_wr_index == 7; - -// timecode_generator #( -// .SYS_CLOCK_FREQ(SYS_CLOCK_FREQ) -// ) timecode_generator_ist ( -// .clk (clk), -// .rst_n(rst_n), - -// .timecode_format(r3_timecode_format), - -// .timecode0_wen(timecode0_wen), -// .timecode0(wr_data), -// .timecode1_wen(timecode1_wen), -// .timecode1(wr_data), - -// .timecode0_export(r6_timecode0), -// .timecode1_export(r7_timecode1), - -// .en(out_en_flag), - -// .out_timecode_serial_data(out_timecode_serial_sig), -// .out_trigger_sig(out_timecode_tirgger_sig), -// .out_timecode0(out_timecode_sig[31:0]), -// .out_timecode1(out_timecode_sig[63:32]) -// ); - - -// endmodule