diff --git a/release/v1.0.5/xsyncv105.sbit b/release/v1.0.5/xsyncv105.sbit new file mode 100644 index 0000000..2857f5c Binary files /dev/null and b/release/v1.0.5/xsyncv105.sbit differ diff --git a/release/v1.0.5/xsyncv105.sfc b/release/v1.0.5/xsyncv105.sfc new file mode 100644 index 0000000..0d0fbf6 Binary files /dev/null and b/release/v1.0.5/xsyncv105.sfc differ diff --git a/source/src/app_top.v b/source/src/app_top.v index 509593e..b83458f 100644 --- a/source/src/app_top.v +++ b/source/src/app_top.v @@ -45,7 +45,15 @@ module AppTop ( output wire timecode_is_detected, output wire debug_ext_timecode_tigger_sig, output wire debug_ch1_timecode_tigger_sig, - output wire debug_ch2_timecode_tigger_sig + output wire debug_ch2_timecode_tigger_sig, + + output wire debug_tcin_ch1_sample_sig, + output wire debug_tcin_ch1_in_sig_edge, + output wire debug_tcin_ch2_sample_sig, + output wire debug_tcin_ch2_in_sig_edge, + + output wire endsig + ); @@ -122,7 +130,7 @@ module AppTop ( wire [31:0] sig_src; // 系统内部信号总线 - assign debug_ext_timecode_tigger_sig = ext_timecode_tigger_sig; + assign debug_ext_timecode_tigger_sig = ext_timecode_tigger_sig; assign sig_src[`SIGNAL_LOGIC0] = signal_logic0; @@ -400,7 +408,12 @@ module AppTop ( .timecode_is_detected(timecode_is_detected), .debug_ch1_timecode_tigger_sig(debug_ch1_timecode_tigger_sig), - .debug_ch2_timecode_tigger_sig(debug_ch2_timecode_tigger_sig) + .debug_ch2_timecode_tigger_sig(debug_ch2_timecode_tigger_sig), + + .debug_ch1_sample_sig (debug_tcin_ch1_sample_sig), + .debug_ch1_in_sig_edge(debug_tcin_ch1_in_sig_edge), + .debug_ch2_sample_sig (debug_tcin_ch2_sample_sig), + .debug_ch2_in_sig_edge(debug_tcin_ch2_in_sig_edge) ); timecode_output #( diff --git a/source/src/input/timecode_input.v b/source/src/input/timecode_input.v index 598ee91..8831dbb 100644 --- a/source/src/input/timecode_input.v +++ b/source/src/input/timecode_input.v @@ -33,7 +33,17 @@ module timecode_input #( //调试信号 output wire debug_ch1_timecode_tigger_sig, - output wire debug_ch2_timecode_tigger_sig + output wire debug_ch1_sample_sig, + output wire debug_ch1_in_sig_edge, + + + output wire debug_ch2_timecode_tigger_sig, + output wire debug_ch2_sample_sig, + output wire debug_ch2_in_sig_edge, + + + + output wire endsig //没有作用，主要是为了让添加新的信号线时，无须在关心逗号问题 ); @@ -113,10 +123,12 @@ module timecode_input #( ) timecode_decoder_1 ( .clk (clk), .rst_n (rst_n), - .timecode_in (timecode_bnc_in_after), // 时码输入 - .timecode_tigger_sig (ch1_timecode_tigger_sig), // - .timecode_data (ch1_timecode_data), //[63:0] - .timecode_serial_data(ch1_timecode_serial_data) // + .timecode_in (timecode_bnc_in_after), // 时码输入 + .timecode_tigger_sig (ch1_timecode_tigger_sig), // + .timecode_data (ch1_timecode_data), //[63:0] + .timecode_serial_data(ch1_timecode_serial_data), // + .debug_sample_sig (debug_ch1_sample_sig), + .debug_in_sig_edge (debug_ch1_in_sig_edge) ); @@ -125,10 +137,12 @@ module timecode_input #( ) timecode_decoder_2 ( .clk (clk), .rst_n (rst_n), - .timecode_in (timecode_headphone_in), // 时码输入 - .timecode_tigger_sig (ch2_timecode_tigger_sig), // - .timecode_data (ch2_timecode_data), //[63:0] - .timecode_serial_data(ch2_timecode_serial_data) // + .timecode_in (timecode_headphone_in), // 时码输入 + .timecode_tigger_sig (ch2_timecode_tigger_sig), // + .timecode_data (ch2_timecode_data), //[63:0] + .timecode_serial_data(ch2_timecode_serial_data), // + .debug_sample_sig (debug_ch2_sample_sig), + .debug_in_sig_edge (debug_ch2_in_sig_edge) ); diff --git a/source/src/internal/internal_sig_generator_en_contrler.v b/source/src/internal/internal_sig_generator_en_contrler.v index 9797093..c26499e 100644 --- a/source/src/internal/internal_sig_generator_en_contrler.v +++ b/source/src/internal/internal_sig_generator_en_contrler.v @@ -37,8 +37,8 @@ module internal_sig_generator_en_contrler #( always @(posedge clk or negedge rst_n) begin if (!rst_n) begin - // r1_en <= 32'hFFFF_FFFF; - r1_en <= 32'h0; + r1_en <= 32'hFFFF_FFFF; + // r1_en <= 32'h0; end else begin if (reg_wr_sig) begin case (reg_wr_index) diff --git a/source/src/internal/internal_timecode_generator.v b/source/src/internal/internal_timecode_generator.v index f3e07c5..957099b 100644 --- a/source/src/internal/internal_timecode_generator.v +++ b/source/src/internal/internal_timecode_generator.v @@ -54,7 +54,7 @@ module internal_timecode_generator #( always @(posedge clk or negedge rst_n) begin if (!rst_n) begin reg1_timecode_en <= 1; - reg2_timecode_format <= 0; + reg2_timecode_format <= 5; end else begin if (reg_wr_sig) begin case (reg_wr_index) diff --git a/source/src/timecode/timecode_decoder.v b/source/src/timecode/timecode_decoder.v index 60d815e..cfc9188 100644 --- a/source/src/timecode/timecode_decoder.v +++ b/source/src/timecode/timecode_decoder.v @@ -14,7 +14,10 @@ module timecode_decoder #( output reg timecode_tigger_sig, output reg [63:0] timecode_data, // output [31:0] timecode_format, - output timecode_serial_data + output timecode_serial_data, + + output wire debug_sample_sig, + output wire debug_in_sig_edge ); // Rate us 1/2Fe 1Fe 1/2CNT 1CNT @@ -45,6 +48,8 @@ module timecode_decoder #( assign timecode_serial_data = timecode_in_af_filter; assign timecode_in_state = timecode_in_af_filter; + + wire timecode_sample_sig_generator_rest_sig; wire timecode_in_edge; assign timecode_sample_sig_generator_rest_sig = !timecode_in_edge & rst_n; @@ -68,6 +73,9 @@ module timecode_decoder #( .sample_sig(sample_sig) ); + assign debug_sample_sig = sample_sig; + assign debug_in_sig_edge = timecode_in_edge; + // 采样+缓存采样数据 reg [159:0] timecode_data_cache; diff --git a/source/src/top.v b/source/src/top.v index d8db7cf..b60eaa3 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -148,18 +148,24 @@ module Top ( .timecode_is_detected (timecode_is_detected), .debug_ext_timecode_tigger_sig(debug_ext_timecode_tigger_sig), .debug_ch1_timecode_tigger_sig(debug_ch1_timecode_tigger_sig), - .debug_ch2_timecode_tigger_sig(debug_ch2_timecode_tigger_sig) + .debug_ch2_timecode_tigger_sig(debug_ch2_timecode_tigger_sig), + .debug_tcin_ch1_sample_sig (debug_tcin_ch1_sample_sig), + .debug_tcin_ch1_in_sig_edge (debug_tcin_ch1_in_sig_edge), + .debug_tcin_ch2_sample_sig (debug_tcin_ch2_sample_sig), + .debug_tcin_ch2_in_sig_edge (debug_tcin_ch2_in_sig_edge), + + .endsig(endsig) ); zutils_pluse_generator _pluse_generator ( - .clk (sys_clk), - .rst_n (sys_rst_n), - .pluse_width (32'd100), - .pluse_delay (32'd0), - .trigger (debug_ext_timecode_tigger_sig), - .output_signal(debug_ext_timecode_tigger_sig_pluse) -); + .clk (sys_clk), + .rst_n (sys_rst_n), + .pluse_width (32'd100), + .pluse_delay (32'd0), + .trigger (debug_ext_timecode_tigger_sig), + .output_signal(debug_ext_timecode_tigger_sig_pluse) + ); @@ -174,10 +180,11 @@ module Top ( assign debug_signal_output[8] = stm32if_start_signal_out; assign debug_signal_output[9] = stm32if_camera_sync_out; assign debug_signal_output[10] = stm32if_timecode_sync_out; - assign debug_signal_output[11] = 0; - assign debug_signal_output[12] = 0; - assign debug_signal_output[13] = 0; - assign debug_signal_output[14] = timecode_is_detected; + + assign debug_signal_output[11] = debug_tcin_ch1_sample_sig; + assign debug_signal_output[12] = debug_tcin_ch1_in_sig_edge; + assign debug_signal_output[13] = debug_tcin_ch2_sample_sig; + assign debug_signal_output[14] = debug_tcin_ch2_in_sig_edge; assign debug_signal_output[15] = debug_ext_timecode_tigger_sig_pluse; // assign debug_signal_output[5] = sync_ttl_out1; // assign debug_signal_output[6] = sync_ttl_out2; diff --git a/xsync.pds b/xsync.pds index f0d8842..73045b7 100644 --- a/xsync.pds +++ b/xsync.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2022.2-SP4.2" - (_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2) at Sat Nov 2 19:25:01 2024") + (_comment "Generated by Fabric Compiler (version on 2022.2-SP4.2) at Sun Nov 3 14:19:41 2024") (_version "1.1.0") (_status "initial") (_project @@ -21,7 +21,7 @@ (_input (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-11-02T18:50:41") + (_timespec "2024-11-03T14:04:29") ) (_file "source/src/spi_reg_reader.v" (_format verilog) @@ -129,11 +129,11 @@ ) (_file "source/src/input/timecode_input.v" (_format verilog) - (_timespec "2024-11-02T17:59:02") + (_timespec "2024-11-03T14:01:00") ) (_file "source/src/timecode/timecode_decoder.v" (_format verilog) - (_timespec "2024-08-28T21:53:27") + (_timespec "2024-11-03T13:58:51") ) (_file "source/src/timecode/timecode_sample_sig_generator.v" (_format verilog) @@ -177,7 +177,7 @@ ) (_file "source/src/internal/internal_timecode_generator.v" (_format verilog) - (_timespec "2024-08-23T13:36:15") + (_timespec "2024-11-03T13:12:31") ) (_file "source/src/sys/sys_timecode.v" (_format verilog) @@ -229,7 +229,7 @@ ) (_file "source/src/internal/internal_sig_generator_en_contrler.v" (_format verilog) - (_timespec "2024-11-02T19:11:23") + (_timespec "2024-11-03T12:54:48") ) (_file "source/src/zutils/zutils_timer.v" (_format verilog) @@ -241,7 +241,7 @@ ) (_file "source/src/app_top.v" (_format verilog) - (_timespec "2024-11-02T18:02:58") + (_timespec "2024-11-03T14:03:01") ) (_file "source/src/timecode/timecode_freq_detector.v" (_format verilog) @@ -334,17 +334,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-11-02T19:11:49") + (_timespec "2024-11-03T14:04:52") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-11-02T19:11:49") + (_timespec "2024-11-03T14:04:52") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-11-02T19:11:49") + (_timespec "2024-11-03T14:04:52") ) ) ) @@ -359,25 +359,25 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-11-02T19:14:32") + (_timespec "2024-11-03T14:07:59") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-11-02T19:14:46") + (_timespec "2024-11-03T14:08:14") ) (_file "synthesize/Top_controlsets.txt" (_format text) - (_timespec "2024-11-02T19:14:18") + (_timespec "2024-11-03T14:07:44") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-11-02T19:14:53") + (_timespec "2024-11-03T14:08:21") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-11-02T19:14:53") + (_timespec "2024-11-03T14:08:21") ) ) ) @@ -398,21 +398,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-11-02T19:15:44") + (_timespec "2024-11-03T14:09:25") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-11-02T19:15:20") + (_timespec "2024-11-03T14:08:59") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-11-02T19:15:45") + (_timespec "2024-11-03T14:09:25") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-11-02T19:15:45") + (_timespec "2024-11-03T14:09:25") ) ) ) @@ -421,7 +421,7 @@ (_input (_file "device_map/xsync.pcf" (_format pcf) - (_timespec "2024-11-02T19:15:44") + (_timespec "2024-11-03T14:09:25") ) ) ) @@ -442,33 +442,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-11-02T19:23:16") + (_timespec "2024-11-03T14:17:48") ) ) (_output (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-11-02T19:22:34") + (_timespec "2024-11-03T14:16:59") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-11-02T19:19:17") + (_timespec "2024-11-03T14:13:13") ) (_file "place_route/Top.prr" (_format text) - (_timespec "2024-11-02T19:23:18") + (_timespec "2024-11-03T14:17:49") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-11-02T19:22:34") + (_timespec "2024-11-03T14:16:58") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-11-02T19:23:17") + (_timespec "2024-11-03T14:17:48") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-11-02T19:23:18") + (_timespec "2024-11-03T14:17:49") ) ) ) @@ -504,19 +504,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-11-02T19:24:56") + (_timespec "2024-11-03T14:19:36") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-11-02T19:24:57") + (_timespec "2024-11-03T14:19:37") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-11-02T19:25:01") + (_timespec "2024-11-03T14:19:41") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-11-02T19:25:00") + (_timespec "2024-11-03T14:19:41") ) ) ) diff --git a/xsync.pds.lock b/xsync.pds.lock index a0a334b..63b74f7 100644 --- a/xsync.pds.lock +++ b/xsync.pds.lock @@ -1,4 +1,4 @@ -17704 +14124 pds ZHAOHE f8caf121-d1d2-4c26-8a45-7e1d59cde8b6