diff --git a/README.md b/README.md index 60531db..719b432 100644 --- a/README.md +++ b/README.md @@ -14,4 +14,12 @@ define_attribute {p:sys_clk} {PAP_IO_STANDARD} {LVTTL33} +``` + +``` +SPI2_CS 48 R2_13_N V14 +SPI2_MOSI 50 R2_13_P U14 +SPI2_SCK 54 R2_2_N V13 +SPI2_MISO 56 R2_2_P U13 + ``` \ No newline at end of file diff --git a/ipcore/DebugCoreIst/.last_generated b/ipcore/DebugCoreIst/.last_generated index 189c154..b09bf16 100644 --- a/ipcore/DebugCoreIst/.last_generated +++ b/ipcore/DebugCoreIst/.last_generated @@ -1,2 +1,2 @@ -2024-01-06 22:31 +2024-01-07 14:18 rev_1 \ No newline at end of file diff --git a/ipcore/DebugCoreIst/DebugCoreIst.idf b/ipcore/DebugCoreIst/DebugCoreIst.idf index 7b5d55e..f370c1b 100644 --- a/ipcore/DebugCoreIst/DebugCoreIst.idf +++ b/ipcore/DebugCoreIst/DebugCoreIst.idf @@ -15,807 +15,807 @@ - TU8_CNT_MODE - 00 + c_Port1_EN + false - EN_WINDOWS + TRIG_MU_EN4 false - V14_RADIX - Bin + TRIG1_EXCLUDE + false - TRIG8_MATCH_UNIT - 1 + STOR_MU_EN11 + false - TRIG9_EXCLUDE + TRIG_MU_NEG11 false - VALUE9_1 - 0 + TRIG10_MATCH_UNIT + 1 - TRIG_MU_NEG8 + TRIG_MU_EN11 false - V7_2RADIX - Bin - - - VALUE2 - 0 + TU14_CNT_VALUE + 1 - INIT_M11_CONFIG - 0 + TU13_FUNCTION + 000 - V9_1RADIX - Bin + TRIG12_PORT_WIDTH + 8 - TRIG_MU_EN12 - false + INIT_M14_CONFIG + 0 - TRIG9_CNT_WIDTH + VALUE6 0 - TU4_CNT_MODE + TU14_CNT_MODE 00 - STOR_MU_EN11 + TRIG_MU_NEG15 false - VALUE6 - 0 + TRIG12_EXCLUDE + false - INIT_M13_CONFIG - 0 + TU11_FUNCTION + 000 - TRIG10_PORT_WIDTH - 8 + TRIG6_MATCH_UNIT + 1 - TRIG_MU_EN13 + STOR_MU_EN5 false - V12_RADIX - Bin - - - TRIG_SEQ_SEL11 - 0 + TU15_CNT_MODE + 00 - VALUE3_1 - 0 + STOR_MU_EN15 + false - TU14_FUNCTION - 000 + V13_RADIX + Bin - TRIG5_MATCH_UNIT + TRIG8_MATCH_UNIT 1 - c_Port7_EN - false + V8_RADIX + Bin - V1_1RADIX - Bin + DATA_DEPTH + 14 - STOR_MU_EN1 + STOR_MU_EN2 false - TU1_FUNCTION + TU14_FUNCTION 000 - V8_RADIX - Bin + INIT_M7_CONFIG + 0 - TRIG_SEQ_NEG15 - false + VALUE8_1 + 0 - VALUE13 + VALUE0_1 0 - VALUE13_1 + INIT_M3_CONFIG 0 - TU10_CNT_MODE - 00 + TRIG6_PORT_WIDTH + 8 - TRIG9_MATCH_TYPE - 1 + V0_RADIX + Bin - TU2_CNT_VALUE + TRIG_MU_NEG9 + false + + + TU11_CNT_VALUE 1 - V13_2RADIX - Bin + TRIG9_MATCH_UNIT + 1 - INIT_M7_CONFIG + VALUE8 0 - INIT_M0_CONFIG - 25'b0010010010010010010010010 + TRIG5_EXCLUDE + false - INIT_M3_CONFIG - 0 + TRIG_MU_NEG13 + false - TRIG13_EXCLUDE + TRIG_SEQ_NEG11 false - VALUE2_2 - 0 + TRIG3_MATCH_TYPE + 1 - TRIG_SEQ_NEG5 - false + TRIG12_CNT_WIDTH + 0 - STOR_MU_EN6 - false + VALUE1 + 0 - STOR_MU_NEG0 + TRIG_SEQ_NEG4 false - TU0_CNT_VALUE - 1 + VALUE13 + 0 - TU8_FUNCTION - 000 + TU7_CNT_VALUE + 1 - TRIG_SEQ_NEG8 - false + TU12_CNT_VALUE + 1 - V6_1RADIX + V10_RADIX Bin - VALUE12_1 - 0 + TU15_FUNCTION + 000 - V3_1RADIX - Bin + TRIG_SEQ_SEL0 + 0 - EN_STOR_QUAL + STOR_MU_NEG1 false - STORE_POSITION - 0 + TU4_CNT_VALUE + 1 - TRIG_MU_EN4 + STOR_MU_EN13 false - V15_RADIX - Bin + TRIG_MU_EN7 + false - STOR_MU_NEG13 - false + TRIG2_PORT_WIDTH + 8 - DATA_DEPTH - 14 + STOR_MU_EN8 + false - TRIG_SEQ_NEG12 + TRIG_MU_EN8 false - VALUE14 - 0 + c_Port12_EN + false - V4_RADIX + V8_2RADIX Bin - TRIG_MODE + VALUE11_1 0 - TRIG_MU_EN0 + STOR_MU_EN1 false - VALUE11_2 - 0 + INIT_TRIG_OUT + 3'b000 - TRIG2_MATCH_TYPE + TRIG7_MATCH_TYPE 1 - VALUE5_1 - 0 + ALL_DATA + 1 - INIT_M1_CONFIG - 25'b0010010010010010010010010 + TRIG7_MATCH_UNIT + 1 - TRIG_SEQ_NEG6 - false + V0_1RADIX + Bin - STOR_MU_NEG4 - false + TU1_CNT_MODE + 00 - INIT_M9_CONFIG - 0 + c_Port14_EN + false - STOR_MU_NEG9 + TRIG_MU_EN14 false - TRIG6_PORT_WIDTH - 8 + STOR_MU_NEG15 + false - V3_2RADIX - Bin + TRIG_SEQ_SEL5 + 0 - VALUE7_2 - 0 + STOR_MU_NEG6 + false - TRIG11_EXCLUDE + TRIG_MU_NEG0 false - STOR_MU_NEG10 + TRIG9_EXCLUDE false - V3_RADIX - Bin + TRIG3_EXCLUDE + false - TRIG4_MATCH_UNIT - 1 + TRIG0_EXCLUDE + false - V6_2RADIX + V9_2RADIX Bin - STORE_TYPE - 0 - - - TRIG10_EXCLUDE + INIT_ENABLE false - VALUE9 + TRIG0_CNT_WIDTH 0 - STOR_MU_EN13 + STOR_MU_NEG11 false - TRIG8_PORT_WIDTH + TRIG13_PORT_WIDTH 8 - TU15_CNT_MODE - 00 + TU9_CNT_VALUE + 1 - STOR_MU_NEG2 + TRIG_SEQ_NEG9 false - INIT_M2_CONFIG - 0 - - - TU13_CNT_VALUE - 1 + STOR_MU_EN6 + false - V9_RADIX - Bin + TRIG4_EXCLUDE + false - TRIG6_MATCH_TYPE - 1 + INIT_M8_CONFIG + 0 - TU5_FUNCTION - 000 + TRIG_SEQ_SEL6 + 0 - INIT_M10_CONFIG + VALUE11_2 0 - V13_RADIX - Bin + STOR_MU_NEG14 + false - VALUE15_1 - 0 + TU8_CNT_VALUE + 1 - STOR_MU_EN7 + TRIG_CONTIGUOUS false - V8_2RADIX + V15_1RADIX Bin - TRIG_MU_EN7 - false + TRIG5_MATCH_UNIT + 1 - TRIG_MU_NEG12 - false + TU8_FUNCTION + 000 - TRIG14_EXCLUDE - false + VALUE10_2 + 0 - STOR_MU_EN8 - false + VALUE6_1 + 0 - VALUE10 - 0 + V12_1RADIX + Bin - TRIG_SEQ_LEVEL - 1 + TU8_CNT_MODE + 00 - TRIG1_MATCH_UNIT - 1 + c_Port5_EN + false - INIT_STOR_QUAL - 5'b0 + TRIG7_PORT_WIDTH + 8 - c_Port2_EN - false + TU12_FUNCTION + 000 - VALUE14_1 + INIT_M10_CONFIG 0 - TRIG2_MATCH_UNIT - 1 + TU11_CNT_MODE + 00 - V2_2RADIX + V1_2RADIX Bin - TRIG_SEQ_SEL0 - 0 + STOR_MU_NEG12 + false - TRIG8_MATCH_TYPE - 1 + V13_1RADIX + Bin - INIT_M4_CONFIG + STORE_POSITION 0 - TRIG3_EXCLUDE - false + VALUE4 + 0 - TU1_CNT_MODE - 00 + VALUE3_1 + 0 - V15_1RADIX - Bin + TRIG8_MATCH_TYPE + 1 - TRIG_MU_NEG15 - false + TRIG_SEQ_SEL9 + 0 - TRIG4_MATCH_TYPE - 1 + INIT_M15_CONFIG + 0 - TRIG_SEQ_NEG0 - false + TRIG14_MATCH_TYPE + 1 - VALUE4 + TRIG_SEQ_SEL12 0 - V12_1RADIX - Bin + TRIG_MU_NEG10 + false - STOR_MU_EN2 + STOR_MU_NEG13 false - TRIG_MU_NEG11 + EN_TRIG_OUT false - TRIG12_CNT_WIDTH + TRIG_SEQ_SEL1 0 - TRIG_MU_NEG9 + TU2_CNT_VALUE + 1 + + + c_Port13_EN false - TRIG_SEQ_SEL14 - 0 + TRIG_MU_NEG12 + false - STOR_MU_NEG7 + TRIG_SEQ_NEG1 false - VALUE1 + VALUE12_1 0 - V7_RADIX - Bin + c_Port11_EN + false - TU3_CNT_VALUE - 1 + EN_STOR_QUAL + false - V10_1RADIX - Bin + VALUE13_2 + 0 - STOR_MU_EN4 - false + TU1_FUNCTION + 000 - TRIG_SEQ_SEL12 + VALUE5_1 0 - TRIG_MU_NEG2 + STOR_MU_EN3 false - TRIG8_CNT_WIDTH - 0 + TU15_CNT_VALUE + 1 - VALUE8_2 + VALUE3_2 0 - TRIG_CONTIGUOUS + TRIG_SEQ_NEG8 false - TU0_FUNCTION - 000 + TRIG12_MATCH_TYPE + 1 TRIG14_MATCH_UNIT 1 - TRIG8_EXCLUDE + STOR_MU_NEG5 false - c_Port9_EN + TRIG2_EXCLUDE false - VALUE7_1 + TRIG5_CNT_WIDTH 0 - V1_2RADIX + TRIG2_CNT_WIDTH + 0 + + + V11_2RADIX Bin - c_Port14_EN - false + V4_RADIX + Bin - MAX_SEQ_LEVEL - 1 + TRIG_SEQ_SEL8 + 0 - TU7_FUNCTION - 000 + c_Port6_EN + false - TRIG_MU_EN3 + TRIG_SEQ_NEG0 false - V4_1RADIX + V11_RADIX Bin - VALUE4_1 - 0 + TRIG_SEQ_NEG15 + false - VALUE3_2 - 0 + TU0_CNT_MODE + 00 - TRIG_SEQ_SEL1 - 0 + c_Port0_EN + true - VALUE6_1 - 0 + V8_1RADIX + Bin - VALUE8 - 0 + TRIG_SEQ_NEG10 + false - TRIG1_MATCH_TYPE + V9_1RADIX + Bin + + + TU5_CNT_MODE + 00 + + + DATA_WIDTH 1 - TRIG_MU_NEG5 + TRIG_MU_NEG2 false - c_Port8_EN + TRIG10_CNT_WIDTH + 0 + + + TRIG_MU_EN5 false - TRIG14_CNT_WIDTH + TRIG8_PORT_WIDTH + 8 + + + VALUE10 0 - TU11_FUNCTION + TRIG6_MATCH_TYPE + 1 + + + TU6_FUNCTION 000 - TRIG_MU_EN15 - false + V15_2RADIX + Bin - VALUE12_2 - 0 + TRIG1_PORT_WIDTH + 8 - TU3_FUNCTION - 000 + TU13_CNT_MODE + 00 - TRIG_MU_EN11 - false + TU3_CNT_MODE + 00 - VALUE0_2 - 0 + TU0_FUNCTION + 000 - TRIG13_CNT_WIDTH + TRIG_SEQ_SEL3 0 - STOR_MU_NEG12 - false + TU3_CNT_VALUE + 1 - STOR_MU_EN5 - false + TU7_FUNCTION + 000 - VALUE3 - 0 + V4_1RADIX + Bin - TRIG12_EXCLUDE - false + INIT_M13_CONFIG + 0 - TRIG3_CNT_WIDTH + TRIG9_CNT_WIDTH 0 - TRIG0_EXCLUDE + TRIG_MU_EN3 false - VALUE0 + STORE_TYPE 0 - TU14_CNT_MODE - 00 + TU2_FUNCTION + 000 - TRIG_MU_NEG13 + TRIG_MU_EN9 false - TRIG_SEQ_SEL10 + VALUE9_2 0 - INIT_TRIG_COND - 6'b000000 - - - TU0_CNT_MODE - 00 + INIT_M5_CONFIG + 0 - TU8_CNT_VALUE + TU10_CNT_VALUE 1 - TRIG14_MATCH_TYPE - 1 + TRIG8_EXCLUDE + false - TRIG7_MATCH_TYPE + TRIG10_MATCH_TYPE 1 - TRIG12_MATCH_TYPE - 1 + VALUE7 + 0 - V0_1RADIX - Bin + TRIG0_MATCH_TYPE + 1 - VALUE0_1 + VALUE13_1 0 - V7_1RADIX + V10_1RADIX Bin - STOR_MU_NEG1 - false - - - TRIG_SEQ_SEL2 + VALUE4_1 0 - STOR_MU_EN10 - false + TU5_CNT_VALUE + 1 - TRIG_SEQ_NEG7 - false + INIT_M6_CONFIG + 0 - V2_RADIX + V13_2RADIX Bin - c_Port4_EN - false - - - TRIG_SEQ_NEG1 - false + INIT_M0_CONFIG + 22'b0010010010010010010010 - TU4_FUNCTION - 000 + INIT_STOR_TYPE + 19'b0000000000000000000 - TRIG_MU_EN6 + TRIG11_EXCLUDE false - c_Port1_EN - true - - - TU6_CNT_MODE - 00 + VALUE15_1 + 0 - TRIG9_MATCH_UNIT + TRIG9_MATCH_TYPE 1 - V0_2RADIX + V2_RADIX Bin - EN_TRIG_OUT + STOR_MU_NEG10 false - TRIG1_EXCLUDE + TRIG13_EXCLUDE false - DATA_SAME_AS_TRIG - true + TRIG3_PORT_WIDTH + 8 - VALUE5 - 0 + STOR_MU_NEG4 + false - INIT_TRIG_OUT - 3'b000 + TRIG_MU_NEG7 + false - c_Port11_EN + STOR_MU_EN4 false - TRIG3_PORT_WIDTH - 8 + TRIG_SEQ_SEL14 + 0 - V15_2RADIX + V0_2RADIX Bin - STOR_NEG_WHOLE + TRIG_SEQ_NEG3 false @@ -823,391 +823,375 @@ Bin - TU12_CNT_VALUE - 1 + V1_RADIX + Bin - TRIG0_CNT_WIDTH + VALUE12_2 0 - TU6_FUNCTION - 000 - - - CLK_EDGE - 1 - - - TU15_CNT_VALUE - 1 - - - TRIG7_MATCH_UNIT - 1 - - - TRIG_MU_EN10 - false + V5_1RADIX + Bin - TRIG13_PORT_WIDTH - 8 + V3_1RADIX + Bin - TRIG_SEQ_NEG4 + TRIG_MU_EN13 false - TRIG_MU_NEG3 - false + TRIG14_CNT_WIDTH + 0 - TRIG10_MATCH_UNIT + TU1_CNT_VALUE 1 - TRIG5_EXCLUDE + TRIG_MU_EN1 false - V11_RADIX - Bin - - - INIT_M14_CONFIG - 0 + TU10_FUNCTION + 000 - TU2_CNT_MODE + TU12_CNT_MODE 00 - STOR_MU_NEG11 - false + V6_1RADIX + Bin - VALUE15_2 - 0 + TRIG2_MATCH_UNIT + 1 - VALUE4_2 + TRIG6_CNT_WIDTH 0 - TRIG7_EXCLUDE - false - - - TRIG15_MATCH_UNIT + TRIG11_MATCH_UNIT 1 - c_Port5_EN - false + TRIG_SEQ_SEL15 + 0 - TRIG_NEG_WHOLE + TRIG_MU_EN12 false - TRIG_MU_NEG1 - false + TU9_FUNCTION + 000 - TRIG11_CNT_WIDTH - 0 + V2_1RADIX + Bin - V14_1RADIX + V5_RADIX Bin - TRIG_MU_EN8 - false + TRIG15_MATCH_TYPE + 1 - TRIG_SEQ_SEL9 - 0 + TRIG11_MATCH_TYPE + 1 - STOR_MU_NEG3 + TRIG_MU_EN15 false - TRIG12_PORT_WIDTH - 8 - - - VALUE11 - 0 + c_Port15_EN + false - TU6_CNT_VALUE + TRIG_PORT_NUM 1 - V11_1RADIX + V3_2RADIX Bin - STOR_MU_NEG14 - false - - - TRIG_MU_NEG0 + TRIG6_EXCLUDE false - V1_RADIX + V14_1RADIX Bin - VALUE11_1 - 0 + INIT_STOR_QUAL + 2'b0 - TRIG_MU_EN1 + STOR_MU_EN9 false - VALUE9_2 + TU5_FUNCTION + 000 + + + TRIG1_CNT_WIDTH 0 - c_Port3_EN + VALUE12 + 0 + + + c_Port2_EN false - V4_2RADIX - Bin + TRIG15_CNT_WIDTH + 0 - TRIG15_PORT_WIDTH - 8 + V12_RADIX + Bin - TRIG2_PORT_WIDTH + TRIG9_PORT_WIDTH 8 - TRIG10_CNT_WIDTH - 0 + STORE_TYPE_DIV + 1 - STOR_MU_EN12 - false + TU9_CNT_MODE + 00 - TRIG_MU_NEG14 - false + V7_1RADIX + Bin - TRIG_SEQ_SEL3 + VALUE2 0 - STOR_MU_EN0 - false + V6_2RADIX + Bin - STOR_MU_EN3 + TRIG_MU_NEG3 false - TU2_FUNCTION - 000 + TRIG12_MATCH_UNIT + 1 - TRIG0_MATCH_TYPE - 1 + TRIG4_PORT_WIDTH + 8 - DATA_WIDTH - 1 + VALUE3 + 0 - INIT_ENABLE - false + VALUE9 + 0 - VALUE10_2 + V9_RADIX + Bin + + + INIT_M4_CONFIG 0 - INIT_M5_CONFIG + TRIG_SEQ_SEL13 0 - TU9_CNT_MODE + TRIG10_EXCLUDE + false + + + TU6_CNT_MODE 00 - TRIG_SEQ_SEL5 + VALUE2_2 0 - TU9_CNT_VALUE - 1 + TRIG_SEQ_SEL11 + 0 - TU7_CNT_MODE - 00 + TRIG_MU_NEG5 + false - TU4_CNT_VALUE + TRIG3_MATCH_UNIT 1 - TRIG5_PORT_WIDTH - 8 + STOR_MU_EN7 + false - c_Port0_EN - true + V1_1RADIX + Bin - c_Port12_EN + TRIG_SEQ_NEG2 false - TRIG_SEQ_SEL13 + TRIG3_CNT_WIDTH 0 - TRIG_SEQ_SEL15 - 0 + c_Port10_EN + false - c_Port13_EN - false + TU6_CNT_VALUE + 1 - STOR_MU_EN15 + TRIG_MU_EN10 false - VALUE14_2 + VALUE4_2 0 - STOR_MU_EN14 - false + MAX_SEQ_LEVEL + 1 - VALUE12 + VALUE14_1 0 - V10_2RADIX - Bin + TRIG_MU_NEG14 + false - VALUE1_2 + VALUE14 0 - TRIG0_MATCH_UNIT - 1 + VALUE2_1 + 0 - c_Port6_EN - false + VALUE14_2 + 0 - TRIG5_MATCH_TYPE - 1 + AREA_SPEED + 0 - TRIG13_MATCH_UNIT - 1 + TRIG_MU_EN2 + false - c_Port10_EN + TRIG_MU_NEG1 false - STORE_TYPE_DIV - 1 + DATA_SAME_AS_TRIG + true - TU11_CNT_VALUE + TRIG1_MATCH_TYPE 1 - VALUE2_1 - 0 + STOR_MU_EN0 + false - TRIG_MU_NEG4 + TRIG_NEG_WHOLE false - TRIG2_CNT_WIDTH - 0 + STOR_MU_EN12 + false - TRIG15_MATCH_TYPE - 1 + TU7_CNT_MODE + 00 - TU1_CNT_VALUE + TRIG13_MATCH_TYPE 1 - TU10_CNT_VALUE - 1 + V15_RADIX + Bin - STOR_MU_NEG15 - false + VALUE1_1 + 0 - TRIG0_PORT_WIDTH - 8 + STOR_MU_NEG2 + false - TRIG_SEQ_SEL4 - 0 + TRIG_SEQ_NEG7 + false - VALUE10_1 + TRIG_SEQ_SEL4 0 - AREA_SPEED - 0 + STOR_MU_EN10 + false - TRIG1_PORT_WIDTH - 8 + TRIG_MU_EN6 + false - VALUE7 + VALUE7_1 0 - V13_1RADIX + V10_2RADIX Bin - c_Port15_EN + TRIG_SEQ_NEG13 false - TRIG11_MATCH_UNIT - 1 + c_Port4_EN + false - TRIG6_CNT_WIDTH + TRIG7_CNT_WIDTH 0 - INIT_M12_CONFIG - 0 + TU4_CNT_MODE + 00 - TRIG7_CNT_WIDTH + TRIG_SEQ_SEL7 0 @@ -1215,35 +1199,55 @@ 8 - TRIG11_MATCH_TYPE - 1 + STOR_MU_EN14 + false + + + TRIG_MU_NEG8 + false + + + INIT_M11_CONFIG + 0 + + + TU10_CNT_MODE + 00 - TRIG2_EXCLUDE - false + VALUE0 + 0 - INIT_M8_CONFIG + TRIG_SEQ_SEL10 0 - TRIG_MU_EN9 - false + INIT_M9_CONFIG + 0 - TRIG15_CNT_WIDTH + TRIG13_CNT_WIDTH 0 - STOR_MU_NEG5 + TRIG5_MATCH_TYPE + 1 + + + c_Port9_EN false - V9_2RADIX + V2_2RADIX Bin - VALUE6_2 + TRIG_SEQ_NEG14 + false + + + VALUE15_2 0 @@ -1251,271 +1255,267 @@ Bin - V5_RADIX - Bin + c_Port7_EN + false - TRIG7_PORT_WIDTH - 8 + TRIG4_MATCH_UNIT + 1 - TRIG_SEQ_SEL7 + TRIG4_CNT_WIDTH 0 - TRIG6_EXCLUDE - false + TU0_CNT_VALUE + 1 - STOR_MU_NEG6 + EN_WINDOWS false - VALUE15 + VALUE5 0 - TU5_CNT_MODE - 00 - - - TRIG_SEQ_NEG14 - false + VALUE6_2 + 0 - TU10_FUNCTION - 000 + VALUE10_1 + 0 - TRIG4_EXCLUDE - false + V3_RADIX + Bin - TU9_FUNCTION + TU3_FUNCTION 000 - TRIG_MU_NEG6 - false - - - TRIG_SEQ_NEG10 - false + TRIG11_PORT_WIDTH + 8 - TRIG_MU_NEG7 + TRIG14_EXCLUDE false - TU13_FUNCTION - 000 + INIT_M12_CONFIG + 0 - TRIG13_MATCH_TYPE - 1 + VALUE7_2 + 0 - VALUE1_1 + VALUE15 0 - V0_RADIX - Bin + INIT_M1_CONFIG + 0 - INIT_M6_CONFIG - 0 + INIT_TRIG_COND + 3'b000 - STOR_MU_EN9 + STOR_MU_NEG8 false - TU7_CNT_VALUE - 1 + INIT_M2_CONFIG + 0 - VALUE5_2 - 0 + TRIG2_MATCH_TYPE + 1 - TRIG_SEQ_SEL8 - 0 + TRIG15_PORT_WIDTH + 8 - TRIG3_MATCH_TYPE + TRIG4_MATCH_TYPE 1 - V8_1RADIX - Bin + TRIG8_CNT_WIDTH + 0 - V2_1RADIX + V7_RADIX Bin - VALUE13_2 - 0 + TRIG7_EXCLUDE + false - TRIG3_MATCH_UNIT - 1 + TRIG_MU_EN0 + false - TRIG_SEQ_NEG11 + STOR_MU_NEG9 false - TU12_FUNCTION + TU4_FUNCTION 000 - TU11_CNT_MODE - 00 + VALUE9_1 + 0 - TRIG15_EXCLUDE - false + TRIG_SEQ_LEVEL + 1 - TU15_FUNCTION - 000 + TRIG5_PORT_WIDTH + 8 - TRIG_MU_NEG10 - false + VALUE1_2 + 0 - TU3_CNT_MODE - 00 + VALUE8_2 + 0 - TRIG_SEQ_NEG9 - false + TRIG_SEQ_SEL2 + 0 - INIT_M15_CONFIG + VALUE5_2 0 - INIT_STOR_TYPE - 19'b0000000000000000000 + TRIG0_PORT_WIDTH + 7 - V10_RADIX - Bin + STOR_NEG_WHOLE + false - TRIG10_MATCH_TYPE - 1 + TRIG_SEQ_NEG6 + false - V5_1RADIX + V4_2RADIX Bin - TRIG_MU_EN2 - false - - - TRIG9_PORT_WIDTH - 8 + TRIG0_MATCH_UNIT + 1 - VALUE8_1 - 0 + STOR_MU_NEG3 + false - TRIG4_PORT_WIDTH + TRIG10_PORT_WIDTH 8 - TU14_CNT_VALUE + TRIG13_MATCH_UNIT 1 - TRIG_SEQ_NEG3 - false - - - TRIG5_CNT_WIDTH + TRIG_MODE 0 - TU12_CNT_MODE - 00 + STOR_MU_NEG7 + false V5_2RADIX Bin - TRIG4_CNT_WIDTH + VALUE11 0 - ALL_DATA - 1 + TU2_CNT_MODE + 00 - TRIG_PORT_NUM - 2 + V14_RADIX + Bin - TRIG_SEQ_NEG13 + TRIG_MU_NEG4 false - TRIG_SEQ_SEL6 - 0 + V7_2RADIX + Bin - TRIG1_CNT_WIDTH + TRIG11_CNT_WIDTH 0 - TU5_CNT_VALUE + V11_1RADIX + Bin + + + TRIG_SEQ_NEG5 + false + + + TRIG15_MATCH_UNIT 1 - V14_2RADIX - Bin + CLK_EDGE + 1 - TRIG_MU_EN5 + c_Port8_EN false - TRIG12_MATCH_UNIT + TRIG1_MATCH_UNIT 1 - TRIG6_MATCH_UNIT - 1 + V14_2RADIX + Bin - STOR_MU_NEG8 + c_Port3_EN false - TRIG11_PORT_WIDTH - 8 + TRIG_MU_NEG6 + false - TRIG_SEQ_NEG2 + TRIG_SEQ_NEG12 false - V11_2RADIX - Bin + TU13_CNT_VALUE + 1 - TU13_CNT_MODE - 00 + VALUE0_2 + 0 - TRIG_MU_EN14 + TRIG15_EXCLUDE + false + + + STOR_MU_NEG0 false @@ -1581,15 +1581,7 @@ trig0_i input right - 7 - 0 - - - trig1_i - trig1_i - input - right - 7 + 6 0 diff --git a/ipcore/DebugCoreIst/DebugCoreIst.v b/ipcore/DebugCoreIst/DebugCoreIst.v index b345326..ac06322 100644 --- a/ipcore/DebugCoreIst/DebugCoreIst.v +++ b/ipcore/DebugCoreIst/DebugCoreIst.v @@ -17,8 +17,6 @@ module DebugCoreIst trig0_i, //the trigger data for path 0, from user logic. - trig1_i, //the trigger data for path 1, from user logic. - resetn_i //the hw reset from user logic, it would be used for powerup trig. ); @@ -26,7 +24,7 @@ localparam FLA_VERSION = 32'h9001F002; localparam AREA_SPEED = 0; //@IPC int 0,3 -localparam TRIG_PORT_NUM = 2; //@IPC int 1,16 +localparam TRIG_PORT_NUM = 1; //@IPC int 1,16 localparam MAX_SEQ_LEVEL = 1; //@IPC int 1,16 @@ -44,7 +42,7 @@ localparam DATA_SAME_AS_TRIG = 1; //@IPC bool localparam DATA_WIDTH = 1; //@IPC int 1,4096 -localparam TRIG0_PORT_WIDTH = 8; //@IPC int 1,256 +localparam TRIG0_PORT_WIDTH = 7; //@IPC int 1,256 localparam TRIG0_MATCH_UNIT = 1; //@IPC int 1,16 @@ -209,14 +207,14 @@ localparam TRIG15_EXCLUDE = 0; //@IPC bool localparam INIT_ENABLE = 0; //@IPC bool -localparam INIT_TRIG_COND = 6'b000000; //@IPC string @H trigger condition +localparam INIT_TRIG_COND = 3'b000; //@IPC string @H trigger condition // match unit config -localparam INIT_M0_CONFIG = 25'b0010010010010010010010010; //@IPC string @H +localparam INIT_M0_CONFIG = 22'b0010010010010010010010; //@IPC string @H -localparam INIT_M1_CONFIG = 25'b0010010010010010010010010; //@IPC string @H +localparam INIT_M1_CONFIG = 0; //@IPC string @H localparam INIT_M2_CONFIG = 0; //@IPC string @H @@ -680,7 +678,7 @@ localparam STORE_TYPE_DIV = 1; //@IPC int 1,131072 max 2^17 localparam STORE_POSITION = 0; //@IPC int 0,131072 max 2^17 -localparam INIT_STOR_QUAL = 5'b0; //@IPC string @H +localparam INIT_STOR_QUAL = 2'b0; //@IPC string @H localparam ALL_DATA = 1; //@IPC enum 1,0 @@ -752,7 +750,7 @@ localparam STOR_MU_NEG15 = 0; //@IPC bool localparam c_Port0_EN = 1; //@IPC bool -localparam c_Port1_EN = 1; //@IPC bool +localparam c_Port1_EN = 0; //@IPC bool localparam c_Port2_EN = 0; //@IPC bool @@ -797,8 +795,6 @@ localparam c_Port15_EN = 0; //@IPC bool input trig0_i; //the trigger data for path 0, from user logic. - input trig1_i; //the trigger data for path 1, from user logic. - input resetn_i; //the hw reset from user logic, it would be used for powerup trig. wire drck_in; diff --git a/ipcore/DebugCoreIst/DebugCoreIst_tmpl.v b/ipcore/DebugCoreIst/DebugCoreIst_tmpl.v index 5a296e2..47638c4 100644 --- a/ipcore/DebugCoreIst/DebugCoreIst_tmpl.v +++ b/ipcore/DebugCoreIst/DebugCoreIst_tmpl.v @@ -16,6 +16,5 @@ DebugCoreIst the_instance_name ( .drck_in(drck_in), // input .clk(clk), // input .resetn_i(resetn_i), // input - .trig0_i(trig0_i), // input [7:0] - .trig1_i(trig1_i) // input [7:0] + .trig0_i(trig0_i) // input [6:0] ); diff --git a/ipcore/DebugCoreIst/DebugCoreIst_tmpl.vhdl b/ipcore/DebugCoreIst/DebugCoreIst_tmpl.vhdl index 8092ad8..6c21100 100644 --- a/ipcore/DebugCoreIst/DebugCoreIst_tmpl.vhdl +++ b/ipcore/DebugCoreIst/DebugCoreIst_tmpl.vhdl @@ -17,8 +17,7 @@ COMPONENT DebugCoreIst drck_in : IN STD_LOGIC; clk : IN STD_LOGIC; resetn_i : IN STD_LOGIC; - trig0_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - trig1_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0) + trig0_i : IN STD_LOGIC_VECTOR(6 DOWNTO 0) ); END COMPONENT; @@ -34,6 +33,5 @@ the_instance_name : DebugCoreIst drck_in => drck_in, clk => clk, resetn_i => resetn_i, - trig0_i => trig0_i, - trig1_i => trig1_i + trig0_i => trig0_i ); diff --git a/ipcore/DebugCoreIst/generate.log b/ipcore/DebugCoreIst/generate.log index 53bbe53..a2660aa 100644 --- a/ipcore/DebugCoreIst/generate.log +++ b/ipcore/DebugCoreIst/generate.log @@ -1,6 +1,6 @@ IP Generator (Version 2021.1-SP7 build 86875) Check out license ... -Start generating at 2024-01-06 22:31 +Start generating at 2024-01-07 14:18 Instance: DebugCoreIst (D:\workspace\fpga_demo\led_test\ipcore\DebugCoreIst\DebugCoreIst.idf) IP: DebugCore (1.3) Part: Logos-PGL22G-MBG324--6 diff --git a/ipcore/SPLL/.last_generated b/ipcore/SPLL/.last_generated new file mode 100644 index 0000000..188a96e --- /dev/null +++ b/ipcore/SPLL/.last_generated @@ -0,0 +1,2 @@ +2024-01-07 14:25 +rev_1 \ No newline at end of file diff --git a/ipcore/SPLL/SPLL.idf b/ipcore/SPLL/SPLL.idf new file mode 100644 index 0000000..cd0dfb5 --- /dev/null +++ b/ipcore/SPLL/SPLL.idf @@ -0,0 +1,663 @@ + + +
+ Pango + 021001 + PLL + Logos PLL + 1.5 + SPLL + Logos + PGL22G + MBG324 + -6 + IP Compiler +
+ + + CLKOUT4_REQ_PHASE_basicPage + 0.0000 + 4 + + + CLKOUT3_REQ_FREQ_basicPage + 50.0000 + 4 + + + STATIC_PHASE4_advancedPage + 16 + + + DYNAMIC_RATIOI_EN_advancedPage + false + + + CLKOUT4_EN_basicPage + false + + + STATIC_DUTY0_advancedPage + 16 + + + STATIC_DUTY3_basicPage + 16 + + + CLKOUT0_GATE_EN_basicPage + false + + + CLKIN_SEL_EN_ENABLE_basicPage + false + + + CLKOUT0_EXT_EN_advancedPage + false + + + DYNAMIC_RATIO0_EN_advancedPage + false + + + DYNAMIC_CLKIN_EN_basicPage + false + + + DYNAMIC_RATIOM_EN_advancedPage + false + + + CLKOUT2_GATE_EN_advancedPage + false + + + CLKOUT0_REQ_DUTY_basicPage + 50.0000 + 4 + + + STATIC_RATIO0_basicPage + 24 + + + CLK_CAS4_EN_basicPage + false + + + CLKOUT4_REQ_FREQ_basicPage + 50.0000 + 4 + + + DYNAMIC_PHASE_EN_advancedPage + false + + + DYNAMIC_RATIO4_EN_advancedPage + false + + + DYNAMIC_PHASE1_EN_advancedPage + false + + + STATIC_RATIO2_basicPage + 120 + + + CLK_CAS2_EN_basicPage + false + + + CLKOUT2_REQ_DUTY_basicPage + 50.0000 + 4 + + + STATIC_RATIO3_advancedPage + 16 + + + DEVICE_PGL35 + false + + + STATIC_RATIO4_basicPage + 16 + + + FB_MODE_basicPage + 0 + + + CLKOUT4_GATE_EN_basicPage + false + + + STATIC_PHASE3_advancedPage + 16 + + + STATIC_PHASE4_basicPage + 16 + + + CLKOUT2_REQ_FREQ_basicPage + 5.0000 + 4 + + + CLKOUT1_REQ_DUTY_basicPage + 50.0000 + 4 + + + PLL_PWD_ENABLE_basicPage + false + + + DYNAMIC_DUTY1_EN_advancedPage + false + + + CLKOUT3_GATE_EN_basicPage + false + + + CLKOUT0_EN_advancedPage + true + + + STATIC_DUTY2_advancedPage + 16 + + + CLKOUT5_EN_advancedPage + false + + + CLK_CAS3_EN_basicPage + false + + + DYNAMIC_RATIO3_EN_advancedPage + false + + + CLKOUT3_GATE_EN_advancedPage + false + + + CLKSWITCH_FLAG_ENABLE_basicPage + false + + + STATIC_RATIO3_basicPage + 16 + + + DYNAMIC_DUTY0_EN_advancedPage + false + + + STATIC_PHASE1_basicPage + 16 + + + CLKOUT5_SEL_advancedPage + 0 + + + CLKOUT0_REQ_PHASE_basicPage + 0.0000 + 4 + + + CLK_CAS3_EN_advancedPage + false + + + CLKOUT0_EXT_EN_basicPage + false + + + CLKOUT4_GATE_EN_advancedPage + false + + + STATIC_DUTY1_basicPage + 60 + + + BANDWIDTH_advancedPage + OPTIMIZED + + + CLKOUT2_GATE_EN_basicPage + false + + + BANDWIDTH_basicPage + OPTIMIZED + + + CLKIN_SEL_ENABLE_advancedPage + false + + + CLKIN_FREQ_basicPage + 50.0000 + 4 + + + STATIC_RATIOF_basicPage + 24 + + + STATIC_DUTY2_basicPage + 120 + + + STATIC_RATIOM_advancedPage + 1 + + + CLKOUT3_EN_basicPage + false + + + MODE + false + + + FBMODE_basicPage + false + + + CLKOUT5_GATE_EN_advancedPage + false + + + CLKIN_SEL_EN_ENABLE_advancedPage + false + + + MODE_CFG + 0 + + + FEEDBACK_DELAY_VALUE_basicPage + 0.000 + 3 + + + RST_ENABLE_advancedPage + false + + + DYNAMIC_DUTY3_EN_advancedPage + false + + + STATIC_RATIOF_advancedPage + 16 + + + CLKOUT2_EN_basicPage + true + + + STATIC_DUTY4_basicPage + 16 + + + CLKSWITCH_FLAG_ENABLE_advancedPage + false + + + FEEDBACK_DELAY_ENABLE_advancedPage + false + + + CLKOUT3_REQ_DUTY_basicPage + 50.0000 + 4 + + + FBMODE_advancedPage + false + + + RST_ENABLE_basicPage + false + + + FEEDBACK_DELAY_VALUE_advancedPage + 0.000 + 3 + + + STATIC_DUTY0_basicPage + 24 + + + STATIC_RATIO0_advancedPage + 16 + + + DYNAMIC_RATIO2_EN_advancedPage + false + + + CLKOUT1_EN_advancedPage + false + + + DYNAMIC_DUTY2_EN_advancedPage + false + + + VCODIV2_ENABLE_advancedPage + false + + + DYNAMIC_PHASE4_EN_advancedPage + false + + + STATIC_PHASE0_basicPage + 16 + + + CLK_CAS1_EN_advancedPage + false + + + DYNAMIC_PHASE2_EN_advancedPage + false + + + CLKOUT1_REQ_FREQ_basicPage + 10.0000 + 4 + + + CLKIN_BYPASS_EN_advancedPage + false + + + DYNAMIC_RATIOF_EN_advancedPage + false + + + CLKOUT1_REQ_PHASE_basicPage + 0.0000 + 4 + + + CLKOUT4_EN_advancedPage + false + + + PFDEN_EN_advancedPage + false + + + STATIC_PHASE2_basicPage + 16 + + + DYNAMIC_CLKIN_EN_advancedPage + false + + + CLKOUT2_EN_advancedPage + false + + + STATIC_PHASE0_advancedPage + 16 + + + STATIC_RATIO1_advancedPage + 16 + + + RSTODIV_ENABLE_advancedPage + false + + + STATIC_DUTYF_basicPage + 24 + + + CLKOUT1_GATE_EN_basicPage + false + + + DYNAMIC_LOOP_EN_advancedPage + false + + + CLKOUT3_EN_advancedPage + false + + + CLKOUT3_REQ_PHASE_basicPage + 0.0000 + 4 + + + LOOP_MAPPING_EN_advancedPage + false + + + PLL_PWD_ENABLE_advancedPage + false + + + STATIC_DUTY4_advancedPage + 16 + + + CLKOUT1_GATE_EN_advancedPage + false + + + CLKOUT4_REQ_DUTY_basicPage + 50.0000 + 4 + + + STATIC_PHASE2_advancedPage + 16 + + + DYNAMIC_DUTY4_EN_advancedPage + false + + + FEEDBACK_DELAY_ENABLE_basicPage + false + + + DYNAMIC_RATIO1_EN_advancedPage + false + + + STATIC_RATIOI_advancedPage + 2 + + + CLKOUT0_EN_basicPage + true + + + CLKOUT2_REQ_PHASE_basicPage + 0.0000 + 4 + + + STATIC_DUTY1_advancedPage + 16 + + + FBDIV_SEL_basicPage + 0 + + + STATIC_RATIOM_basicPage + 1 + + + DEVICE_PGL22 + true + + + CLKOUT0_EXT_GATE_EN_advancedPage + false + + + SHOW_SETTING_EN_basicPage + false + + + CLK_CAS4_EN_advancedPage + false + + + STATIC_RATIOI_basicPage + 2 + + + FB_MODE_advancedPage + 0 + + + CLKIN_SEL_ENABLE_basicPage + false + + + CLKOUT0_EXT_GATE_EN_basicPage + false + + + STATIC_PHASE3_basicPage + 16 + + + STATIC_RATIO2_advancedPage + 16 + + + CLKOUT0_GATE_EN_advancedPage + false + + + CLKOUT1_EN_basicPage + true + + + CLKOUT0_REQ_FREQ_basicPage + 25.0000 + 4 + + + STATIC_DUTY3_advancedPage + 16 + + + CLK_CAS2_EN_advancedPage + false + + + FBDIV_SEL_advancedPage + 0 + + + CLKIN_FREQ_advancedPage + 50.0000 + 4 + + + STATIC_PHASE1_advancedPage + 16 + + + CLK_CAS1_EN_basicPage + false + + + STATIC_RATIO4_advancedPage + 16 + + + DYNAMIC_PHASE3_EN_advancedPage + false + + + CLKIN_BYPASS_EN_basicPage + false + + + STATIC_RATIO1_basicPage + 60 + + + DEVICE_PGL12 + false + + + DYNAMIC_PHASE0_EN_advancedPage + false + + + + + clkin1 + clkin1 + input + left + + + pll_lock + pll_lock + output + right + + + clkout0 + clkout0 + output + right + + + clkout1 + clkout1 + output + right + + + clkout2 + clkout2 + output + right + + + + + + + + + + + + + + + + + diff --git a/ipcore/SPLL/SPLL.v b/ipcore/SPLL/SPLL.v new file mode 100644 index 0000000..c71a4d2 --- /dev/null +++ b/ipcore/SPLL/SPLL.v @@ -0,0 +1,299 @@ +// Created by IP Generator (Version 2021.1-SP7 build 86875) + + + +////////////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2019 PANGO MICROSYSTEMS, INC +// ALL RIGHTS REVERVED. +// +// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC. +// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY +// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER. +// +////////////////////////////////////////////////////////////////////////////// +// +// Library: +// Filename:SPLL.v +////////////////////////////////////////////////////////////////////////////// + +module SPLL ( + clkin1, + clkout0, + clkout1, + clkout2, + + pll_lock + ); + + localparam real CLKIN_FREQ = 50.0; + localparam integer STATIC_RATIOI = 2; + localparam integer STATIC_RATIO0 = 24; + localparam integer STATIC_RATIO1 = 60; + localparam integer STATIC_RATIO2 = 120; + localparam integer STATIC_RATIO3 = 16; + localparam integer STATIC_RATIO4 = 16; + localparam integer STATIC_RATIOF = 24; + localparam integer STATIC_DUTY0 = 24; + localparam integer STATIC_DUTY1 = 60; + localparam integer STATIC_DUTY2 = 120; + localparam integer STATIC_DUTY3 = 16; + localparam integer STATIC_DUTY4 = 16; + localparam integer STATIC_DUTYF = 24; + localparam integer STATIC_PHASE0 = 16; + localparam integer STATIC_PHASE1 = 16; + localparam integer STATIC_PHASE2 = 16; + localparam integer STATIC_PHASE3 = 16; + localparam integer STATIC_PHASE4 = 16; + localparam CLK_CAS1_EN = "FALSE"; + localparam CLK_CAS2_EN = "FALSE"; + localparam CLK_CAS3_EN = "FALSE"; + localparam CLK_CAS4_EN = "FALSE"; + localparam CLKIN_BYPASS_EN = "FALSE"; + localparam CLKOUT0_GATE_EN = "FALSE"; + localparam CLKOUT0_EXT_GATE_EN = "FALSE"; + localparam CLKOUT1_GATE_EN = "FALSE"; + localparam CLKOUT2_GATE_EN = "FALSE"; + localparam CLKOUT3_GATE_EN = "FALSE"; + localparam CLKOUT4_GATE_EN = "FALSE"; + localparam FBMODE = "FALSE"; + localparam integer FBDIV_SEL = 0; + localparam BANDWIDTH = "OPTIMIZED"; + localparam PFDEN_EN = "FALSE"; + localparam VCOCLK_DIV2 = 1'b0; + localparam DYNAMIC_RATIOI_EN = "FALSE"; + localparam DYNAMIC_RATIO0_EN = "FALSE"; + localparam DYNAMIC_RATIO1_EN = "FALSE"; + localparam DYNAMIC_RATIO2_EN = "FALSE"; + localparam DYNAMIC_RATIO3_EN = "FALSE"; + localparam DYNAMIC_RATIO4_EN = "FALSE"; + localparam DYNAMIC_RATIOF_EN = "FALSE"; + localparam DYNAMIC_DUTY0_EN = "FALSE"; + localparam DYNAMIC_DUTY1_EN = "FALSE"; + localparam DYNAMIC_DUTY2_EN = "FALSE"; + localparam DYNAMIC_DUTY3_EN = "FALSE"; + localparam DYNAMIC_DUTY4_EN = "FALSE"; + localparam DYNAMIC_DUTYF_EN = "FALSE"; + localparam PHASE_ADJUST0_EN = "TRUE"; + localparam PHASE_ADJUST1_EN = (CLK_CAS1_EN == "TRUE") ? "FALSE" : "TRUE"; + localparam PHASE_ADJUST2_EN = (CLK_CAS2_EN == "TRUE") ? "FALSE" : "TRUE"; + localparam PHASE_ADJUST3_EN = (CLK_CAS3_EN == "TRUE") ? "FALSE" : "TRUE"; + localparam PHASE_ADJUST4_EN = (CLK_CAS4_EN == "TRUE") ? "FALSE" : "TRUE"; + localparam DYNAMIC_PHASE0_EN = "FALSE"; + localparam DYNAMIC_PHASE1_EN = "FALSE"; + localparam DYNAMIC_PHASE2_EN = "FALSE"; + localparam DYNAMIC_PHASE3_EN = "FALSE"; + localparam DYNAMIC_PHASE4_EN = "FALSE"; + localparam DYNAMIC_PHASEF_EN = "FALSE"; + localparam integer STATIC_PHASEF = 16; + localparam CLK_CAS0_EN = "FALSE"; + localparam integer CLKOUT5_SEL = 0; + localparam CLKOUT5_GATE_EN = "FALSE"; + localparam INTERNAL_FB = (FBMODE == "FALSE") ? "ENABLE":"DISABLE"; + localparam EXTERNAL_FB = (FBMODE == "FALSE") ? "DISABLE": + (FBDIV_SEL == 0) ? "CLKOUT0": + (FBDIV_SEL == 1) ? "CLKOUT1": + (FBDIV_SEL == 2) ? "CLKOUT2": + (FBDIV_SEL == 3) ? "CLKOUT3": + (FBDIV_SEL == 4) ? "CLKOUT4":"DISABLE"; + localparam RSTODIV_ENABLE = "FALSE"; + localparam SIM_DEVICE = "PGL22G"; + + input clkin1; + output clkout0; + output clkout1; + output clkout2; + + output pll_lock; + + wire clkout0; + wire clkout0_2pad; + wire clkout1; + wire clkout2; + wire clkout3; + wire clkout4; + wire clkout5; + wire clkswitch_flag; + wire pll_lock; + wire clkin1; + wire clkin2; + wire clkfb; + wire clkin_sel; + wire clkin_sel_en; + wire pfden; + wire clkout0_gate; + wire clkout0_2pad_gate; + wire clkout1_gate; + wire clkout2_gate; + wire clkout3_gate; + wire clkout4_gate; + wire clkout5_gate; + wire [9:0] dyn_idiv; + wire [9:0] dyn_odiv0; + wire [9:0] dyn_odiv1; + wire [9:0] dyn_odiv2; + wire [9:0] dyn_odiv3; + wire [9:0] dyn_odiv4; + wire [9:0] dyn_fdiv; + wire [9:0] dyn_duty0; + wire [9:0] dyn_duty1; + wire [9:0] dyn_duty2; + wire [9:0] dyn_duty3; + wire [9:0] dyn_duty4; + wire [12:0] dyn_phase0; + wire [12:0] dyn_phase1; + wire [12:0] dyn_phase2; + wire [12:0] dyn_phase3; + wire [12:0] dyn_phase4; + wire pll_pwd; + wire pll_rst; + wire rstodiv; + wire icp_base; + wire [3:0] icp_sel; + wire [2:0] lpfres_sel; + wire cripple_sel; + wire [2:0] phase_sel; + wire phase_dir; + wire phase_step_n; + wire load_phase; + wire [6:0] dyn_mdiv; + + assign clkin2 = 1'b0; + assign clkin_sel = 1'b0; + assign clkin_sel_en = 1'b0; + + assign pll_pwd = 1'b0; + + assign pll_rst = 1'b0; + + assign rstodiv = 1'b0; + +GTP_PLL_E1 #( + .CLKIN_FREQ(CLKIN_FREQ), + .PFDEN_EN(PFDEN_EN), + .VCOCLK_DIV2(VCOCLK_DIV2), + .DYNAMIC_RATIOI_EN(DYNAMIC_RATIOI_EN), + + .DYNAMIC_RATIO0_EN(DYNAMIC_RATIO0_EN), + .DYNAMIC_RATIO1_EN(DYNAMIC_RATIO1_EN), + .DYNAMIC_RATIO2_EN(DYNAMIC_RATIO2_EN), + .DYNAMIC_RATIO3_EN(DYNAMIC_RATIO3_EN), + .DYNAMIC_RATIO4_EN(DYNAMIC_RATIO4_EN), + .DYNAMIC_RATIOF_EN(DYNAMIC_RATIOF_EN), + .STATIC_RATIOI(STATIC_RATIOI), + + .STATIC_RATIO0(STATIC_RATIO0), + .STATIC_RATIO1(STATIC_RATIO1), + .STATIC_RATIO2(STATIC_RATIO2), + .STATIC_RATIO3(STATIC_RATIO3), + .STATIC_RATIO4(STATIC_RATIO4), + .STATIC_RATIOF(STATIC_RATIOF), + .DYNAMIC_DUTY0_EN(DYNAMIC_DUTY0_EN), + .DYNAMIC_DUTY1_EN(DYNAMIC_DUTY1_EN), + .DYNAMIC_DUTY2_EN(DYNAMIC_DUTY2_EN), + .DYNAMIC_DUTY3_EN(DYNAMIC_DUTY3_EN), + .DYNAMIC_DUTY4_EN(DYNAMIC_DUTY4_EN), + .DYNAMIC_DUTYF_EN(DYNAMIC_DUTYF_EN), + .STATIC_DUTY0(STATIC_DUTY0), + .STATIC_DUTY1(STATIC_DUTY1), + .STATIC_DUTY2(STATIC_DUTY2), + .STATIC_DUTY3(STATIC_DUTY3), + .STATIC_DUTY4(STATIC_DUTY4), + .STATIC_DUTYF(STATIC_DUTYF), + .PHASE_ADJUST0_EN(PHASE_ADJUST0_EN), + .PHASE_ADJUST1_EN(PHASE_ADJUST1_EN), + .PHASE_ADJUST2_EN(PHASE_ADJUST2_EN), + .PHASE_ADJUST3_EN(PHASE_ADJUST3_EN), + .PHASE_ADJUST4_EN(PHASE_ADJUST4_EN), + .DYNAMIC_PHASE0_EN(DYNAMIC_PHASE0_EN), + .DYNAMIC_PHASE1_EN(DYNAMIC_PHASE1_EN), + .DYNAMIC_PHASE2_EN(DYNAMIC_PHASE2_EN), + .DYNAMIC_PHASE3_EN(DYNAMIC_PHASE3_EN), + .DYNAMIC_PHASE4_EN(DYNAMIC_PHASE4_EN), + .DYNAMIC_PHASEF_EN(DYNAMIC_PHASEF_EN), + .STATIC_PHASE0(STATIC_PHASE0[2:0]), + .STATIC_PHASE1(STATIC_PHASE1[2:0]), + .STATIC_PHASE2(STATIC_PHASE2[2:0]), + .STATIC_PHASE3(STATIC_PHASE3[2:0]), + .STATIC_PHASE4(STATIC_PHASE4[2:0]), + .STATIC_PHASEF(STATIC_PHASEF[2:0]), + .STATIC_CPHASE0(STATIC_PHASE0[12:3]), + .STATIC_CPHASE1(STATIC_PHASE1[12:3]), + .STATIC_CPHASE2(STATIC_PHASE2[12:3]), + .STATIC_CPHASE3(STATIC_PHASE3[12:3]), + .STATIC_CPHASE4(STATIC_PHASE4[12:3]), + .STATIC_CPHASEF(STATIC_PHASEF[12:3]), + .CLK_CAS0_EN(CLK_CAS0_EN), + .CLK_CAS1_EN(CLK_CAS1_EN), + .CLK_CAS2_EN(CLK_CAS2_EN), + .CLK_CAS3_EN(CLK_CAS3_EN), + .CLK_CAS4_EN(CLK_CAS4_EN), + .CLKOUT5_SEL(CLKOUT5_SEL), + .CLKIN_BYPASS_EN(CLKIN_BYPASS_EN), + .CLKOUT0_SYN_EN(CLKOUT0_GATE_EN), + .CLKOUT0_EXT_SYN_EN(CLKOUT0_EXT_GATE_EN), + .CLKOUT1_SYN_EN(CLKOUT1_GATE_EN), + .CLKOUT2_SYN_EN(CLKOUT2_GATE_EN), + .CLKOUT3_SYN_EN(CLKOUT3_GATE_EN), + .CLKOUT4_SYN_EN(CLKOUT4_GATE_EN), + .CLKOUT5_SYN_EN(CLKOUT5_GATE_EN), + .INTERNAL_FB(INTERNAL_FB), + .EXTERNAL_FB(EXTERNAL_FB), + .RSTODIV_PHASE_EN(RSTODIV_ENABLE), + .SIM_DEVICE(SIM_DEVICE), + .BANDWIDTH(BANDWIDTH) + ) u_pll_e1 ( + .CLKOUT0(clkout0), + .CLKOUT0_EXT(clkout0_2pad), + .CLKOUT1(clkout1), + .CLKOUT2(clkout2), + .CLKOUT3(clkout3), + .CLKOUT4(clkout4), + .CLKOUT5(clkout5), + .CLKSWITCH_FLAG(clkswitch_flag), + .LOCK(pll_lock), + .CLKIN1(clkin1), + .CLKIN2(clkin2), + .CLKFB(clkfb), + .CLKIN_SEL(clkin_sel), + .CLKIN_SEL_EN(clkin_sel_en), + .PFDEN(pfden), + + .RATIOI(dyn_idiv), + .RATIO0(dyn_odiv0), + .RATIO1(dyn_odiv1), + .RATIO2(dyn_odiv2), + .RATIO3(dyn_odiv3), + .RATIO4(dyn_odiv4), + .RATIOF(dyn_fdiv), + .DUTY0(dyn_duty0), + .DUTY1(dyn_duty1), + .DUTY2(dyn_duty2), + .DUTY3(dyn_duty3), + .DUTY4(dyn_duty4), + .DUTYF(), + .PHASE0(dyn_phase0[2:0]), + .PHASE1(dyn_phase1[2:0]), + .PHASE2(dyn_phase2[2:0]), + .PHASE3(dyn_phase3[2:0]), + .PHASE4(dyn_phase4[2:0]), + .PHASEF(), + .CPHASE0(dyn_phase0[12:3]), + .CPHASE1(dyn_phase1[12:3]), + .CPHASE2(dyn_phase2[12:3]), + .CPHASE3(dyn_phase3[12:3]), + .CPHASE4(dyn_phase4[12:3]), + .CPHASEF(), + .CLKOUT0_SYN(clkout0_gate), + .CLKOUT0_EXT_SYN(clkout0_2pad_gate), + .CLKOUT1_SYN(clkout1_gate), + .CLKOUT2_SYN(clkout2_gate), + .CLKOUT3_SYN(clkout3_gate), + .CLKOUT4_SYN(clkout4_gate), + .CLKOUT5_SYN(clkout5_gate), + .PLL_PWD(pll_pwd), + .RST(pll_rst), + .RSTODIV_PHASE(rstodiv) + ); + +endmodule diff --git a/ipcore/SPLL/SPLL_tb.v b/ipcore/SPLL/SPLL_tb.v new file mode 100644 index 0000000..60dd5fe --- /dev/null +++ b/ipcore/SPLL/SPLL_tb.v @@ -0,0 +1,254 @@ +// Created by IP Generator (Version 2021.1-SP7 build 86875) + + + +////////////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2019 PANGO MICROSYSTEMS, INC +// ALL RIGHTS REVERVED. +// +// THE SOURCE CODE CONTAINED HEREIN IS PROPRIETARY TO PANGO MICROSYSTEMS, INC. +// IT SHALL NOT BE REPRODUCED OR DISCLOSED IN WHOLE OR IN PART OR USED BY +// PARTIES WITHOUT WRITTEN AUTHORIZATION FROM THE OWNER. +// +////////////////////////////////////////////////////////////////////////////// +// +// Library: +// Filename:SPLL.v +////////////////////////////////////////////////////////////////////////////// +`timescale 1 ns/1 ps + +module SPLL_tb (); + +localparam CLKIN_FREQ = 50.0; +localparam integer FBDIV_SEL = 0; +localparam FBMODE = "FALSE"; + + +// Generate testbench reset and clock +reg pll_rst; +reg rstodiv; +reg pll_pwd; +reg clkin1; +reg clkin2; +reg clkin_dsel; +reg clkin_dsel_en; +reg pfden; +reg clkout0_gate; +reg clkout0_2pad_gate; +reg clkout1_gate; +reg clkout2_gate; +reg clkout3_gate; +reg clkout4_gate; +reg clkout5_gate; +reg [9:0] dyn_idiv; +reg [9:0] dyn_odiv0; +reg [9:0] dyn_odiv1; +reg [9:0] dyn_odiv2; +reg [9:0] dyn_odiv3; +reg [9:0] dyn_odiv4; +reg [9:0] dyn_fdiv; +reg [9:0] dyn_duty0; +reg [9:0] dyn_duty1; +reg [9:0] dyn_duty2; +reg [9:0] dyn_duty3; +reg [9:0] dyn_duty4; +reg [12:0] dyn_phase0; +reg [12:0] dyn_phase1; +reg [12:0] dyn_phase2; +reg [12:0] dyn_phase3; +reg [12:0] dyn_phase4; +reg err_chk; +reg [2:0] results_cnt; + +reg rst_n; +reg clk_tb; + +wire clkout0; +wire clkout1; +wire clkout2; +wire clkout3; +wire clkout4; +wire clkfb = (FBMODE == "FALSE") ? clkin1 : + (FBDIV_SEL == 0 ) ? clkout0 : + (FBDIV_SEL == 1 ) ? clkout1 : + (FBDIV_SEL == 2 ) ? clkout2 : + (FBDIV_SEL == 3 ) ? clkout3 : + (FBDIV_SEL == 4 ) ? clkout4 : clkin1; + + +initial +begin + rst_n = 0; + #20 + rst_n = 1; +end + +initial +begin + clk_tb = 0; + forever #1 clk_tb = ~clk_tb; +end + +parameter CLOCK_PERIOD1 = (500.0/CLKIN_FREQ); +//parameter CLOCK_PERIOD2 = (500.0/CLKIN_FREQ); + +initial +begin + clkin1 = 0; + forever #(CLOCK_PERIOD1) clkin1 = ~clkin1; +end + + +initial +begin + pll_pwd = 0; + pll_rst = 0; + rstodiv = 0; + clkin_dsel = 0; + clkin_dsel_en = 0; + pfden = 0; + clkout0_gate = 0; + clkout0_2pad_gate = 0; + clkout1_gate = 0; + clkout2_gate = 0; + clkout3_gate = 0; + clkout4_gate = 0; + clkout5_gate = 0; + dyn_idiv = 10'd2; + dyn_fdiv = 10'd32; + dyn_odiv0 = 10'd100; + dyn_odiv1 = 10'd100; + dyn_odiv2 = 10'd100; + dyn_odiv3 = 10'd100; + dyn_odiv4 = 10'd100; + dyn_duty0 = 10'd100; + dyn_duty1 = 10'd100; + dyn_duty2 = 10'd100; + dyn_duty3 = 10'd100; + dyn_duty4 = 10'd100; + dyn_phase0 = 13'd16; + dyn_phase1 = 13'd16; + dyn_phase2 = 13'd16; + dyn_phase3 = 13'd16; + dyn_phase4 = 13'd16; + + #10 + pll_pwd = 1; + #20 + pll_pwd = 0; + + pll_rst = 0; + #10 + pll_rst = 1; + #20 + pll_rst = 0; + + #1000000 + dyn_odiv0 = 10'd200; + dyn_odiv1 = 10'd200; + dyn_odiv2 = 10'd200; + dyn_odiv3 = 10'd200; + dyn_odiv4 = 10'd200; + dyn_duty0 = 10'd200; + dyn_duty1 = 10'd200; + dyn_duty2 = 10'd200; + dyn_duty3 = 10'd200; + dyn_duty4 = 10'd200; + #3000000 + $finish; +end + +initial +begin + $display("Simulation Starts.") ; + $display("Simulation is done.") ; + if (|results_cnt) + $display("Simulation Failed due to Error Found.") ; + else + $display("Simulation Success.") ; +end + + +GTP_GRS GRS_INST( + .GRS_N(1'b1) + ); + +SPLL U_SPLL ( +.clkout0(clkout0), + .clkout1(clkout1), + .clkout2(clkout2), + + .clkin1(clkin1), + + .pll_lock(pll_lock) + ); + + +//******************Results Cheching************************ + +reg [2:0] pll_lock_shift; +wire pll_lock_pulse = ~pll_lock_shift[2] & pll_lock_shift[1]; +always @( posedge clk_tb or negedge rst_n ) +begin + if (!rst_n) + begin + pll_lock_shift <= 3'd0; + end + else + begin + pll_lock_shift[0] <= pll_lock; + pll_lock_shift[2:1] <= pll_lock_shift[1:0]; + end +end + +reg [1:0] pll_lock_pulse_cnt; +always @( posedge clk_tb or negedge rst_n ) +begin + if (!rst_n) + begin + pll_lock_pulse_cnt <= 2'd0; + end + else + begin + if (pll_lock_pulse) + pll_lock_pulse_cnt <= pll_lock_pulse_cnt + 1; + else ; + end +end + + +always @( posedge clk_tb or negedge rst_n ) +begin + if (!rst_n) + begin + err_chk <= 1'b0; + end + else + begin + if ((!pll_lock) && (^pll_lock_pulse_cnt)) + err_chk <= 1'b1; + else if (pll_lock_pulse_cnt[1]) + err_chk <= 1'b1; + else + err_chk <= 1'b0; + end +end +always @(posedge clk_tb or negedge rst_n) +begin + if (!rst_n) + results_cnt <= 3'b000 ; + else if (&results_cnt) + results_cnt <= 3'b100 ; + else if (err_chk) + results_cnt <= results_cnt + 3'd1 ; +end + + +integer result_fid; +initial begin + result_fid = $fopen ("sim_results.log","a"); + $fmonitor(result_fid,"err_chk=%b", err_chk); +end + +endmodule diff --git a/ipcore/SPLL/SPLL_tmpl.v b/ipcore/SPLL/SPLL_tmpl.v new file mode 100644 index 0000000..0d0a436 --- /dev/null +++ b/ipcore/SPLL/SPLL_tmpl.v @@ -0,0 +1,15 @@ +// Created by IP Generator (Version 2021.1-SP7 build 86875) +// Instantiation Template +// +// Insert the following codes into your Verilog file. +// * Change the_instance_name to your own instance name. +// * Change the signal names in the port associations + + +SPLL the_instance_name ( + .clkin1(clkin1), // input + .pll_lock(pll_lock), // output + .clkout0(clkout0), // output + .clkout1(clkout1), // output + .clkout2(clkout2) // output +); diff --git a/ipcore/SPLL/SPLL_tmpl.vhdl b/ipcore/SPLL/SPLL_tmpl.vhdl new file mode 100644 index 0000000..c75c06f --- /dev/null +++ b/ipcore/SPLL/SPLL_tmpl.vhdl @@ -0,0 +1,27 @@ +-- Created by IP Generator (Version 2021.1-SP7 build 86875) +-- Instantiation Template +-- +-- Insert the following codes into your VHDL file. +-- * Change the_instance_name to your own instance name. +-- * Change the net names in the port map. + + +COMPONENT SPLL + PORT ( + clkin1 : IN STD_LOGIC; + pll_lock : OUT STD_LOGIC; + clkout0 : OUT STD_LOGIC; + clkout1 : OUT STD_LOGIC; + clkout2 : OUT STD_LOGIC + ); +END COMPONENT; + + +the_instance_name : SPLL + PORT MAP ( + clkin1 => clkin1, + pll_lock => pll_lock, + clkout0 => clkout0, + clkout1 => clkout1, + clkout2 => clkout2 + ); diff --git a/ipcore/SPLL/generate.log b/ipcore/SPLL/generate.log new file mode 100644 index 0000000..b19aeb5 --- /dev/null +++ b/ipcore/SPLL/generate.log @@ -0,0 +1,17 @@ +IP Generator (Version 2021.1-SP7 build 86875) +Check out license ... +Start generating at 2024-01-07 14:25 +Instance: SPLL (D:\workspace\fpga_demo\led_test\ipcore\SPLL\SPLL.idf) +IP: PLL (1.5) +Part: Logos-PGL22G-MBG324--6 +Create directory 'rtl' ... +Copy 'ipml_pll_wrapper_v1_4.v.xml' ... +Compile file 'ipml_pll_wrapper_v1_4.v.xml' to 'SPLL.v' ... +Found top module 'SPLL' in file 'SPLL.v'. +Copy 'ipml_pll_wrapper_v1_4_tb.v.xml' ... +Compile file 'ipml_pll_wrapper_v1_4_tb.v.xml' to 'SPLL_tb.v' ... +Create template file 'SPLL_tmpl.v' ... +Create template file 'SPLL_tmpl.vhdl' ... +There is 1 source file to synthesize. +Synthesis is disabled. +Done: 0 error(s), 0 warning(s) diff --git a/led_test.fdc b/led_test.fdc index acac9ec..c292cfa 100644 --- a/led_test.fdc +++ b/led_test.fdc @@ -12,3 +12,21 @@ define_attribute {p:core_board_debug_led} {PAP_IO_VCCIO} {3.3} define_attribute {p:core_board_debug_led} {PAP_IO_STANDARD} {LVCMOS33} define_attribute {p:core_board_debug_led} {PAP_IO_DRIVE} {4} define_attribute {p:core_board_debug_led} {PAP_IO_SLEW} {SLOW} +define_attribute {p:spi1_tx_pin} {PAP_IO_DIRECTION} {OUTPUT} +define_attribute {p:spi1_tx_pin} {PAP_IO_LOC} {U13} +define_attribute {p:spi1_tx_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi1_tx_pin} {PAP_IO_STANDARD} {LVCMOS33} +define_attribute {p:spi1_tx_pin} {PAP_IO_DRIVE} {4} +define_attribute {p:spi1_tx_pin} {PAP_IO_SLEW} {SLOW} +define_attribute {p:spi1_clk_pin} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:spi1_clk_pin} {PAP_IO_LOC} {V13} +define_attribute {p:spi1_clk_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi1_clk_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:spi1_cs_pin} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:spi1_cs_pin} {PAP_IO_LOC} {V14} +define_attribute {p:spi1_cs_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi1_cs_pin} {PAP_IO_STANDARD} {LVTTL33} +define_attribute {p:spi1_rx_pin} {PAP_IO_DIRECTION} {INPUT} +define_attribute {p:spi1_rx_pin} {PAP_IO_LOC} {U14} +define_attribute {p:spi1_rx_pin} {PAP_IO_VCCIO} {3.3} +define_attribute {p:spi1_rx_pin} {PAP_IO_STANDARD} {LVTTL33} diff --git a/led_test.pds b/led_test.pds index 53a3d69..f26d896 100644 --- a/led_test.pds +++ b/led_test.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2021.1-SP7" - (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Jan 7 13:39:07 2024") + (_comment "Generated by Fabric Compiler (version on 2021.1-SP7) at Sun Jan 7 14:48:21 2024") (_version "1.0.5") (_status "initial") (_project @@ -27,7 +27,7 @@ ) (_file "source/src/top.v" + "Top:" (_format verilog) - (_timespec "2024-01-07T13:39:05") + (_timespec "2024-01-07T14:48:21") ) (_file "source/src/uart_tx.v" (_format verilog) @@ -47,7 +47,7 @@ ) (_file "source/src/spi_reg_reader.v" (_format verilog) - (_timespec "2023-12-15T22:06:08") + (_timespec "2024-01-07T13:55:23") ) (_file "source/src/src_ttl_parser.v" (_format verilog) @@ -71,7 +71,7 @@ ) (_file "source/src/zutils/zutils_register.v" (_format verilog) - (_timespec "2023-12-31T16:33:39") + (_timespec "2024-01-07T13:59:36") ) (_file "source/src/zutils/zutils_multiplexer_4t1.v" (_format verilog) @@ -81,6 +81,10 @@ (_format verilog) (_timespec "2024-01-06T19:12:28") ) + (_file "source/src/zutils/zutils_signal_filter.v" + (_format verilog) + (_timespec "2024-01-07T13:48:54") + ) ) ) (_widget wgt_my_ips_src @@ -95,7 +99,7 @@ ) ) (_ip "ipcore/DebugCoreIst/DebugCoreIst.idf" - (_timespec "2024-01-06T22:31:25") + (_timespec "2024-01-07T14:18:11") (_ip_source_item "ipcore/DebugCoreIst/rtl/ips_dbc_cfg_reg_file_v1_0.v" (_timespec "2021-12-07T10:55:24") ) @@ -130,7 +134,13 @@ (_timespec "2021-12-07T10:55:24") ) (_ip_source_item "ipcore/DebugCoreIst/DebugCoreIst.v" - (_timespec "2024-01-06T22:31:25") + (_timespec "2024-01-07T14:18:11") + ) + ) + (_ip "ipcore/SPLL/SPLL.idf" + (_timespec "2024-01-07T14:25:26") + (_ip_source_item "ipcore/SPLL/SPLL.v" + (_timespec "2024-01-07T14:25:26") ) ) ) @@ -139,7 +149,7 @@ (_input (_file "led_test.fdc" (_format fdc) - (_timespec "2024-01-06T19:22:21") + (_timespec "2024-01-07T14:16:20") ) ) ) @@ -182,17 +192,17 @@ (_db_output (_file "compile/Top_comp.adf" (_format adif) - (_timespec "2024-01-06T22:31:35") + (_timespec "2024-01-07T14:45:41") ) ) (_output (_file "compile/Top.cmr" (_format verilog) - (_timespec "2024-01-06T22:31:34") + (_timespec "2024-01-07T14:45:40") ) (_file "compile/cmr.db" (_format text) - (_timespec "2024-01-06T22:31:35") + (_timespec "2024-01-07T14:45:41") ) ) ) @@ -208,21 +218,21 @@ (_db_output (_file "synthesize/Top_syn.adf" (_format adif) - (_timespec "2024-01-06T22:31:39") + (_timespec "2024-01-07T14:45:44") ) ) (_output (_file "synthesize/Top_syn.vm" (_format structural_verilog) - (_timespec "2024-01-06T22:31:39") + (_timespec "2024-01-07T14:45:44") ) (_file "synthesize/Top.snr" (_format text) - (_timespec "2024-01-06T22:31:39") + (_timespec "2024-01-07T14:45:44") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2024-01-06T22:31:39") + (_timespec "2024-01-07T14:45:44") ) ) ) @@ -243,21 +253,21 @@ (_db_output (_file "device_map/Top_map.adf" (_format adif) - (_timespec "2024-01-06T22:31:41") + (_timespec "2024-01-07T14:45:47") ) ) (_output (_file "device_map/Top_dmr.prt" (_format text) - (_timespec "2024-01-06T22:31:41") + (_timespec "2024-01-07T14:45:47") ) (_file "device_map/Top.dmr" (_format text) - (_timespec "2024-01-06T22:31:41") + (_timespec "2024-01-07T14:45:47") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2024-01-06T22:31:41") + (_timespec "2024-01-07T14:45:47") ) ) ) @@ -266,7 +276,7 @@ (_input (_file "device_map/led_test.pcf" (_format pcf) - (_timespec "2024-01-06T22:31:41") + (_timespec "2024-01-07T14:45:47") ) ) ) @@ -280,33 +290,33 @@ (_db_output (_file "place_route/Top_pnr.adf" (_format adif) - (_timespec "2024-01-06T22:31:50") + (_timespec "2024-01-07T14:45:55") ) ) (_output (_file "place_route/Top.prr" (_format text) - (_timespec "2024-01-06T22:31:50") + (_timespec "2024-01-07T14:45:55") ) (_file "place_route/Top_prr.prt" (_format text) - (_timespec "2024-01-06T22:31:50") + (_timespec "2024-01-07T14:45:55") ) (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2024-01-06T22:31:50") + (_timespec "2024-01-07T14:45:55") ) (_file "place_route/Top_plc.adf" (_format adif) - (_timespec "2024-01-06T22:31:48") + (_timespec "2024-01-07T14:45:53") ) (_file "place_route/Top_pnr.netlist" (_format text) - (_timespec "2024-01-06T22:31:50") + (_timespec "2024-01-07T14:45:55") ) (_file "place_route/prr.db" (_format text) - (_timespec "2024-01-06T22:31:50") + (_timespec "2024-01-07T14:45:55") ) ) ) @@ -322,17 +332,17 @@ (_db_output (_file "report_timing/Top_rtp.adf" (_format adif) - (_timespec "2024-01-06T22:31:54") + (_timespec "2024-01-07T14:45:59") ) ) (_output (_file "report_timing/Top.rtr" (_format text) - (_timespec "2024-01-06T22:31:54") + (_timespec "2024-01-07T14:45:59") ) (_file "report_timing/rtr.db" (_format text) - (_timespec "2024-01-06T22:31:54") + (_timespec "2024-01-07T14:45:59") ) ) ) @@ -356,19 +366,19 @@ (_output (_file "generate_bitstream/Top.sbit" (_format text) - (_timespec "2024-01-06T22:31:58") + (_timespec "2024-01-07T14:46:04") ) (_file "generate_bitstream/Top.smsk" (_format text) - (_timespec "2024-01-06T22:31:58") + (_timespec "2024-01-07T14:46:04") ) (_file "generate_bitstream/Top.bgr" (_format text) - (_timespec "2024-01-06T22:31:58") + (_timespec "2024-01-07T14:46:04") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2024-01-06T22:31:59") + (_timespec "2024-01-07T14:46:05") ) ) ) diff --git a/source/src/spi_reg_reader.v b/source/src/spi_reg_reader.v index c4f92fa..bb2a907 100644 --- a/source/src/spi_reg_reader.v +++ b/source/src/spi_reg_reader.v @@ -8,9 +8,9 @@ module spi_reg_reader ( output reg wr_en, input wire [31:0] rd_data, //received serial data // - input wire spi_cs_pin, - input wire spi_clk_pin, - input wire spi_rx_pin, + input wire spi_cs_pin, // + input wire spi_clk_pin, // + input wire spi_rx_pin, // output reg spi_tx_pin ); @@ -22,6 +22,30 @@ module spi_reg_reader ( parameter STATE_WRITE_REG = 5; parameter ADDRESS_WIDTH_BYTE_NUM = 2; + zutils_signal_filter #(.FILTER_COUNT(2)) cs_filter ( + .clk(clk), + .rst_n(rst_n), + .in(spi_cs_pin), + .out(spi_cs_pin_after_filter) + ); + + zutils_signal_filter #(.FILTER_COUNT(2)) clk_filter ( + .clk(clk), + .rst_n(rst_n), + .in(spi_clk_pin), + .out(spi_clk_pin_after_filter) + ); + + zutils_signal_filter #(.FILTER_COUNT(2)) spi_rx_filter ( + .clk(clk), + .rst_n(rst_n), + .in(spi_rx_pin), + .out(spi_rx_pin_after_filter) + ); + + + + // // 捕获SPI_CS的下降沿 和 SPI_CLK的上升沿 @@ -32,15 +56,15 @@ module spi_reg_reader ( reg spi_cs_last_state = 0; reg spi_clk_last_state = 0; - assign spi_clk_posedge_tri = spi_clk_pin & ~spi_clk_last_state; - assign spi_clk_negedge_tri = ~spi_clk_pin & spi_clk_last_state; + assign spi_clk_posedge_tri = spi_clk_pin_after_filter & ~spi_clk_last_state; + assign spi_clk_negedge_tri = ~spi_clk_pin_after_filter & spi_clk_last_state; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin spi_cs_last_state <= 1; spi_clk_last_state <= 1; end else begin - spi_cs_last_state <= spi_cs_pin; - spi_clk_last_state <= spi_clk_pin; + spi_cs_last_state <= spi_cs_pin_after_filter; + spi_clk_last_state <= spi_clk_pin_after_filter; end end @@ -76,7 +100,7 @@ module spi_reg_reader ( bit_cnt <= 0; first_edge <= 1; end else begin - if (spi_cs_pin) begin + if (spi_cs_pin_after_filter) begin bit_cnt <= 0; first_edge <= 1; end else begin @@ -105,7 +129,7 @@ module spi_reg_reader ( if (!rst_n) begin spi_byte_cnt <= 0; end else begin - if (spi_cs_pin) begin + if (spi_cs_pin_after_filter) begin spi_byte_cnt <= 0; end else begin if (spi_clk_negedge_tri && bit_cnt == 7) begin @@ -135,13 +159,13 @@ module spi_reg_reader ( spi_rx_1byte_data <= 0; spi_rx_1byte_data_valid <= 0; end else begin - if (spi_cs_pin) begin + if (spi_cs_pin_after_filter) begin spi_rx_1byte_data <= 0; spi_rx_1byte_data_valid <= 0; end else begin if (spi_clk_posedge_tri) begin - spi_rx_1byte_data[bit_cnt] <= spi_rx_pin; + spi_rx_1byte_data[bit_cnt] <= spi_rx_pin_after_filter; end if (spi_clk_negedge_tri && bit_cnt == 7) spi_rx_1byte_data_valid <= 1; @@ -173,7 +197,7 @@ module spi_reg_reader ( spi_rx_data_cache[7] <= 0; end else begin - if (spi_cs_pin) begin + if (spi_cs_pin_after_filter) begin // 失能状态 rx_byte_count <= 0; spi_rx_data_cache[0] <= 0; @@ -268,10 +292,10 @@ module spi_reg_reader ( wr_en <= 0; has_trigger_wr_en <= 0; end else begin - if (spi_cs_pin) begin + if (spi_cs_pin_after_filter) begin wr_en <= 0; has_trigger_wr_en <= 0; - end else if (!spi_cs_pin && // + end else if (!spi_cs_pin_after_filter && // !has_trigger_wr_en && // spi_byte_cnt == ADDRESS_WIDTH_BYTE_NUM + 4 && // spi_rx_data_cache[ADDRESS_WIDTH_BYTE_NUM-1][7]) begin diff --git a/source/src/top.v b/source/src/top.v index c3d6d24..1826af3 100644 --- a/source/src/top.v +++ b/source/src/top.v @@ -7,17 +7,55 @@ module Top ( input wire spi1_cs_pin, input wire spi1_clk_pin, input wire spi1_rx_pin, - output reg spi1_tx_pin, + output wire spi1_tx_pin, //SPI 串行总线2 input wire spi2_cs_pin, input wire spi2_clk_pin, input wire spi2_rx_pin, - output reg spi2_tx_pin, + output wire spi2_tx_pin, output wire core_board_debug_led ); + SPLL spll ( + .clkin1(sys_clk), // input + .pll_lock(pll_lock), // output + .clkout0(sys_clk_25m), // output + .clkout1(sys_clk_10m), // output + .clkout2(sys_clk_5m) // output + ); + + + /******************************************************************************* + * 调试器 * + *******************************************************************************/ + // wire [6:0] trig0_i; + // JtagHubIst jtag_hub_ist ( + // .resetn_i(rst_n), // input + // .drck_o (drck_o), // output + // .hub_tdi (hub_tdi), // output + // .capt_o (capt_o), // output + // .shift_o (shift_o), // output + // .conf_sel(conf_sel), // output [14:0] + // .id_o (id_o), // output [4:0] + // .hub_tdo (hub_tdo) // input [14:0] + // ); + + // DebugCoreIst debug_core_ist ( + // .hub_tdi (hub_tdi), // input + // .hub_tdo (hub_tdo[0]), // output + // .id_i (id_o), // input [4:0] + // .capt_i (capt_o), // input + // .shift_i (shift_o), // input + // .conf_sel(conf_sel[0]), // input + // .drck_in (drck_o), // input + // .clk (sys_clk), // input + // .resetn_i(rst_n), // input + // .trig0_i (trig0_i) + // ); + + /******************************************************************************* * DEBUG_LED * *******************************************************************************/ @@ -37,9 +75,7 @@ module Top ( wire [31:0] reg_reader_bus_wr_data; wire reg_reader_bus_wr_en; wire [31:0] reg_reader_bus_rd_data; - spi_reg_reader #( - .REG_START_ADD(16'h0000) - ) spi1_reg_reader_inst ( + spi_reg_reader spi1_reg_reader_inst ( .clk (sys_clk), .rst_n(rst_n), @@ -57,18 +93,22 @@ module Top ( /******************************************************************************* * TEST_SPI_REG * *******************************************************************************/ - zutils_register16 #( .REG_START_ADD(16'h0020) ) core_board_debug_led_reg ( - .clk (sys_clk), + .clk(sys_clk), .rst_n(rst_n), .addr(reg_reader_bus_addr), .wr_data(reg_reader_bus_wr_data), .wr_en(reg_reader_bus_wr_en), - .rd_data(reg_reader_bus_rd_data), - .reg0(core_board_debug_led) + .rd_data(reg_reader_bus_rd_data) ); + assign trig0_i[0] = sys_clk_5m; + assign trig0_i[1] = spi2_clk_pin; + assign trig0_i[2] = spi1_rx_pin; + assign trig0_i[3] = spi1_tx_pin; + assign trig0_i[4] = spi1_cs_pin; + endmodule diff --git a/source/src/zutils/zutils_register.v b/source/src/zutils/zutils_register.v index c73a467..e07ebd9 100644 --- a/source/src/zutils/zutils_register.v +++ b/source/src/zutils/zutils_register.v @@ -31,7 +31,7 @@ module zutils_register16 #( localparam ADD_NUM = 16; //寄存器数量 parameter REG_END_ADD = REG_START_ADD + ADD_NUM - 1; //寄存器结束地址 - reg [31:0] data[REG_START_ADD:REG_END_ADD]; + reg [31:0] data[0:ADD_NUM]; assign reg0 = data[0]; @@ -58,10 +58,11 @@ module zutils_register16 #( data[i] <= 0; end end else begin - if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) data[addr] <= wr_data; + if (wr_en && addr >= REG_START_ADD && addr <= REG_END_ADD) + data[addr-REG_START_ADD] <= wr_data; end end - assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? data[addr] : 31'bz; + assign rd_data = (addr >= REG_START_ADD && addr <= REG_END_ADD) ? data[addr-REG_START_ADD] : 31'bz; endmodule diff --git a/source/src/zutils/zutils_signal_filter.v b/source/src/zutils/zutils_signal_filter.v new file mode 100644 index 0000000..8db98bf --- /dev/null +++ b/source/src/zutils/zutils_signal_filter.v @@ -0,0 +1,33 @@ +module zutils_signal_filter #( + parameter FILTER_COUNT = 5 +) ( + input clk, //clock input + input rst_n, //asynchronous reset input, low active + input wire in, + output reg out +); + reg [31:0] counter; + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + counter <= 0; + end else begin + if (out != in) begin + counter <= counter + 1; + end else begin + counter <= 0; + end + end + end + + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + out <= in; + end else begin + if (counter == FILTER_COUNT) begin + out <= in; + end else begin + out <= out; + end + end + end +endmodule